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// and manual are owned by Synopsys, Inc., and may be used only as authorized 
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`lmv_timescale


[Up: Msystem u1]
module pcimonitor
  (clk,rstnn,ad,cxbenn,par,framenn,trdynn,irdynn,stopnn,devselnn,idsel,perrnn
   ,serrnn,reqnn,gntnn,locknn,par64,req64nn,ack64nn,sbonn,sdone,intann,intbnn
   ,intcnn,intdnn,disablemsg);

input clk;
input rstnn;
inout [63:0] ad;
inout [7:0] cxbenn;
inout par;
input framenn;
input trdynn;
input irdynn;
input stopnn;
input devselnn;
input [7:0] idsel;
input perrnn;
input serrnn;
input [7:0] reqnn;
inout [7:0] gntnn;
input locknn;
input par64;
input req64nn;
input ack64nn;
input sbonn;
input sdone;
input intann;
input intbnn;
input intcnn;
input intdnn;
input disablemsg;


pcimonitor_fm fm
(clk,rstnn,ad,cxbenn,par,framenn,trdynn,irdynn,stopnn,devselnn,idsel,perrnn
   ,serrnn,reqnn,gntnn,locknn,par64,req64nn,ack64nn,sbonn,sdone,intann,intbnn
   ,intcnn,intdnn,disablemsg);

 //----------------------------------
 //----------------------------------
 //-- This block terminates the    --
 //-- code which will be replaced  --
 //-- by VGEN on future reruns     --
 //-- Enter USER code only after   --
 //-- this comment block           --
 //----------------------------------
 //--**--**--**--**--**--**--**--**--


initial begin : model
 //-------------------------------
 //-------------------------------
 // User model code goes here ----
 //-------------------------------
 //-------------------------------
end // model

endmodule // pcimonitor

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This page: Created:Thu Aug 19 12:00:37 1999
From: ../../../sparc_v8/system/lmc/rtl/pcimonitor.v

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