//
// Copyright Notice and Proprietary Information
//
// Copyright (C) 1992 - 1995 Synopsys, Inc. All rights reserved. This Software
// and manual are owned by Synopsys, Inc., and may be used only as authorized
// in the license agreement controlling such use. No part of this publication
// may be reproduced, transmitted, or translated, in any form or by any means,
// electronic, mechanical, manual, optical, or otherwise, without prior written
// permission of Synopsys, Inc., or as expressly provided by the license agreement.
//
// Destination Control Statement
//
// All technical data contained in this publication is subject to the export
// control laws of the United States of America. Disclosure to nationals of other
// countries contrary to United States law is prohibited. It is the reader's
// responsibility to determine the applicable regulations and to comply with them.
//
// Disclaimer
//
// Synopsys, Inc., makes no warranty of any kind, express or implied, with regard
// to this material, including, but not limited to, the implied warranties of
// merchantability and fitness for a particular purpose.
//
// Synopsys, Inc., reserves the right to make changes without further notice to
// the products described herein. Synopsys, Inc. does not assume any liability
// arising out of the application or use of any product or circuit described
// herein. The Synopsys products described herein are not authorized for use as
// components in life-support devices.
//
// $Version 5.3.00
// $End_Version
// $Version 5.2.11
// 115 fm 03.20.96 Slave devsel responds after 6 cloks
// 221 fm 03.20.96 Rotating priority scheme
// 313 fm 03.20.96 setup timimg violation between pins par and clk
// 42767 fm 03.20.96 idsel-to-clk set-up time violations
// 43199 fm 03.20.96 valid combination of BE's ('F'x) flagged as invalid on io cycles
// 43258 fm 03.20.96 Target termination (RETRY) Rule 5 is violated
// 43264 fm 03.20.96 violation of Rule 6 not reported
// 42777 fm 02.28.96 Retrys on Dual Address Cycle Accesses lead to invalid error Msg.
// 43141 fm 02.11.96 Invalid warning : PCI ERROR 47, linear mode used for config cycles
// 42933 fm 02.11.96 Monitor reporting errors during reset
// 112 fm,tst 05.27.95 removed code for priority file
// $End_Version
//
//
`lmv_timescale
![[Up: pcimonitor fm]](v2html-up.gif)
module pcimonitor_fm
(clk,rstnn,ad,cxbenn,par,framenn,trdynn,irdynn,stopnn,devselnn,idsel,perrnn
,serrnn,reqnn,gntnn,locknn,par64,req64nn,ack64nn,sbonn,sdone,intann,intbnn
,intcnn,intdnn,disablemsg);
input clk;
input rstnn;
inout [63:0] ad;
reg ad_reg_63; assign ad[63] = ad_reg_63;
reg ad_reg_62; assign ad[62] = ad_reg_62;
reg ad_reg_61; assign ad[61] = ad_reg_61;
reg ad_reg_60; assign ad[60] = ad_reg_60;
reg ad_reg_59; assign ad[59] = ad_reg_59;
reg ad_reg_58; assign ad[58] = ad_reg_58;
reg ad_reg_57; assign ad[57] = ad_reg_57;
reg ad_reg_56; assign ad[56] = ad_reg_56;
reg ad_reg_55; assign ad[55] = ad_reg_55;
reg ad_reg_54; assign ad[54] = ad_reg_54;
reg ad_reg_53; assign ad[53] = ad_reg_53;
reg ad_reg_52; assign ad[52] = ad_reg_52;
reg ad_reg_51; assign ad[51] = ad_reg_51;
reg ad_reg_50; assign ad[50] = ad_reg_50;
reg ad_reg_49; assign ad[49] = ad_reg_49;
reg ad_reg_48; assign ad[48] = ad_reg_48;
reg ad_reg_47; assign ad[47] = ad_reg_47;
reg ad_reg_46; assign ad[46] = ad_reg_46;
reg ad_reg_45; assign ad[45] = ad_reg_45;
reg ad_reg_44; assign ad[44] = ad_reg_44;
reg ad_reg_43; assign ad[43] = ad_reg_43;
reg ad_reg_42; assign ad[42] = ad_reg_42;
reg ad_reg_41; assign ad[41] = ad_reg_41;
reg ad_reg_40; assign ad[40] = ad_reg_40;
reg ad_reg_39; assign ad[39] = ad_reg_39;
reg ad_reg_38; assign ad[38] = ad_reg_38;
reg ad_reg_37; assign ad[37] = ad_reg_37;
reg ad_reg_36; assign ad[36] = ad_reg_36;
reg ad_reg_35; assign ad[35] = ad_reg_35;
reg ad_reg_34; assign ad[34] = ad_reg_34;
reg ad_reg_33; assign ad[33] = ad_reg_33;
reg ad_reg_32; assign ad[32] = ad_reg_32;
reg ad_reg_31; assign ad[31] = ad_reg_31;
reg ad_reg_30; assign ad[30] = ad_reg_30;
reg ad_reg_29; assign ad[29] = ad_reg_29;
reg ad_reg_28; assign ad[28] = ad_reg_28;
reg ad_reg_27; assign ad[27] = ad_reg_27;
reg ad_reg_26; assign ad[26] = ad_reg_26;
reg ad_reg_25; assign ad[25] = ad_reg_25;
reg ad_reg_24; assign ad[24] = ad_reg_24;
reg ad_reg_23; assign ad[23] = ad_reg_23;
reg ad_reg_22; assign ad[22] = ad_reg_22;
reg ad_reg_21; assign ad[21] = ad_reg_21;
reg ad_reg_20; assign ad[20] = ad_reg_20;
reg ad_reg_19; assign ad[19] = ad_reg_19;
reg ad_reg_18; assign ad[18] = ad_reg_18;
reg ad_reg_17; assign ad[17] = ad_reg_17;
reg ad_reg_16; assign ad[16] = ad_reg_16;
reg ad_reg_15; assign ad[15] = ad_reg_15;
reg ad_reg_14; assign ad[14] = ad_reg_14;
reg ad_reg_13; assign ad[13] = ad_reg_13;
reg ad_reg_12; assign ad[12] = ad_reg_12;
reg ad_reg_11; assign ad[11] = ad_reg_11;
reg ad_reg_10; assign ad[10] = ad_reg_10;
reg ad_reg_9; assign ad[9] = ad_reg_9;
reg ad_reg_8; assign ad[8] = ad_reg_8;
reg ad_reg_7; assign ad[7] = ad_reg_7;
reg ad_reg_6; assign ad[6] = ad_reg_6;
reg ad_reg_5; assign ad[5] = ad_reg_5;
reg ad_reg_4; assign ad[4] = ad_reg_4;
reg ad_reg_3; assign ad[3] = ad_reg_3;
reg ad_reg_2; assign ad[2] = ad_reg_2;
reg ad_reg_1; assign ad[1] = ad_reg_1;
reg ad_reg_0; assign ad[0] = ad_reg_0;
inout [7:0] cxbenn;
reg cxbenn_reg_7; assign cxbenn[7] = cxbenn_reg_7;
reg cxbenn_reg_6; assign cxbenn[6] = cxbenn_reg_6;
reg cxbenn_reg_5; assign cxbenn[5] = cxbenn_reg_5;
reg cxbenn_reg_4; assign cxbenn[4] = cxbenn_reg_4;
reg cxbenn_reg_3; assign cxbenn[3] = cxbenn_reg_3;
reg cxbenn_reg_2; assign cxbenn[2] = cxbenn_reg_2;
reg cxbenn_reg_1; assign cxbenn[1] = cxbenn_reg_1;
reg cxbenn_reg_0; assign cxbenn[0] = cxbenn_reg_0;
inout par; reg par_reg; assign par = par_reg;
input framenn;
input trdynn;
input irdynn;
input stopnn;
input devselnn;
input [7:0] idsel;
input perrnn;
input serrnn;
input [7:0] reqnn;
inout [7:0] gntnn;
reg gntnn_reg_7; assign gntnn[7] = gntnn_reg_7;
reg gntnn_reg_6; assign gntnn[6] = gntnn_reg_6;
reg gntnn_reg_5; assign gntnn[5] = gntnn_reg_5;
reg gntnn_reg_4; assign gntnn[4] = gntnn_reg_4;
reg gntnn_reg_3; assign gntnn[3] = gntnn_reg_3;
reg gntnn_reg_2; assign gntnn[2] = gntnn_reg_2;
reg gntnn_reg_1; assign gntnn[1] = gntnn_reg_1;
reg gntnn_reg_0; assign gntnn[0] = gntnn_reg_0;
input locknn;
input par64;
input req64nn;
input ack64nn;
input sbonn;
input sdone;
input intann;
input intbnn;
input intcnn;
input intdnn;
input disablemsg;
parameter version = "pci33,pci33-10",
data_file = "pcimonitor_tst.lst",
arbitrate = `false,
priority = 0,
park_zero = `false,
trace_file = `true,
error_check = `true,
gen_global = `true,
gen_option = `lmv_maximum,
gen_time_check = `true,
gen_x_check = `true,
gen_annotated = `false,
gen_debug_level = 0,
gen_vlt = 5000,
gen_tmp = 300,
gen_DF = 100;
pcimonitor_timing timing(); // instantiation of timing package
pcimonitor_fm_input INP();
pcimonitor_fm_cntrl CNTRL();
pcimonitor_flags model_flags();
pcimonitor_times model_times();
reg init_finished; initial init_finished = `false;
reg timeout_flag;
// TIMING INITIALIZATION PROCESS
initial
begin : init_process
CNTRL.clk = `true;
CNTRL.ck_clk = `true;
CNTRL.rstnn = `true;
CNTRL.ck_rstnn = `true;
CNTRL.ad = `true;
CNTRL.ad_in = `true;
CNTRL.r_ad_clk = `true;
CNTRL.cxbenn = `true;
CNTRL.cxbenn_in = `true;
CNTRL.r_cxbenn_clk = `true;
CNTRL.par = `true;
CNTRL.par_in = `true;
CNTRL.r_par_clk = `true;
CNTRL.framenn = `true;
CNTRL.r_framenn_clk = `true;
CNTRL.trdynn = `true;
CNTRL.r_trdynn_clk = `true;
CNTRL.irdynn = `true;
CNTRL.r_irdynn_clk = `true;
CNTRL.stopnn = `true;
CNTRL.r_stopnn_clk = `true;
CNTRL.devselnn = `true;
CNTRL.r_devselnn_clk = `true;
CNTRL.idsel = `true;
CNTRL.r_idsel_clk = `true;
CNTRL.perrnn = `true;
CNTRL.r_perrnn_clk = `true;
CNTRL.serrnn = `true;
CNTRL.r_serrnn_clk = `true;
CNTRL.reqnn = `true;
CNTRL.r_reqnn_clk = `true;
CNTRL.gntnn = `true;
CNTRL.gntnn_in = `true;
CNTRL.r_gntnn_clk = `true;
CNTRL.locknn = `true;
CNTRL.r_locknn_clk = `true;
CNTRL.par64 = `true;
CNTRL.r_par64_clk = `true;
CNTRL.req64nn = `true;
CNTRL.r_req64nn_clk = `true;
CNTRL.ack64nn = `true;
CNTRL.r_ack64nn_clk = `true;
CNTRL.sbonn = `true;
CNTRL.r_sbonn_clk = `true;
CNTRL.sdone = `true;
CNTRL.r_sdone_clk = `true;
CNTRL.intann = `true;
CNTRL.r_intann_clk = `true;
CNTRL.intbnn = `true;
CNTRL.r_intbnn_clk = `true;
CNTRL.intcnn = `true;
CNTRL.r_intcnn_clk = `true;
CNTRL.intdnn = `true;
CNTRL.r_intdnn_clk = `true;
timeout_flag = `false;
if (gen_global === `true) begin
lmcver.get_flags(model_flags.option,model_flags.time_check,model_flags.x_check,
model_flags.annotated,model_flags.debug_level,
model_flags.vlt,model_flags.tmp,model_flags.DF);
end else begin
model_flags.option = gen_option;
model_flags.time_check = gen_time_check;
model_flags.x_check = gen_x_check;
model_flags.annotated = gen_annotated;
model_flags.vlt = gen_vlt;
model_flags.tmp = gen_tmp;
model_flags.DF = gen_DF;
end
model_flags.debug_level = gen_debug_level;
timing.get_timing(
model_times.tcy_min_clk,
model_times.tcy_max_clk,
model_times.tpwh_min_clk,
model_times.tpwh_max_clk,
model_times.tpwl_min_clk,
model_times.tpwl_max_clk,
model_times.twd_clk,
model_times.tcy_min_rstnn,
model_times.tcy_max_rstnn,
model_times.tpwh_min_rstnn,
model_times.tpwh_max_rstnn,
model_times.tpwl_min_rstnn,
model_times.tpwl_max_rstnn,
model_times.twd_rstnn,
model_times.trs_ad_clk,
model_times.trh_ad_clk,
model_times.twd_ad[63],
model_times.twd_ad[62],
model_times.twd_ad[61],
model_times.twd_ad[60],
model_times.twd_ad[59],
model_times.twd_ad[58],
model_times.twd_ad[57],
model_times.twd_ad[56],
model_times.twd_ad[55],
model_times.twd_ad[54],
model_times.twd_ad[53],
model_times.twd_ad[52],
model_times.twd_ad[51],
model_times.twd_ad[50],
model_times.twd_ad[49],
model_times.twd_ad[48],
model_times.twd_ad[47],
model_times.twd_ad[46],
model_times.twd_ad[45],
model_times.twd_ad[44],
model_times.twd_ad[43],
model_times.twd_ad[42],
model_times.twd_ad[41],
model_times.twd_ad[40],
model_times.twd_ad[39],
model_times.twd_ad[38],
model_times.twd_ad[37],
model_times.twd_ad[36],
model_times.twd_ad[35],
model_times.twd_ad[34],
model_times.twd_ad[33],
model_times.twd_ad[32],
model_times.twd_ad[31],
model_times.twd_ad[30],
model_times.twd_ad[29],
model_times.twd_ad[28],
model_times.twd_ad[27],
model_times.twd_ad[26],
model_times.twd_ad[25],
model_times.twd_ad[24],
model_times.twd_ad[23],
model_times.twd_ad[22],
model_times.twd_ad[21],
model_times.twd_ad[20],
model_times.twd_ad[19],
model_times.twd_ad[18],
model_times.twd_ad[17],
model_times.twd_ad[16],
model_times.twd_ad[15],
model_times.twd_ad[14],
model_times.twd_ad[13],
model_times.twd_ad[12],
model_times.twd_ad[11],
model_times.twd_ad[10],
model_times.twd_ad[9],
model_times.twd_ad[8],
model_times.twd_ad[7],
model_times.twd_ad[6],
model_times.twd_ad[5],
model_times.twd_ad[4],
model_times.twd_ad[3],
model_times.twd_ad[2],
model_times.twd_ad[1],
model_times.twd_ad[0],
model_times.tpr_clk_ad[31:0],
model_times.tpr_clk_ad[63:32],
model_times.tpr_clk_ad[95:64],
model_times.tpr_clk_ad[127:96],
model_times.tld_ad[63],
model_times.tld_ad[62],
model_times.tld_ad[61],
model_times.tld_ad[60],
model_times.tld_ad[59],
model_times.tld_ad[58],
model_times.tld_ad[57],
model_times.tld_ad[56],
model_times.tld_ad[55],
model_times.tld_ad[54],
model_times.tld_ad[53],
model_times.tld_ad[52],
model_times.tld_ad[51],
model_times.tld_ad[50],
model_times.tld_ad[49],
model_times.tld_ad[48],
model_times.tld_ad[47],
model_times.tld_ad[46],
model_times.tld_ad[45],
model_times.tld_ad[44],
model_times.tld_ad[43],
model_times.tld_ad[42],
model_times.tld_ad[41],
model_times.tld_ad[40],
model_times.tld_ad[39],
model_times.tld_ad[38],
model_times.tld_ad[37],
model_times.tld_ad[36],
model_times.tld_ad[35],
model_times.tld_ad[34],
model_times.tld_ad[33],
model_times.tld_ad[32],
model_times.tld_ad[31],
model_times.tld_ad[30],
model_times.tld_ad[29],
model_times.tld_ad[28],
model_times.tld_ad[27],
model_times.tld_ad[26],
model_times.tld_ad[25],
model_times.tld_ad[24],
model_times.tld_ad[23],
model_times.tld_ad[22],
model_times.tld_ad[21],
model_times.tld_ad[20],
model_times.tld_ad[19],
model_times.tld_ad[18],
model_times.tld_ad[17],
model_times.tld_ad[16],
model_times.tld_ad[15],
model_times.tld_ad[14],
model_times.tld_ad[13],
model_times.tld_ad[12],
model_times.tld_ad[11],
model_times.tld_ad[10],
model_times.tld_ad[9],
model_times.tld_ad[8],
model_times.tld_ad[7],
model_times.tld_ad[6],
model_times.tld_ad[5],
model_times.tld_ad[4],
model_times.tld_ad[3],
model_times.tld_ad[2],
model_times.tld_ad[1],
model_times.tld_ad[0],
model_times.trs_cxbenn_clk,
model_times.trh_cxbenn_clk,
model_times.twd_cxbenn[7],
model_times.twd_cxbenn[6],
model_times.twd_cxbenn[5],
model_times.twd_cxbenn[4],
model_times.twd_cxbenn[3],
model_times.twd_cxbenn[2],
model_times.twd_cxbenn[1],
model_times.twd_cxbenn[0],
model_times.tpr_clk_cxbenn[31:0],
model_times.tpr_clk_cxbenn[63:32],
model_times.tpr_clk_cxbenn[95:64],
model_times.tpr_clk_cxbenn[127:96],
model_times.tld_cxbenn[7],
model_times.tld_cxbenn[6],
model_times.tld_cxbenn[5],
model_times.tld_cxbenn[4],
model_times.tld_cxbenn[3],
model_times.tld_cxbenn[2],
model_times.tld_cxbenn[1],
model_times.tld_cxbenn[0],
model_times.trs_par_clk,
model_times.trh_par_clk,
model_times.twd_par,
model_times.tpr_clk_par[31:0],
model_times.tpr_clk_par[63:32],
model_times.tpr_clk_par[95:64],
model_times.tpr_clk_par[127:96],
model_times.tld_par,
model_times.trs_framenn_clk,
model_times.trh_framenn_clk,
model_times.twd_framenn,
model_times.trs_trdynn_clk,
model_times.trh_trdynn_clk,
model_times.twd_trdynn,
model_times.trs_irdynn_clk,
model_times.trh_irdynn_clk,
model_times.twd_irdynn,
model_times.trs_stopnn_clk,
model_times.trh_stopnn_clk,
model_times.twd_stopnn,
model_times.trs_devselnn_clk,
model_times.trh_devselnn_clk,
model_times.twd_devselnn,
model_times.trs_idsel_clk,
model_times.trh_idsel_clk,
model_times.twd_idsel[7],
model_times.twd_idsel[6],
model_times.twd_idsel[5],
model_times.twd_idsel[4],
model_times.twd_idsel[3],
model_times.twd_idsel[2],
model_times.twd_idsel[1],
model_times.twd_idsel[0],
model_times.trs_perrnn_clk,
model_times.trh_perrnn_clk,
model_times.twd_perrnn,
model_times.trs_serrnn_clk,
model_times.trh_serrnn_clk,
model_times.twd_serrnn,
model_times.trs_reqnn_clk,
model_times.trh_reqnn_clk,
model_times.twd_reqnn[7],
model_times.twd_reqnn[6],
model_times.twd_reqnn[5],
model_times.twd_reqnn[4],
model_times.twd_reqnn[3],
model_times.twd_reqnn[2],
model_times.twd_reqnn[1],
model_times.twd_reqnn[0],
model_times.trs_gntnn_clk,
model_times.trh_gntnn_clk,
model_times.twd_gntnn[7],
model_times.twd_gntnn[6],
model_times.twd_gntnn[5],
model_times.twd_gntnn[4],
model_times.twd_gntnn[3],
model_times.twd_gntnn[2],
model_times.twd_gntnn[1],
model_times.twd_gntnn[0],
model_times.tpr_clk_gntnn[31:0],
model_times.tpr_clk_gntnn[63:32],
model_times.tpr_clk_gntnn[95:64],
model_times.tpr_clk_gntnn[127:96],
model_times.tld_gntnn[7],
model_times.tld_gntnn[6],
model_times.tld_gntnn[5],
model_times.tld_gntnn[4],
model_times.tld_gntnn[3],
model_times.tld_gntnn[2],
model_times.tld_gntnn[1],
model_times.tld_gntnn[0],
model_times.trs_locknn_clk,
model_times.trh_locknn_clk,
model_times.twd_locknn,
model_times.trs_par64_clk,
model_times.trh_par64_clk,
model_times.twd_par64,
model_times.trs_req64nn_clk,
model_times.trh_req64nn_clk,
model_times.twd_req64nn,
model_times.trs_ack64nn_clk,
model_times.trh_ack64nn_clk,
model_times.twd_ack64nn,
model_times.trs_sbonn_clk,
model_times.trh_sbonn_clk,
model_times.twd_sbonn,
model_times.trs_sdone_clk,
model_times.trh_sdone_clk,
model_times.twd_sdone,
model_times.trs_intann_clk,
model_times.trh_intann_clk,
model_times.twd_intann,
model_times.trs_intbnn_clk,
model_times.trh_intbnn_clk,
model_times.twd_intbnn,
model_times.trs_intcnn_clk,
model_times.trh_intcnn_clk,
model_times.twd_intcnn,
model_times.trs_intdnn_clk,
model_times.trh_intdnn_clk,
model_times.twd_intdnn,
model_flags.option,
model_flags.annotated,
model_flags.vlt,
model_flags.tmp,
model_flags.DF,
version);
clk_check.last_rising = -50*`time_scale_multiplier;
clk_check.last_falling = -50*`time_scale_multiplier;
rstnn_check.last_rising = -50*`time_scale_multiplier;
rstnn_check.last_falling = -50*`time_scale_multiplier;
init_finished = `true;
end // init_process
// Performs all TIMING CHECKS and X-CHECKs for signal CLK
always begin : clk_check
reg wait_for_0;
integer last_rising, last_falling;
if (init_finished !== `true) begin
wait (init_finished === `true);
end
if (model_flags.time_check !== `true && model_flags.x_check !== `true) begin
// Kill process if NOT USED in simulation
wait(`false);
end else begin
@(INP.clk or CNTRL.clk);
wait_for_0 = `true;
wait_for_0 <= #(0) `false;
@(negedge wait_for_0);
INP.clk_last_event = $time - INP.clk_event_time;
INP.clk_last_event = $time - INP.clk_event_time;
INP.rstnn_last_event = $time - INP.rstnn_event_time;
INP.ad_last_event = $time - INP.ad_event_time;
INP.cxbenn_last_event = $time - INP.cxbenn_event_time;
INP.par_last_event = $time - INP.par_event_time;
INP.framenn_last_event = $time - INP.framenn_event_time;
INP.trdynn_last_event = $time - INP.trdynn_event_time;
INP.irdynn_last_event = $time - INP.irdynn_event_time;
INP.stopnn_last_event = $time - INP.stopnn_event_time;
INP.devselnn_last_event = $time - INP.devselnn_event_time;
INP.idsel_last_event = $time - INP.idsel_event_time;
INP.perrnn_last_event = $time - INP.perrnn_event_time;
INP.serrnn_last_event = $time - INP.serrnn_event_time;
INP.reqnn_last_event = $time - INP.reqnn_event_time;
INP.gntnn_last_event = $time - INP.gntnn_event_time;
INP.locknn_last_event = $time - INP.locknn_event_time;
INP.par64_last_event = $time - INP.par64_event_time;
INP.req64nn_last_event = $time - INP.req64nn_event_time;
INP.ack64nn_last_event = $time - INP.ack64nn_event_time;
INP.sbonn_last_event = $time - INP.sbonn_event_time;
INP.sdone_last_event = $time - INP.sdone_event_time;
INP.intann_last_event = $time - INP.intann_event_time;
INP.intbnn_last_event = $time - INP.intbnn_event_time;
INP.intcnn_last_event = $time - INP.intcnn_event_time;
INP.intdnn_last_event = $time - INP.intdnn_event_time;
if ($time > 1 && CNTRL.clk && INP.clk_last_event <= (2*`time_unit)) begin
if (model_flags.time_check) begin
if (INP.clk === 1'b1) begin
// Check cycle, pulse width low, and rising edge setup times
if (last_rising > 0 && $time - last_rising < model_times.tcy_min_clk && CNTRL.ck_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Cycle period is too short on pin clk\"");
end
if (last_rising > 0 && model_times.tcy_max_clk != 0 &&
$time - last_rising > model_times.tcy_max_clk && CNTRL.ck_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Cycle period is too long on pin clk\"");
end
if (last_falling > 0 && $time - last_falling < model_times.tpwl_min_clk && CNTRL.ck_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Pulse width low period is too short on pin clk\"");
end
if (last_falling > 0 && model_times.tpwl_max_clk != 0 &&
$time - last_falling > model_times.tpwl_max_clk && CNTRL.ck_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Pulse width low period is too long on pin clk\"");
end
last_rising = $time;
if ((INP.ad_last_event < model_times.trs_ad_clk) &&
CNTRL.ad_in && CNTRL.r_ad_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins ad and clk\"");
end
if ((INP.cxbenn_last_event < model_times.trs_cxbenn_clk) &&
CNTRL.cxbenn_in && CNTRL.r_cxbenn_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins cxbenn and clk\"");
end
if ((INP.par_last_event < model_times.trs_par_clk) &&
CNTRL.par_in && CNTRL.r_par_clk) begin
$display("WARNING at time %0t from %m",$time, ,CNTRL.r_par_clk);
$display(" \"Setup timing violation between pins par and clk\"");
end
if ((INP.framenn_last_event < model_times.trs_framenn_clk) &&
CNTRL.framenn && CNTRL.r_framenn_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins framenn and clk\"");
end
if ((INP.trdynn_last_event < model_times.trs_trdynn_clk) &&
CNTRL.trdynn && CNTRL.r_trdynn_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins trdynn and clk\"");
end
if ((INP.irdynn_last_event < model_times.trs_irdynn_clk) &&
CNTRL.irdynn && CNTRL.r_irdynn_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins irdynn and clk\"");
end
if ((INP.stopnn_last_event < model_times.trs_stopnn_clk) &&
CNTRL.stopnn && CNTRL.r_stopnn_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins stopnn and clk\"");
end
if ((INP.devselnn_last_event < model_times.trs_devselnn_clk) &&
CNTRL.devselnn && CNTRL.r_devselnn_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins devselnn and clk\"");
end
if ((INP.idsel_last_event < model_times.trs_idsel_clk) &&
CNTRL.idsel && CNTRL.r_idsel_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins idsel and clk\"");
end
if ((INP.perrnn_last_event < model_times.trs_perrnn_clk) &&
CNTRL.perrnn && CNTRL.r_perrnn_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins perrnn and clk\"");
end
if ((INP.serrnn_last_event < model_times.trs_serrnn_clk) &&
CNTRL.serrnn && CNTRL.r_serrnn_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins serrnn and clk\"");
end
if ((INP.reqnn_last_event < model_times.trs_reqnn_clk) &&
CNTRL.reqnn && CNTRL.r_reqnn_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins reqnn and clk\"");
end
if ((INP.gntnn_last_event < model_times.trs_gntnn_clk) &&
CNTRL.gntnn_in && CNTRL.r_gntnn_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins gntnn and clk\"");
end
if ((INP.locknn_last_event < model_times.trs_locknn_clk) &&
CNTRL.locknn && CNTRL.r_locknn_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins locknn and clk\"");
end
if ((INP.par64_last_event < model_times.trs_par64_clk) &&
CNTRL.par64 && CNTRL.r_par64_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins par64 and clk\"");
end
if ((INP.req64nn_last_event < model_times.trs_req64nn_clk) &&
CNTRL.req64nn && CNTRL.r_req64nn_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins req64nn and clk\"");
end
if ((INP.ack64nn_last_event < model_times.trs_ack64nn_clk) &&
CNTRL.ack64nn && CNTRL.r_ack64nn_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins ack64nn and clk\"");
end
if ((INP.sbonn_last_event < model_times.trs_sbonn_clk) &&
CNTRL.sbonn && CNTRL.r_sbonn_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins sbonn and clk\"");
end
if ((INP.sdone_last_event < model_times.trs_sdone_clk) &&
CNTRL.sdone && CNTRL.r_sdone_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins sdone and clk\"");
end
if ((INP.intann_last_event < model_times.trs_intann_clk) &&
CNTRL.intann && CNTRL.r_intann_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins intann and clk\"");
end
if ((INP.intbnn_last_event < model_times.trs_intbnn_clk) &&
CNTRL.intbnn && CNTRL.r_intbnn_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins intbnn and clk\"");
end
if ((INP.intcnn_last_event < model_times.trs_intcnn_clk) &&
CNTRL.intcnn && CNTRL.r_intcnn_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins intcnn and clk\"");
end
if ((INP.intdnn_last_event < model_times.trs_intdnn_clk) &&
CNTRL.intdnn && CNTRL.r_intdnn_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins intdnn and clk\"");
end
end else if (INP.clk === 1'b0) begin
// Check pulse width high, and falling edge setup times
if (last_rising > 0 && $time - last_rising < model_times.tpwh_min_clk && CNTRL.ck_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Pulse width high period is too short on pin clk\"");
end
if (last_rising > 0 && model_times.tpwh_max_clk != 0 &&
$time - last_rising > model_times.tpwh_max_clk && CNTRL.ck_clk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Pulse width high period is too long on pin clk\"");
end
last_falling = $time;
end
end
if (model_flags.x_check) begin
if (INP.clk === 1'bx) begin
// Check for UNKNOWN value on control/clock pin
$display("WARNING at time %0t from %m",$time);
$display(" \"Unknown value on pin clk will be ignored\"");
end
end
end else if ($time > 1 && INP.clk_event) begin
if (INP.clk === 1'b1) begin
last_rising = $time;
end else if (INP.clk === 1'b0) begin
last_falling = $time;
end
end
if ($time > 1 && model_flags.x_check) begin
if (clk === 1'b1) begin
if (par === 1'bx && CNTRL.par) begin
// $display("WARNING at time %0t from %m",$time);
// $display(" \"Unknown value on par input\"");
end
if (INP.par === 1'bz && CNTRL.par) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hi-Z value on par input\"");
end
if (framenn === 1'bx && CNTRL.framenn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Unknown value on framenn input\"");
end
if (INP.framenn === 1'bz && CNTRL.framenn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hi-Z value on framenn input\"");
end
if (trdynn === 1'bx && CNTRL.trdynn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Unknown value on trdynn input\"");
end
if (INP.trdynn === 1'bz && CNTRL.trdynn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hi-Z value on trdynn input\"");
end
if (irdynn === 1'bx && CNTRL.irdynn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Unknown value on irdynn input\"");
end
if (INP.irdynn === 1'bz && CNTRL.irdynn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hi-Z value on irdynn input\"");
end
if (stopnn === 1'bx && CNTRL.stopnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Unknown value on stopnn input\"");
end
if (INP.stopnn === 1'bz && CNTRL.stopnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hi-Z value on stopnn input\"");
end
if (devselnn === 1'bx && CNTRL.devselnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Unknown value on devselnn input\"");
end
if (INP.devselnn === 1'bz && CNTRL.devselnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hi-Z value on devselnn input\"");
end
if (perrnn === 1'bx && CNTRL.perrnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Unknown value on perrnn input\"");
end
if (INP.perrnn === 1'bz && CNTRL.perrnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hi-Z value on perrnn input\"");
end
if (serrnn === 1'bx && CNTRL.serrnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Unknown value on serrnn input\"");
end
if (INP.serrnn === 1'bz && CNTRL.serrnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hi-Z value on serrnn input\"");
end
if (locknn === 1'bx && CNTRL.locknn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Unknown value on locknn input\"");
end
if (INP.locknn === 1'bz && CNTRL.locknn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hi-Z value on locknn input\"");
end
if (par64 === 1'bx && CNTRL.par64) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Unknown value on par64 input\"");
end
if (INP.par64 === 1'bz && CNTRL.par64) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hi-Z value on par64 input\"");
end
if (req64nn === 1'bx && CNTRL.req64nn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Unknown value on req64nn input\"");
end
if (INP.req64nn === 1'bz && CNTRL.req64nn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hi-Z value on req64nn input\"");
end
if (ack64nn === 1'bx && CNTRL.ack64nn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Unknown value on ack64nn input\"");
end
if (INP.ack64nn === 1'bz && CNTRL.ack64nn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hi-Z value on ack64nn input\"");
end
if (sbonn === 1'bx && CNTRL.sbonn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Unknown value on sbonn input\"");
end
if (INP.sbonn === 1'bz && CNTRL.sbonn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hi-Z value on sbonn input\"");
end
if (sdone === 1'bx && CNTRL.sdone) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Unknown value on sdone input\"");
end
if (INP.sdone === 1'bz && CNTRL.sdone) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hi-Z value on sdone input\"");
end
if (intann === 1'bx && CNTRL.intann) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Unknown value on intann input\"");
end
if (INP.intann === 1'bz && CNTRL.intann) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hi-Z value on intann input\"");
end
if (intbnn === 1'bx && CNTRL.intbnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Unknown value on intbnn input\"");
end
if (INP.intbnn === 1'bz && CNTRL.intbnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hi-Z value on intbnn input\"");
end
if (intcnn === 1'bx && CNTRL.intcnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Unknown value on intcnn input\"");
end
if (INP.intcnn === 1'bz && CNTRL.intcnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hi-Z value on intcnn input\"");
end
if (intdnn === 1'bx && CNTRL.intdnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Unknown value on intdnn input\"");
end
if (INP.intdnn === 1'bz && CNTRL.intdnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hi-Z value on intdnn input\"");
end
begin: clk_reqnn_checkx
integer i;
for (i=0; i<=7; i=i+1) begin
if ((reqnn[i] === 1'bx || reqnn[i] === 1'bz) && CNTRL.reqnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Unknown value on reqnn inputs\"");
disable clk_reqnn_checkx;
end
end // loop
end // clk_reqnn_checkx
end
end
end
end // clk_check;
// Performs all TIMING CHECKS and X-CHECKs for signal RSTNN
always begin : rstnn_check
reg wait_for_0;
integer last_rising, last_falling;
if (init_finished !== `true) begin
wait (init_finished === `true);
end
if (model_flags.time_check !== `true && model_flags.x_check !== `true) begin
// Kill process if NOT USED in simulation
wait(`false);
end else begin
@(INP.rstnn or CNTRL.rstnn);
wait_for_0 = `true;
wait_for_0 <= #(0) `false;
@(negedge wait_for_0);
INP.rstnn_last_event = $time - INP.rstnn_event_time;
INP.clk_last_event = $time - INP.clk_event_time;
INP.rstnn_last_event = $time - INP.rstnn_event_time;
INP.ad_last_event = $time - INP.ad_event_time;
INP.cxbenn_last_event = $time - INP.cxbenn_event_time;
INP.par_last_event = $time - INP.par_event_time;
INP.framenn_last_event = $time - INP.framenn_event_time;
INP.trdynn_last_event = $time - INP.trdynn_event_time;
INP.irdynn_last_event = $time - INP.irdynn_event_time;
INP.stopnn_last_event = $time - INP.stopnn_event_time;
INP.devselnn_last_event = $time - INP.devselnn_event_time;
INP.idsel_last_event = $time - INP.idsel_event_time;
INP.perrnn_last_event = $time - INP.perrnn_event_time;
INP.serrnn_last_event = $time - INP.serrnn_event_time;
INP.reqnn_last_event = $time - INP.reqnn_event_time;
INP.gntnn_last_event = $time - INP.gntnn_event_time;
INP.locknn_last_event = $time - INP.locknn_event_time;
INP.par64_last_event = $time - INP.par64_event_time;
INP.req64nn_last_event = $time - INP.req64nn_event_time;
INP.ack64nn_last_event = $time - INP.ack64nn_event_time;
INP.sbonn_last_event = $time - INP.sbonn_event_time;
INP.sdone_last_event = $time - INP.sdone_event_time;
INP.intann_last_event = $time - INP.intann_event_time;
INP.intbnn_last_event = $time - INP.intbnn_event_time;
INP.intcnn_last_event = $time - INP.intcnn_event_time;
INP.intdnn_last_event = $time - INP.intdnn_event_time;
if ($time > 1 && CNTRL.rstnn && INP.rstnn_last_event <= (2*`time_unit)) begin
if (model_flags.time_check) begin
if (INP.rstnn === 1'b1) begin
// Check cycle, pulse width low, and rising edge setup times
if (last_rising > 0 && $time - last_rising < model_times.tcy_min_rstnn && CNTRL.ck_rstnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Cycle period is too short on pin rstnn\"");
end
if (last_rising > 0 && model_times.tcy_max_rstnn != 0 &&
$time - last_rising > model_times.tcy_max_rstnn && CNTRL.ck_rstnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Cycle period is too long on pin rstnn\"");
end
if (last_falling > 0 && $time - last_falling < model_times.tpwl_min_rstnn && CNTRL.ck_rstnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Pulse width low period is too short on pin rstnn\"");
end
if (last_falling > 0 && model_times.tpwl_max_rstnn != 0 &&
$time - last_falling > model_times.tpwl_max_rstnn && CNTRL.ck_rstnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Pulse width low period is too long on pin rstnn\"");
end
last_rising = $time;
end else if (INP.rstnn === 1'b0) begin
// Check pulse width high, and falling edge setup times
if (last_rising > 0 && $time - last_rising < model_times.tpwh_min_rstnn && CNTRL.ck_rstnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Pulse width high period is too short on pin rstnn\"");
end
if (last_rising > 0 && model_times.tpwh_max_rstnn != 0 &&
$time - last_rising > model_times.tpwh_max_rstnn && CNTRL.ck_rstnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Pulse width high period is too long on pin rstnn\"");
end
last_falling = $time;
| This page: |
Created: | Thu Aug 19 12:00:03 1999 |
| From: |
../../../sparc_v8/system/lmc/rtl/pcimonitor_fm.v
|