/******************************************************************************/ 
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/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
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/******************************************************************************/ 
/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)queue.v
***
***
****************************************************************************
****************************************************************************/
// @(#)queue.v	1.37 4/7/93
// queue.v
//----------------------------------------------------------------------------
/*
	Instruction queue
*/


// m4 doesn't work on the rest of this file with the usual quotes
// because these are used by verilog defines.
// change the quotes to very unlikely characters.
// also have to  .




module Mqueue (

//-------------------------------------------------------------------------o
//				PORTS

// OUTPUTS
	inst_for_int,
	inst_for_fpc,
	iexc_for_int,
	inst_for_br,
	nq1_entry_hi,
	iexc_for_br,
	niexc1_hi,
	fold_aa,
	alt_tag,
	nalttag_low,
	q3_iae, q3_ptc, q2_iae, q2_ptc, q1_iae, q1_ptc,

// INPUTS
	ic_ibus,
	last_gen,
	fpc,
	ic_mem_par,
	mm_fs_perr,
	mm_fs_lvl,
	mm_fs_iae,		// invalid addr error
	mm_fs_xerr,
	mm_fs_mmiss,
	mm_fs_sbe,		// sbus error
	mm_fs_sto,		// sbus timeout
	mm_fs_sptct,		// protection violation
	ic_sup_only,		// supervisor execute only

// CONTROL
	sel_shift1, sel_shift2, sel_shift3,
	sel_fold1, sel_fold2,
	sel_even1, sel_even2, sel_even3,
	sel_odd1, sel_odd2, sel_odd3,
	hold_q1, hold_q2, hold_q3, hold_q4,
	hold,
	fetch_alt,
	hold_alt,
	hld_dirreg, hld_dum_dpc,
	hld_backup, take_icdata,

// final mux control
	fetch_ic_even, fetch_ic_odd, fetch_TOQ,
	fetch_SIQ, ncant_unload, sel_old_aa, hld_dir2,

// MISC
	ss_clock, ss_scan_mode,
//	input_clock, input_clock_l,		6-5-96 
	Mqueue_scan_in, Mqueue_scan_out
);



output [31:0] inst_for_int;
output [31:0] inst_for_fpc;
output [10:0] iexc_for_int;
output [31:22] inst_for_br;
output [31:22] nq1_entry_hi;
output [10:2] iexc_for_br;
output [10:2] niexc1_hi;
output [31:2] fold_aa;
output [31:2] alt_tag;
output nalttag_low;
output q3_iae, q3_ptc, q2_iae, q2_ptc, q1_iae, q1_ptc;

input [63:0] ic_ibus;
input [31:2] last_gen;
input [31:2] fpc;
input [1:0] ic_mem_par;
input [1:0] mm_fs_perr;
input [1:0] mm_fs_lvl;
input mm_fs_iae;		// invalid addr error
input mm_fs_xerr;
input mm_fs_mmiss;
input mm_fs_sbe;		// sbus error
input mm_fs_sto;		// sbus timeout
input mm_fs_sptct;		// protection violation
input ic_sup_only;		// supervisor execute only

input sel_shift1, sel_shift2, sel_shift3;
input sel_fold1, sel_fold2;
input sel_even1, sel_even2, sel_even3;
input sel_odd1, sel_odd2, sel_odd3;
input hold_q1, hold_q2, hold_q3, hold_q4;
input hold;
input fetch_alt;
input hold_alt;
input hld_dirreg, hld_dum_dpc;
input hld_backup, take_icdata;

// final mux control
input fetch_ic_even, fetch_ic_odd, fetch_TOQ;
input fetch_SIQ, ncant_unload, sel_old_aa, hld_dir2;

input ss_clock, ss_scan_mode;
// input input_clock;		6-5-96 
// output input_clock_l;	6-5-96 
input Mqueue_scan_in;
output Mqueue_scan_out;

// forwarded declarations
	wire [31:0] inst_for_int;
	wire [10:0] iexc_for_int;

// this register goes in the STD cell slice

	wire cant_unload;
	Mflipflop_1 cant_unload_reg_1(cant_unload,ncant_unload,ss_clock,hold) ;

/*
        These mux selects are buffered with a special cell that
        turns the select off with ss_scan_mode.  some are turned
        on with ss_scan_mode - this stuff buffers the signal
        in the DP and guarantees that only 1 select is on at a
        time during scan (in conjunction with the control logic)
*/

	// for q3_mux, niexc3_mux, and q3_t_mux
	wire sel_even3_sm = sel_even3 | ss_scan_mode;
	wire sel_odd3_sm = sel_odd3 & ~ss_scan_mode;
	wire sel_shift3_sm = sel_shift3 & ~ss_scan_mode;

	// for q2_mux, niexc2_mux, and q2_t_mux
	wire sel_even2_sm = sel_even2 | ss_scan_mode;
	wire sel_odd2_sm = sel_odd2 & ~ss_scan_mode;
	wire sel_fold2_sm = sel_fold2 & ~ss_scan_mode;
	wire sel_shift2_sm = sel_shift2 & ~ss_scan_mode;

	// for q1_mux, niexc1_mux, and q1_t_mux
	wire sel_even1_sm = sel_even1 | ss_scan_mode;
	wire sel_odd1_sm = sel_odd1 & ~ss_scan_mode;
	wire sel_fold1_sm = sel_fold1 & ~ss_scan_mode;
	wire sel_shift1_sm = sel_shift1 & ~ss_scan_mode;

	// for last_i_mux and last_iexc_mux
	wire fetch_TOQ_sm = fetch_TOQ & ~ss_scan_mode;
	wire fetch_SIQ_sm = fetch_SIQ & ~ss_scan_mode;
	wire fetch_ic_even_sm = fetch_ic_even & ~ss_scan_mode;
	wire fetch_ic_odd_sm = fetch_ic_odd & ~ss_scan_mode;
	wire fetch_alt_sm = fetch_alt & ~ss_scan_mode;
	wire cant_unload_sm = cant_unload | ss_scan_mode;

	// these signals should go into the SPR slice for timing
	wire hold_q1_real = hold_q1 | hold;
	wire hold_q2_real = hold_q2 | hold;
	wire hold_q3_real = hold_q3 | hold;
	wire hold_q4_real = hold_q4 | hold;
	wire hld_dirreg_real = hld_dirreg | hold;
	wire hld_dir2_real = hld_dir2 | hold;
	wire hld_dum_dpc_real = hld_dum_dpc | hold;

	// put this MUX into the SPR slice for timing.  it is
	// only 2 bits.  ic_mm_perr[1:0] indicates that
	// the MEM or MMU found a parity error.  we select
	// MMU parity errors when mm_fs_xerr is on.  otherwise,
	// we look at MEM parity errors.
	wire  [1:0] ic_mm_perr;
    // Expanded macro begin.
    // cmux2(icmmperr_mux, 2, ic_mm_perr, ic_mem_par, mm_fs_perr, mm_fs_xerr)
    function [2:1] icmmperr_mux ;
        input [2:1] in0_fn ;
        input [2:1] in1_fn ;
        input select_fn ;
        reg [2:1] out_fn ;
        begin
            case (select_fn) /* synopsys parallel_case */
                1'b0: out_fn = in0_fn ;
                1'b1: out_fn = in1_fn ;
                default: out_fn = 65'hx;
            endcase
            icmmperr_mux = out_fn ;
        end
    endfunction
    assign ic_mm_perr = icmmperr_mux(ic_mem_par, mm_fs_perr, mm_fs_xerr) ;
    // Expanded macro end.


	// this hold term was gated in Mdecode, but to save a module
	// crossing, the gate was moved here
	wire hld_backup_real = hld_backup & hold;

	// this inverter is to buffer up the output of the PLL for
	// the clock controller.  it will go to Mpc where it will
	// get inverted again before it gets to the CC.
//	wire input_clock_l = ~input_clock;		 6-5-96 

/*
 * Build backup registers - select these during non I$ related
 * holds.
 */
	wire [63:32] ic_even_bu;
	
Mflipflop_32 ic_even_bu_reg_32(ic_even_bu,ic_ibus[63:32],ss_clock, 		hld_backup_real) ;

	wire [31:0] ic_odd_bu;
	Mflipflop_32 ic_odd_bu_reg_32(ic_odd_bu,ic_ibus[31:0],ss_clock,hld_backup_real) ;

	// these two signals belong on the SPR slice.  they
	// indicate a valid I$ parity error from memory.  it
	// is valid when the I$ is bypassing.

	wire [10:0] ic_iexc_f =
		{ic_mm_perr[1:0],	// parity error (even/odd)
		 mm_fs_xerr,		// xlation error
		 mm_fs_mmiss,		// mmu miss exc
		 mm_fs_iae,		// invalid addr error
		 mm_fs_sbe,		// sbus error
		 mm_fs_sto,		// sbus timeout
		 mm_fs_sptct,		// protection violation
		 ic_sup_only,		// supervisor execute only
		 mm_fs_lvl[1:0]		// PTE level
		};

	wire [10:0] ic_iexc_bu;
	Mflipflop_11 ic_iexc_bu_11(ic_iexc_bu,ic_iexc_f,ss_clock,hld_backup_real) ;

/*
 * use 2x1 mux to select correct source - either I$ or backup regs
 * in the event IU got data but couldn't stick in in queue or pipe.
 */
	wire [63:32] ic_even;
	wire [31:0] ic_odd;

    // Expanded macro begin.
    // cmux2(ic_even_mux, 32, ic_even, ic_even_bu, ic_ibus[63:32], take_icdata)
    function [32:1] ic_even_mux ;
        input [32:1] in0_fn ;
        input [32:1] in1_fn ;
        input select_fn ;
        reg [32:1] out_fn ;
        begin
            case (select_fn) /* synopsys parallel_case */
                1'b0: out_fn = in0_fn ;
                1'b1: out_fn = in1_fn ;
                default: out_fn = 65'hx;
            endcase
            ic_even_mux = out_fn ;
        end
    endfunction
    assign ic_even = ic_even_mux(ic_even_bu, ic_ibus[63:32], take_icdata) ;
    // Expanded macro end.

    // Expanded macro begin.
    // cmux2(ic_odd_mux, 32, ic_odd, ic_odd_bu, ic_ibus[31:0], take_icdata)
    function [32:1] ic_odd_mux ;
        input [32:1] in0_fn ;
        input [32:1] in1_fn ;
        input select_fn ;
        reg [32:1] out_fn ;
        begin
            case (select_fn) /* synopsys parallel_case */
                1'b0: out_fn = in0_fn ;
                1'b1: out_fn = in1_fn ;
                default: out_fn = 65'hx;
            endcase
            ic_odd_mux = out_fn ;
        end
    endfunction
    assign ic_odd = ic_odd_mux(ic_odd_bu, ic_ibus[31:0], take_icdata) ;
    // Expanded macro end.


	wire [10:0] iexc;
    // Expanded macro begin.
    // cmux2(iexc_even_mux, 11, iexc, ic_iexc_bu, ic_iexc_f, take_icdata)
    function [11:1] iexc_even_mux ;
        input [11:1] in0_fn ;
        input [11:1] in1_fn ;
        input select_fn ;
        reg [11:1] out_fn ;
        begin
            case (select_fn) /* synopsys parallel_case */
                1'b0: out_fn = in0_fn ;
                1'b1: out_fn = in1_fn ;
                default: out_fn = 65'hx;
            endcase
            iexc_even_mux = out_fn ;
        end
    endfunction
    assign iexc = iexc_even_mux(ic_iexc_bu, ic_iexc_f, take_icdata) ;
    // Expanded macro end.


/*
 * for even word, don't report odd word parity error, and for odd word
 * don't report even word parity error
 */

	wire [10:0] iexc_even =
		{iexc[10], 1'b0, iexc[8:0]};
	wire [10:0] iexc_odd =
		{1'b0, iexc[9], iexc[8:0]};

/*
 * get even/odd address
 */

//	REGWIRE [31:2] last_gen_bu;
//	REG(lgbu_reg,30,last_gen_bu,last_gen,ss_clock,hld_backup)
//
//	wire [31:2] even_adr;
//	CMUX2(even_adr_mux,30,even_adr,last_gen_bu,last_gen,take_icdata)

	wire [31:2] even_adr = last_gen;

	wire [31:2] odd_addr;
	Fincr_30 inc30_q(odd_addr, last_gen);
	/*
	assign odd_addr = last_gen + ({29'b0, 1'b1});
	*/
/*
 * 4 queue entries here with muxes - inst field, tag field
 */

// entry #4
	wire [31:0] q4_entry;
	Mflipflop_32 q4_reg_32(q4_entry,ic_odd[31:0],ss_clock,hold_q4_real) ;

	wire [10:0] iexc4;
	Mflipflop_11 iexc4_reg_11(iexc4,iexc_odd,ss_clock,hold_q4_real) ;

	wire [31:2] q4_tag;
	Mflipflop_30 q4_t_reg_30(q4_tag,odd_addr,ss_clock,hold_q4_real) ;

// entry #3
	wire [31:0] nq3_entry;
    // Expanded macro begin.
    // cmux3d(q3_mux, 32, nq3_entry,  		ic_even[63:32],  sel_even3_sm,  		ic_odd[31:0],  sel_odd3_sm,  		q4_entry,  sel_shift3_sm)
    function [32:1] q3_mux ;
        input [32:1] in0_fn ;
        input s0_fn ;
        input [32:1] in1_fn ;
        input s1_fn ;
        input [32:1] in2_fn ;
        input s2_fn ;
        reg [32:1] out_fn ;
        begin
            case ({ sel_shift3_sm,  sel_odd3_sm,  sel_even3_sm}) /* synopsys parallel_case */
                3'b001:         out_fn = in0_fn;
                3'b010: out_fn = in1_fn;
                3'b100:         out_fn = in2_fn;
                default:        out_fn = 65'hx;
            endcase
            q3_mux = out_fn ;
        end
    endfunction
    assign nq3_entry = q3_mux( 		ic_even[63:32],  sel_even3_sm,  		ic_odd[31:0],  sel_odd3_sm,  		q4_entry,  sel_shift3_sm) ;
    // synopsys translate_off
    always @ (posedge(~Mclocks.clock))
    #1 if (( sel_shift3_sm+ sel_odd3_sm+ sel_even3_sm !== 1) & `SS_SCOPE.input_reset_l &
    ~Mtask.trace.ppr & ~( sel_shift3_sm+ sel_odd3_sm^ sel_even3_sm===1'bx)) begin
    $display("### %m.q3_mux: CMUX3D select error!\n");
    $display(" sel_shift3_sm, sel_odd3_sm, sel_even3_sm=%0d%0d%0d\n",  sel_shift3_sm, sel_odd3_sm, sel_even3_sm);
    Mclocks.warning_count = Mclocks.warning_count + 1;
end
        // synopsys translate_on
        // Expanded macro end.

	wire [31:0] q3_entry;
	Mflipflop_32 q3_reg_32(q3_entry,nq3_entry,ss_clock,hold_q3_real) ;

	wire [10:0] niexc3;
    // Expanded macro begin.
    // cmux3d(niexc3_mux, 11, niexc3,  		iexc_even,  sel_even3_sm,  		iexc_odd,  sel_odd3_sm,  		iexc4,  sel_shift3_sm)
    function [11:1] niexc3_mux ;
        input [11:1] in0_fn ;
        input s0_fn ;
        input [11:1] in1_fn ;
        input s1_fn ;
        input [11:1] in2_fn ;
        input s2_fn ;
        reg [11:1] out_fn ;
        begin
            case ({ sel_shift3_sm,  sel_odd3_sm,  sel_even3_sm}) /* synopsys parallel_case */
                3'b001:         out_fn = in0_fn;
                3'b010: out_fn = in1_fn;
                3'b100:         out_fn = in2_fn;
                default:        out_fn = 65'hx;
            endcase
            niexc3_mux = out_fn ;
        end
    endfunction
    assign niexc3 = niexc3_mux( 		iexc_even,  sel_even3_sm,  		iexc_odd,  sel_odd3_sm,  		iexc4,  sel_shift3_sm) ;
    // synopsys translate_off
    always @ (posedge(~Mclocks.clock))
    #1 if (( sel_shift3_sm+ sel_odd3_sm+ sel_even3_sm !== 1) & `SS_SCOPE.input_reset_l &
    ~Mtask.trace.ppr & ~( sel_shift3_sm+ sel_odd3_sm^ sel_even3_sm===1'bx)) begin
    $display("### %m.niexc3_mux: CMUX3D select error!\n");
    $display(" sel_shift3_sm, sel_odd3_sm, sel_even3_sm=%0d%0d%0d\n",  sel_shift3_sm, sel_odd3_sm, sel_even3_sm);
    Mclocks.warning_count = Mclocks.warning_count + 1;
end
        // synopsys translate_on
        // Expanded macro end.

	wire [10:0] iexc3;
	Mflipflop_11 iexc3_reg_11(iexc3,niexc3,ss_clock,hold_q3_real) ;

	wire [31:2] nq3_tag;
    // Expanded macro begin.
    // cmux3d(q3_t_mux, 30, nq3_tag,  		even_adr,  sel_even3_sm,  		odd_addr,  sel_odd3_sm,  		q4_tag,  sel_shift3_sm)
    function [30:1] q3_t_mux ;
        input [30:1] in0_fn ;
        input s0_fn ;
        input [30:1] in1_fn ;
        input s1_fn ;
        input [30:1] in2_fn ;
        input s2_fn ;
        reg [30:1] out_fn ;
        begin
            case ({ sel_shift3_sm,  sel_odd3_sm,  sel_even3_sm}) /* synopsys parallel_case */
                3'b001:         out_fn = in0_fn;
                3'b010: out_fn = in1_fn;
                3'b100:         out_fn = in2_fn;
                default:        out_fn = 65'hx;
            endcase
            q3_t_mux = out_fn ;
        end
    endfunction
    assign nq3_tag = q3_t_mux( 		even_adr,  sel_even3_sm,  		odd_addr,  sel_odd3_sm,  		q4_tag,  sel_shift3_sm) ;
    // synopsys translate_off
    always @ (posedge(~Mclocks.clock))
    #1 if (( sel_shift3_sm+ sel_odd3_sm+ sel_even3_sm !== 1) & `SS_SCOPE.input_reset_l &
    ~Mtask.trace.ppr & ~( sel_shift3_sm+ sel_odd3_sm^ sel_even3_sm===1'bx)) begin
    $display("### %m.q3_t_mux: CMUX3D select error!\n");
    $display(" sel_shift3_sm, sel_odd3_sm, sel_even3_sm=%0d%0d%0d\n",  sel_shift3_sm, sel_odd3_sm, sel_even3_sm);
    Mclocks.warning_count = Mclocks.warning_count + 1;
end
        // synopsys translate_on
        // Expanded macro end.

	wire [31:2] q3_tag;
	Mflipflop_30 q3_t_reg_30(q3_tag,nq3_tag,ss_clock,hold_q3_real) ;

	wire q3_iae = iexc3[6];
	wire q3_ptc = iexc3[3];

// entry #2
	wire [31:0] nq2_entry;
    // Expanded macro begin.
    // cmux4d(q2_mux, 32, nq2_entry,  		ic_even[63:32],  sel_even2_sm,  		ic_odd[31:0],  sel_odd2_sm,  		q4_entry,  sel_fold2_sm,  		q3_entry,  sel_shift2_sm)
    function [32:1] q2_mux ;
        input [32:1] in0_fn ;
        input s0_fn ;
        input [32:1] in1_fn ;
        input s1_fn ;
        input [32:1] in2_fn ;
        input s2_fn ;
        input [32:1] in3_fn ;
        input s3_fn ;
        reg [32:1] out_fn ;
        begin
            case ({ sel_shift2_sm,  sel_fold2_sm,  sel_odd2_sm,  sel_even2_sm}) /* synopsys parallel_case */
                4'b0001:        out_fn = in0_fn;
                4'b0010: out_fn = in1_fn;
                4'b0100:        out_fn = in2_fn;
                4'b1000: out_fn = in3_fn;
                default: out_fn = 65'hx;
            endcase
            q2_mux = out_fn ;
        end
    endfunction
    assign nq2_entry = q2_mux( 		ic_even[63:32],  sel_even2_sm,  		ic_odd[31:0],  sel_odd2_sm,  		q4_entry,  sel_fold2_sm,  		q3_entry,  sel_shift2_sm) ;
    // synopsys translate_off
    always @ (posedge(~Mclocks.clock))
    #1 if (( sel_shift2_sm+ sel_fold2_sm+ sel_odd2_sm+ sel_even2_sm !== 1) & `SS_SCOPE.input_reset_l &
    ~Mtask.trace.ppr & ~( sel_shift2_sm+ sel_fold2_sm+ sel_odd2_sm^ sel_even2_sm===1'bx)) begin
    $display("### %m.q2_mux: CMUX4D select error!\n");
    $display(" sel_shift2_sm, sel_fold2_sm, sel_odd2_sm, sel_even2_sm=%0d%0d%0d%0d\n",  sel_shift2_sm, sel_fold2_sm, sel_odd2_sm, sel_even2_sm);
    Mclocks.warning_count = Mclocks.warning_count + 1;
end
 // synopsys translate_on
 // Expanded macro end.

	wire [31:0] q2_entry;
	Mflipflop_32 q2_reg_32(q2_entry,nq2_entry,ss_clock,hold_q2_real) ;

	wire [10:0] niexc2;
    // Expanded macro begin.
    // cmux4d(niexc2_mux, 11, niexc2,  		iexc_even,  sel_even2_sm,  		iexc_odd,  sel_odd2_sm,  		iexc4,  sel_fold2_sm,  		iexc3,  sel_shift2_sm)
    function [11:1] niexc2_mux ;
        input [11:1] in0_fn ;
        input s0_fn ;
        input [11:1] in1_fn ;
        input s1_fn ;
        input [11:1] in2_fn ;
        input s2_fn ;
        input [11:1] in3_fn ;
        input s3_fn ;
        reg [11:1] out_fn ;
        begin
            case ({ sel_shift2_sm,  sel_fold2_sm,  sel_odd2_sm,  sel_even2_sm}) /* synopsys parallel_case */
                4'b0001:        out_fn = in0_fn;
                4'b0010: out_fn = in1_fn;
                4'b0100:        out_fn = in2_fn;
                4'b1000: out_fn = in3_fn;
                default: out_fn = 65'hx;
            endcase
            niexc2_mux = out_fn ;
        end
    endfunction
    assign niexc2 = niexc2_mux( 		iexc_even,  sel_even2_sm,  		iexc_odd,  sel_odd2_sm,  		iexc4,  sel_fold2_sm,  		iexc3,  sel_shift2_sm) ;
    // synopsys translate_off
    always @ (posedge(~Mclocks.clock))
    #1 if (( sel_shift2_sm+ sel_fold2_sm+ sel_odd2_sm+ sel_even2_sm !== 1) & `SS_SCOPE.input_reset_l &
    ~Mtask.trace.ppr & ~( sel_shift2_sm+ sel_fold2_sm+ sel_odd2_sm^ sel_even2_sm===1'bx)) begin
    $display("### %m.niexc2_mux: CMUX4D select error!\n");
    $display(" sel_shift2_sm, sel_fold2_sm, sel_odd2_sm, sel_even2_sm=%0d%0d%0d%0d\n",  sel_shift2_sm, sel_fold2_sm, sel_odd2_sm, sel_even2_sm);
    Mclocks.warning_count = Mclocks.warning_count + 1;
end
 // synopsys translate_on
 // Expanded macro end.

	wire [10:0] iexc2;
	Mflipflop_11 iexc2_reg_11(iexc2,niexc2,ss_clock,hold_q2_real) ;

	wire [31:2] nq2_tag;
    // Expanded macro begin.
    // cmux4d(q2_t_mux, 30, nq2_tag,  		even_adr,  sel_even2_sm,  		odd_addr,  sel_odd2_sm,  		q4_tag,  sel_fold2_sm,  		q3_tag,  sel_shift2_sm)
    function [30:1] q2_t_mux ;
        input [30:1] in0_fn ;
        input s0_fn ;
        input [30:1] in1_fn ;
        input s1_fn ;
        input [30:1] in2_fn ;
        input s2_fn ;
        input [30:1] in3_fn ;
        input s3_fn ;
        reg [30:1] out_fn ;
        begin
            case ({ sel_shift2_sm,  sel_fold2_sm,  sel_odd2_sm,  sel_even2_sm}) /* synopsys parallel_case */
                4'b0001:        out_fn = in0_fn;
                4'b0010: out_fn = in1_fn;
                4'b0100:        out_fn = in2_fn;
                4'b1000: out_fn = in3_fn;
                default: out_fn = 65'hx;
            endcase
            q2_t_mux = out_fn ;
        end
    endfunction
    assign nq2_tag = q2_t_mux( 		even_adr,  sel_even2_sm,  		odd_addr,  sel_odd2_sm,  		q4_tag,  sel_fold2_sm,  		q3_tag,  sel_shift2_sm) ;
    // synopsys translate_off
    always @ (posedge(~Mclocks.clock))
    #1 if (( sel_shift2_sm+ sel_fold2_sm+ sel_odd2_sm+ sel_even2_sm !== 1) & `SS_SCOPE.input_reset_l &
    ~Mtask.trace.ppr & ~( sel_shift2_sm+ sel_fold2_sm+ sel_odd2_sm^ sel_even2_sm===1'bx)) begin
    $display("### %m.q2_t_mux: CMUX4D select error!\n");
    $display(" sel_shift2_sm, sel_fold2_sm, sel_odd2_sm, sel_even2_sm=%0d%0d%0d%0d\n",  sel_shift2_sm, sel_fold2_sm, sel_odd2_sm, sel_even2_sm);
    Mclocks.warning_count = Mclocks.warning_count + 1;
end
 // synopsys translate_on
 // Expanded macro end.

	wire [31:2] q2_tag;
	Mflipflop_30 q2_t_reg_30(q2_tag,nq2_tag,ss_clock,hold_q2_real) ;

	wire q2_iae = iexc2[6];
	wire q2_ptc = iexc2[3];

// entry #1
	wire [31:0] nq1_entry;
	wire [31:22] nq1_entry_hi = nq1_entry[31:22];
    // Expanded macro begin.
    // cmux4d(q1_mux, 32, nq1_entry,  		ic_even[63:32],  sel_even1_sm,  		ic_odd[31:0],  sel_odd1_sm,  		q3_entry,  sel_fold1_sm,  		q2_entry,  sel_shift1_sm)
    function [32:1] q1_mux ;
        input [32:1] in0_fn ;
        input s0_fn ;
        input [32:1] in1_fn ;
        input s1_fn ;
        input [32:1] in2_fn ;
        input s2_fn ;
        input [32:1] in3_fn ;
        input s3_fn ;
        reg [32:1] out_fn ;
        begin
            case ({ sel_shift1_sm,  sel_fold1_sm,  sel_odd1_sm,  sel_even1_sm}) /* synopsys parallel_case */
                4'b0001:        out_fn = in0_fn;
                4'b0010: out_fn = in1_fn;
                4'b0100:        out_fn = in2_fn;
                4'b1000: out_fn = in3_fn;
                default: out_fn = 65'hx;
            endcase
            q1_mux = out_fn ;
        end
    endfunction
    assign nq1_entry = q1_mux( 		ic_even[63:32],  sel_even1_sm,  		ic_odd[31:0],  sel_odd1_sm,  		q3_entry,  sel_fold1_sm,  		q2_entry,  sel_shift1_sm) ;
    // synopsys translate_off
    always @ (posedge(~Mclocks.clock))
    #1 if (( sel_shift1_sm+ sel_fold1_sm+ sel_odd1_sm+ sel_even1_sm !== 1) & `SS_SCOPE.input_reset_l &
    ~Mtask.trace.ppr & ~( sel_shift1_sm+ sel_fold1_sm+ sel_odd1_sm^ sel_even1_sm===1'bx)) begin
    $display("### %m.q1_mux: CMUX4D select error!\n");
    $display(" sel_shift1_sm, sel_fold1_sm, sel_odd1_sm, sel_even1_sm=%0d%0d%0d%0d\n",  sel_shift1_sm, sel_fold1_sm, sel_odd1_sm, sel_even1_sm);
    Mclocks.warning_count = Mclocks.warning_count + 1;
end
 // synopsys translate_on
 // Expanded macro end.

	wire [31:0] q1_entry;
	Mflipflop_32 q1_reg_32(q1_entry,nq1_entry,ss_clock,hold_q1_real) ;

	wire [10:0] niexc1;
	wire [10:2] niexc1_hi = niexc1[10:2];
    // Expanded macro begin.
    // cmux4d(niexc1_mux, 11, niexc1,  		iexc_even,  sel_even1_sm,  		iexc_odd,  sel_odd1_sm,  		iexc3,  sel_fold1_sm,  		iexc2,  sel_shift1_sm)
    function [11:1] niexc1_mux ;
        input [11:1] in0_fn ;
        input s0_fn ;
        input [11:1] in1_fn ;
        input s1_fn ;
        input [11:1] in2_fn ;
        input s2_fn ;
        input [11:1] in3_fn ;
        input s3_fn ;
        reg [11:1] out_fn ;
        begin
            case ({ sel_shift1_sm,  sel_fold1_sm,  sel_odd1_sm,  sel_even1_sm}) /* synopsys parallel_case */
                4'b0001:        out_fn = in0_fn;
                4'b0010: out_fn = in1_fn;
                4'b0100:        out_fn = in2_fn;
                4'b1000: out_fn = in3_fn;
                default: out_fn = 65'hx;
            endcase
            niexc1_mux = out_fn ;
        end
    endfunction
    assign niexc1 = niexc1_mux( 		iexc_even,  sel_even1_sm,  		iexc_odd,  sel_odd1_sm,  		iexc3,  sel_fold1_sm,  		iexc2,  sel_shift1_sm) ;
    // synopsys translate_off
    always @ (posedge(~Mclocks.clock))
    #1 if (( sel_shift1_sm+ sel_fold1_sm+ sel_odd1_sm+ sel_even1_sm !== 1) & `SS_SCOPE.input_reset_l &
    ~Mtask.trace.ppr & ~( sel_shift1_sm+ sel_fold1_sm+ sel_odd1_sm^ sel_even1_sm===1'bx)) begin
    $display("### %m.niexc1_mux: CMUX4D select error!\n");
    $display(" sel_shift1_sm, sel_fold1_sm, sel_odd1_sm, sel_even1_sm=%0d%0d%0d%0d\n",  sel_shift1_sm, sel_fold1_sm, sel_odd1_sm, sel_even1_sm);
    Mclocks.warning_count = Mclocks.warning_count + 1;
end
 // synopsys translate_on
 // Expanded macro end.

	wire [10:0] iexc1;
	Mflipflop_11 iexc1_reg_11(iexc1,niexc1,ss_clock,hold_q1_real) ;

	wire [31:2] nq1_tag;
    // Expanded macro begin.
    // cmux4d(q1_t_mux, 30, nq1_tag,  		even_adr,  sel_even1_sm,  		odd_addr,  sel_odd1_sm,  		q3_tag,  sel_fold1_sm,  		q2_tag,  sel_shift1_sm)
    function [30:1] q1_t_mux ;
        input [30:1] in0_fn ;
        input s0_fn ;
        input [30:1] in1_fn ;
        input s1_fn ;
        input [30:1] in2_fn ;
        input s2_fn ;
        input [30:1] in3_fn ;
        input s3_fn ;
        reg [30:1] out_fn ;
        begin
            case ({ sel_shift1_sm,  sel_fold1_sm,  sel_odd1_sm,  sel_even1_sm}) /* synopsys parallel_case */
                4'b0001:        out_fn = in0_fn;
                4'b0010: out_fn = in1_fn;
                4'b0100:        out_fn = in2_fn;
                4'b1000: out_fn = in3_fn;
                default: out_fn = 65'hx;
            endcase
            q1_t_mux = out_fn ;
        end
    endfunction
    assign nq1_tag = q1_t_mux( 		even_adr,  sel_even1_sm,  		odd_addr,  sel_odd1_sm,  		q3_tag,  sel_fold1_sm,  		q2_tag,  sel_shift1_sm) ;
    // synopsys translate_off
    always @ (posedge(~Mclocks.clock))
    #1 if (( sel_shift1_sm+ sel_fold1_sm+ sel_odd1_sm+ sel_even1_sm !== 1) & `SS_SCOPE.input_reset_l &
    ~Mtask.trace.ppr & ~( sel_shift1_sm+ sel_fold1_sm+ sel_odd1_sm^ sel_even1_sm===1'bx)) begin
    $display("### %m.q1_t_mux: CMUX4D select error!\n");
    $display(" sel_shift1_sm, sel_fold1_sm, sel_odd1_sm, sel_even1_sm=%0d%0d%0d%0d\n",  sel_shift1_sm, sel_fold1_sm, sel_odd1_sm, sel_even1_sm);
    Mclocks.warning_count = Mclocks.warning_count + 1;
end
 // synopsys translate_on
 // Expanded macro end.

	wire [31:2] q1_tag;
	Mflipflop_30 q1_t_reg_30(q1_tag,nq1_tag,ss_clock,hold_q1_real) ;

	wire q1_iae = iexc1[6];
	wire q1_ptc = iexc1[3];

/*
 * Address adder and muxes
 */
	wire [31:0] dummy_dir;
	Mflipflop_32 dummy_dir_reg_32(dummy_dir,inst_for_int,ss_clock,hld_dirreg_real) ;

	wire [31:2] dummy_dpc;
	Mflipflop_30 dummy_dpc_reg_30(dummy_dpc,fpc,ss_clock,hld_dum_dpc_real) ;

	wire dumdir_call = dummy_dir[31:30] == 2'b01;
	wire dumdir_brfbr =
		  dummy_dir[31:30] == 2'b00 & (
			  dummy_dir[24:22] == 3'b010	// BICC
			| dummy_dir[24:22] == 3'b110	// BFCC
			);

	wire [29:22] br_offset = {8{dummy_dir[21]}};
	wire [29:22] dir_high;
    // Expanded macro begin.
    // cmux2(dir_high_mux, 8, dir_high, br_offset, dummy_dir[29:22], dumdir_call)
    function [8:1] dir_high_mux ;
        input [8:1] in0_fn ;
        input [8:1] in1_fn ;
        input select_fn ;
        reg [8:1] out_fn ;
        begin
            case (select_fn) /* synopsys parallel_case */
                1'b0: out_fn = in0_fn ;
                1'b1: out_fn = in1_fn ;
                default: out_fn = 65'hx;
            endcase
            dir_high_mux = out_fn ;
        end
    endfunction
    assign dir_high = dir_high_mux(br_offset, dummy_dir[29:22], dumdir_call) ;
    // Expanded macro end.


	wire [31:2] dir_offset = {dir_high,dummy_dir[21:0]};

	wire [31:2] toq_offset = {{8{q1_entry[21]}},q1_entry[21:0]};

	wire sel_dirside = dumdir_call | dumdir_brfbr;
	wire [31:2] pc_offset;
    // Expanded macro begin.
    // cmux2(pc_offset_mux, 30, pc_offset, toq_offset, dir_offset, sel_dirside)
    function [30:1] pc_offset_mux ;
        input [30:1] in0_fn ;
        input [30:1] in1_fn ;
        input select_fn ;
        reg [30:1] out_fn ;
        begin
            case (select_fn) /* synopsys parallel_case */
                1'b0: out_fn = in0_fn ;
                1'b1: out_fn = in1_fn ;
                default: out_fn = 65'hx;
            endcase
            pc_offset_mux = out_fn ;
        end
    endfunction
    assign pc_offset = pc_offset_mux(toq_offset, dir_offset, sel_dirside) ;
    // Expanded macro end.


	wire [31:2] base_pc;
    // Expanded macro begin.
    // cmux2(base_pc_mux, 30, base_pc, q1_tag, dummy_dpc, sel_dirside)
    function [30:1] base_pc_mux ;
        input [30:1] in0_fn ;
        input [30:1] in1_fn ;
        input select_fn ;
        reg [30:1] out_fn ;
        begin
            case (select_fn) /* synopsys parallel_case */
                1'b0: out_fn = in0_fn ;
                1'b1: out_fn = in1_fn ;
                default: out_fn = 65'hx;
            endcase
            base_pc_mux = out_fn ;
        end
    endfunction
    assign base_pc = base_pc_mux(q1_tag, dummy_dpc, sel_dirside) ;
    // Expanded macro end.


	/*
	wire [31:2] fold_aa_adder = base_pc + pc_offset;
	*/

	wire [31:2] fold_aa_adder;
	adder30 adder30(
		.sum	(fold_aa_adder),
		.ain	(base_pc),
		.bin	(pc_offset));

	wire [31:2] p_fold_aa;
	wire [31:2] fold_aa;
	Mflipflop_30 p_fold_aa_reg_30(p_fold_aa,fold_aa,ss_clock,hld_dir2_real) ;

    // Expanded macro begin.
    // cmux2(fold_aa_mux, 30, fold_aa, fold_aa_adder, p_fold_aa, sel_old_aa)
    function [30:1] fold_aa_mux ;
        input [30:1] in0_fn ;
        input [30:1] in1_fn ;
        input select_fn ;
        reg [30:1] out_fn ;
        begin
            case (select_fn) /* synopsys parallel_case */
                1'b0: out_fn = in0_fn ;
                1'b1: out_fn = in1_fn ;
                default: out_fn = 65'hx;
            endcase
            fold_aa_mux = out_fn ;
        end
    endfunction
    assign fold_aa = fold_aa_mux(fold_aa_adder, p_fold_aa, sel_old_aa) ;
    // Expanded macro end.



/*
 * alternate buffer for unpredicted path
 */

// alt entry - inst field, tag field
	wire [31:0] alt_entry;
	Mflipflop_32 alt_reg_32(alt_entry,q1_entry,ss_clock,hold_alt) ;

	wire [10:0] alt_iexc;
	Mflipflop_11 alt_iexc_reg_11(alt_iexc,iexc1,ss_clock,hold_alt) ;

	wire [31:2] alt_tag;
	Mflipflop_30 alt_t_reg_30(alt_tag,q1_tag,ss_clock,hold_alt) ;

	wire nalttag_low = q1_tag[2];

/*
 * instruction reg in case DIR missed it
 */

	wire [31:0] backup_dir;
	Mflipflop_32 backup_dir_reg_32(backup_dir,inst_for_int,ss_clock,hld_dir2_real) ;

	wire [10:0] backup_iexc;
	Mflipflop_11 backup_iexc_reg_11(backup_iexc,iexc_for_int,ss_clock, 		hld_dir2_real) ;

//	REGWIRE [31:22] backup_bdir;
//	REG(backup_bdir_reg,10,backup_bdir, //		inst_for_br[31:22],ss_clock,hld_dir2)

//	REGWIRE [10:2] backup_biexc;
//	REG(backup_biexc_reg,9,backup_biexc,iexc_for_br[10:2], //		ss_clock,hld_dir2_real)

/*
 * final muxing - final inst selection
 */

    // Expanded macro begin.
    // cmux6d(last_i_mux, 32, inst_for_int,  		q1_entry,  fetch_TOQ_sm,  		q2_entry,  fetch_SIQ_sm,  		ic_even[63:32],  fetch_ic_even_sm,  		ic_odd[31:0],  fetch_ic_odd_sm,  		alt_entry,  fetch_alt_sm, 			backup_dir,  cant_unload_sm)
    function [32:1] last_i_mux ;
        input [32:1] in0_fn ;
        input s0_fn ;
        input [32:1] in1_fn ;
        input s1_fn ;
        input [32:1] in2_fn ;
        input s2_fn ;
        input [32:1] in3_fn ;
        input s3_fn ;
        input [32:1] in4_fn ;
        input s4_fn ;
        input [32:1] in5_fn ;
        input s5_fn ;
        reg [32:1] out_fn ;
        begin
            case ({ cant_unload_sm,  fetch_alt_sm,  fetch_ic_odd_sm,  fetch_ic_even_sm,  fetch_SIQ_sm,  fetch_TOQ_sm}) /* synopsys parallel_case */
                6'b000001:      out_fn = in0_fn ;
                6'b000010: out_fn = in1_fn ;
                6'b000100:      out_fn = in2_fn ;
                6'b001000: out_fn = in3_fn ;
                6'b010000:      out_fn = in4_fn ;
                6'b100000: out_fn = in5_fn ;
                default: out_fn = 65'hx;
            endcase
            last_i_mux = out_fn ;
        end
    endfunction
    assign inst_for_int = last_i_mux( 		q1_entry,  fetch_TOQ_sm,  		q2_entry,  fetch_SIQ_sm,  		ic_even[63:32],  fetch_ic_even_sm,  		ic_odd[31:0],
    fetch_ic_odd_sm,  		alt_entry,  fetch_alt_sm, 			backup_dir,  cant_unload_sm) ;
    // synopsys translate_off
    always @ (posedge(~Mclocks.clock))
    #1 if (( cant_unload_sm+ fetch_alt_sm+ fetch_ic_odd_sm+ fetch_ic_even_sm+ fetch_SIQ_sm+ fetch_TOQ_sm !== 1) & `SS_SCOPE.input_reset_l &
    ~Mtask.trace.ppr & ~( cant_unload_sm+ fetch_alt_sm+ fetch_ic_odd_sm+ fetch_ic_even_sm+ fetch_SIQ_sm^ fetch_TOQ_sm===1'bx)) begin
    $display("### %m.last_i_mux: CMUX6D select error!\n");
    $display(" cant_unload_sm, fetch_alt_sm, fetch_ic_odd_sm, fetch_ic_even_sm, fetch_SIQ_sm, fetch_TOQ_sm=%0d%0d%0d%0d%0d%0d\n",  cant_unload_sm, fetch_alt_sm, fetch_ic_odd_sm, fetch_ic_even_sm, fetch_SIQ_sm, fetch_TOQ_sm);
    Mclocks.warning_count = Mclocks.warning_count + 1;
end
 // synopsys translate_on
 // Expanded macro end.


	wire [31:0] inst_for_fpc = inst_for_int;

    // Expanded macro begin.
    // cmux6d(last_iexc_mux, 11, iexc_for_int,  		iexc1,  fetch_TOQ_sm,  		iexc2,  fetch_SIQ_sm,  		iexc_even,  fetch_ic_even_sm,  		iexc_odd,  fetch_ic_odd_sm,  		alt_iexc,  fetch_alt_sm, 			backup_iexc,  cant_unload_sm)
    function [11:1] last_iexc_mux ;
        input [11:1] in0_fn ;
        input s0_fn ;
        input [11:1] in1_fn ;
        input s1_fn ;
        input [11:1] in2_fn ;
        input s2_fn ;
        input [11:1] in3_fn ;
        input s3_fn ;
        input [11:1] in4_fn ;
        input s4_fn ;
        input [11:1] in5_fn ;
        input s5_fn ;
        reg [11:1] out_fn ;
        begin
            case ({ cant_unload_sm,  fetch_alt_sm,  fetch_ic_odd_sm,  fetch_ic_even_sm,  fetch_SIQ_sm,  fetch_TOQ_sm}) /* synopsys parallel_case */
                6'b000001:      out_fn = in0_fn ;
                6'b000010: out_fn = in1_fn ;
                6'b000100:      out_fn = in2_fn ;
                6'b001000: out_fn = in3_fn ;
                6'b010000:      out_fn = in4_fn ;
                6'b100000: out_fn = in5_fn ;
                default: out_fn = 65'hx;
            endcase
            last_iexc_mux = out_fn ;
        end
    endfunction
    assign iexc_for_int = last_iexc_mux( 		iexc1,  fetch_TOQ_sm,  		iexc2,  fetch_SIQ_sm,  		iexc_even,  fetch_ic_even_sm,  		iexc_odd,
    fetch_ic_odd_sm,  		alt_iexc,  fetch_alt_sm, 			backup_iexc,  cant_unload_sm) ;
    // synopsys translate_off
    always @ (posedge(~Mclocks.clock))
    #1 if (( cant_unload_sm+ fetch_alt_sm+ fetch_ic_odd_sm+ fetch_ic_even_sm+ fetch_SIQ_sm+ fetch_TOQ_sm !== 1) & `SS_SCOPE.input_reset_l &
    ~Mtask.trace.ppr & ~( cant_unload_sm+ fetch_alt_sm+ fetch_ic_odd_sm+ fetch_ic_even_sm+ fetch_SIQ_sm^ fetch_TOQ_sm===1'bx)) begin
    $display("### %m.last_iexc_mux: CMUX6D select error!\n");
    $display(" cant_unload_sm, fetch_alt_sm, fetch_ic_odd_sm, fetch_ic_even_sm, fetch_SIQ_sm, fetch_TOQ_sm=%0d%0d%0d%0d%0d%0d\n",  cant_unload_sm, fetch_alt_sm, fetch_ic_odd_sm, fetch_ic_even_sm, fetch_SIQ_sm, fetch_TOQ_sm);
    Mclocks.warning_count = Mclocks.warning_count + 1;
end
 // synopsys translate_on
 // Expanded macro end.


	// only need bicc and cond and annul
	wire [31:22] inst_for_br = q1_entry[31:22];

//	CMUX2(inst_br_mux,10,inst_for_br, //		q1_entry[31:22],backup_bdir,cant_unload)

	// don't need pte level
	wire [10:2] iexc_for_br = iexc1[10:2];

//	wire [10:2] iexc_for_br;
//	CMUX2(iexc_for_br,9,iexc_for_br,iexc1[10:2],backup_biexc,cant_unload)


endmodule