/******************************************************************************/ 
/*                                                                            */ 
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
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/******************************************************************************/ 
/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)iu.v
***
***
****************************************************************************
****************************************************************************/
// @(#)iu.v	1.137 8/7/93


/*******************************************************************************

	The following module is simply a frame around the IU module
	described above. It instantiates Miuchip.

	It's purpose is to allow the inclusion of de-bugging and "trick"
	logic that affects the pins of the IU at the simulation model level
	so that a netlist-driven top level simulation can still have
	this stuff in it.

*******************************************************************************/



module Miu(
	little_endian, // added May 29, 96
	sel_last_gen, sel_recirc,
	select_IU_DOUT, select_FP_DOUT, sel_ldstb_1, src3,
	ld_iu,
	iu_dva_e, iu_dva_e_dc,
	ic_ibus,
	iu_iva_g, icache_adr, icache_tag_in,
	iu_iflush_e, force_dva,
	it_hit_f, enbl_itag_match_f, iwait_f,
	imiss_in_progress, start_itag_inv, ic_force_ifill_g, mm_istat_avail,
	i_dva_req,
	i_nfillp,
	byte_mark0_e, byte_mark1_e, byte_mark2_e, byte_mark3_e,
	FHOLD,
	dc_shold,
	dt_hit_w, enbl_dtag_match_w, dwait_w, dwait_w_for_flush,
	iu_asi_e,
	ld_op_e, ld_op_e_mmu, ld_op_d, sgnd_ld_e,
	st_op_e, st_op_e_mmu, st_op_d,
	fpu_mem_e, size_e,
	ic_idle, mm_icache_enbl,
	mm_dacc_exc_w,
	mm_dacc_err_w,
	mm_dacc_mmu_miss_w, mm_dacc_wp_w, iu_mm_iacc_wp_exc_d,
	ic_mem_par, mm_fs_perr,
	mm_fs_lvl, mm_fs_iae, mm_fs_xerr, mm_fs_mmiss,
	mm_fs_sbe, mm_fs_sto, mm_fs_sptct,
	enbl_br_fold,
	ic_sup_only,
	iu_sfs_sup,
	iu_sfs_perr, iu_sfs_xerr, iu_sfs_mmiss,
	iu_sfs_iae, iu_sfs_sbe, iu_sfs_sto,
	iu_sfs_prtct, iu_sfs_priv, iu_sfs_lvl,
	ss_reset,
	FEXC,
	pfcc, pfccv,
	IRL,
	error_mode,
	ss_clock,
	ss_scan_mode,
	valid_decode, fold_annul,
	pipe_hold4fpc,
	pipe_hold4fprf,
	pipe_hold4mmu_cntl,
	pipe_hold4mmu_dp,
	pipe_hold4dc, pipe_hold4dc_l, fast_hld_terms,
	pipe_hold4ic,
	ihold_d1, dhold_d1, did_fetch,
	TRAP,
	iu_epc, inst_for_fpc,
	IU_in_trap, IU_in_trap4fpu, IU_in_trap4dc,
	FXACK,
	enbl_fetch,
	hld_dirreg,
	iu_event, iu_sup_mode,
//	input_clock, input_clock_buf,
	Miu_scan_in,
	Miu_scan_out
	);

output little_endian; // added May 29, 96 
output sel_last_gen ;
output sel_recirc ;
//output [63:0] iu_dout;		// data output bus
output select_IU_DOUT;
output select_FP_DOUT;
output sel_ldstb_1;
output [31:0] src3;

input [31:0] ld_iu;	// low word of data bus
output [31:0] iu_dva_e;	// D cache address
output [31:0] iu_dva_e_dc;
input [63:0] ic_ibus;	// data from I cache
output [31:2] iu_iva_g;	// I cache address
output [13:3] icache_adr;
output [31:14] icache_tag_in;

output iu_iflush_e;		// IFLUSH in E
output force_dva;

input it_hit_f;
input enbl_itag_match_f;
input iwait_f;

input imiss_in_progress;
input start_itag_inv;
input ic_force_ifill_g;
input mm_istat_avail;
input i_dva_req;
input [4:3] i_nfillp;

//output [0:3] iu_byte_marks_e;	// which bytes to write
output byte_mark0_e;
output byte_mark1_e;
output byte_mark2_e;
output byte_mark3_e;

input FHOLD;			// FPU Hold input

input dc_shold;			// generic hold from d cache

input dt_hit_w;
input enbl_dtag_match_w;
input dwait_w;
input dwait_w_for_flush;

// signals for MMU
output [5:0] iu_asi_e;		// ASI for inst in E

output ld_op_e;
output ld_op_e_mmu;
output ld_op_d;
output sgnd_ld_e;
output st_op_e;
output st_op_e_mmu;
output st_op_d;
output fpu_mem_e;
output [1:0] size_e;

input ic_idle;
input mm_icache_enbl;

input mm_dacc_exc_w;		// data acc exception
input mm_dacc_err_w;		// data acc error

input mm_dacc_mmu_miss_w;
input mm_dacc_wp_w;

output iu_mm_iacc_wp_exc_d;

input [1:0] ic_mem_par;
input [1:0] mm_fs_perr;
input [1:0] mm_fs_lvl;
input mm_fs_iae;
input mm_fs_xerr;
input mm_fs_mmiss;
input mm_fs_sbe;
input mm_fs_sto;
input mm_fs_sptct;
input enbl_br_fold;
input ic_sup_only;

output iu_sfs_sup;
output [1:0] iu_sfs_perr;
output iu_sfs_xerr;
output iu_sfs_mmiss;
output iu_sfs_iae;
output iu_sfs_sbe;
output iu_sfs_sto;
output iu_sfs_prtct;
output iu_sfs_priv;
output [1:0] iu_sfs_lvl;

input ss_reset;			// reset

input FEXC;			// FPU Exception

input [1:0] pfcc;		// FPU cc's
input pfccv;			// FPU cc's Valid

input [3:0] IRL;		// Interrupt Request Level

output error_mode;		// Error State

// input [5:0] ss_clock_iu;			// system clock input
input ss_clock;			// system clock input    6-5-96 

input ss_scan_mode;			// iu scan mode (was SCANMODE)

output valid_decode;	// special form for FPU
output fold_annul;

//output iu_pipe_hold;		// tell things outside of IU
output [2:0] pipe_hold4fpc;
output pipe_hold4fprf;
output pipe_hold4mmu_cntl;
output pipe_hold4mmu_dp;
output pipe_hold4dc;
output [1:0] pipe_hold4dc_l;
output fast_hld_terms;
output pipe_hold4ic;

output ihold_d1;		// for MMU performance counters
output dhold_d1;
output did_fetch;

output TRAP;			// TRAP detected

output [31:2] iu_epc;		// decode PC
output [31:0] inst_for_fpc;	// inst for FPU
//input [63:0] fp_dout;
output IU_in_trap;		// Tell CC that IU is trapping
output IU_in_trap4fpu;		// tell FP
output IU_in_trap4dc;		// tell DC

output FXACK;			// ack FP exceptions for FPU
output enbl_fetch;
output hld_dirreg;
output iu_event;		// special event opcode detected
output iu_sup_mode;		// perf counter in MMU

// input input_clock;		// buffer PLL output for CC
// output input_clock_buf;

input Miu_scan_in;
output Miu_scan_out;

    // IU OUTPUTS

	wire FHOLD_SWAP = FHOLD;
	wire FEXC_SWAP = FEXC;
	wire FCCV_SWAP = pfccv;



	wire [3:0] IU_IRL = IRL;

	/*
	The following stuff implements a mode in which all normal ASI
	accesses are forced to be at addresses in the first 128K.

	This mode is not supported for gate level IU simulations
	because the output enable for AH is not readily available.
	*/

// synopsys translate_off


// Eagle: July 11, 1996.
// These were switched out for gatesim.  I'm not sure why.

	reg modulo_addr_mode;
	initial modulo_addr_mode = 0;




// synopsys translate_on

	wire [31:0] iu_dva_e;
	wire [31:0] iu_dva_e_dc;
	wire [31:2] iu_iva_g;
	wire [13:3] icache_adr;
	wire [31:14] icache_tag_in;
	wire [31:0] DOUTpins;
	wire [1:0] FCC_SWAP = pfcc;

	Miuchip iuchip(
		little_endian,
		sel_last_gen, sel_recirc,
		select_IU_DOUT, select_FP_DOUT, sel_ldstb_1, src3,
		ld_iu, iu_dva_e, iu_dva_e_dc,
		ic_ibus, iu_iva_g, icache_adr, icache_tag_in,
		iu_iflush_e, force_dva,
		it_hit_f, enbl_itag_match_f, iwait_f,
		imiss_in_progress, start_itag_inv,
		ic_force_ifill_g, mm_istat_avail,
		i_dva_req,
		i_nfillp,
		byte_mark0_e, byte_mark1_e, byte_mark2_e, byte_mark3_e,
		FHOLD_SWAP,
		dc_shold,
		dt_hit_w, enbl_dtag_match_w, dwait_w, dwait_w_for_flush,
		iu_asi_e,
		ld_op_e, ld_op_e_mmu, ld_op_d, sgnd_ld_e,
		st_op_e, st_op_e_mmu, st_op_d,
		fpu_mem_e, size_e,
		ic_idle, mm_icache_enbl,
		mm_dacc_exc_w,
		mm_dacc_err_w,
		mm_dacc_mmu_miss_w, mm_dacc_wp_w,
		iu_mm_iacc_wp_exc_d,
		ic_mem_par, mm_fs_perr,
		mm_fs_lvl, mm_fs_iae, mm_fs_xerr, mm_fs_mmiss,
		mm_fs_sbe, mm_fs_sto, mm_fs_sptct,
		enbl_br_fold,
		ic_sup_only,
	iu_sfs_sup,
	iu_sfs_perr, iu_sfs_xerr, iu_sfs_mmiss,
	iu_sfs_iae, iu_sfs_sbe, iu_sfs_sto,
	iu_sfs_prtct, iu_sfs_priv, iu_sfs_lvl,
		ss_reset,
		FEXC_SWAP,
		FCC_SWAP, FCCV_SWAP,
		IU_IRL,
		error_mode,
		ss_clock,
		ss_scan_mode,
	valid_decode, fold_annul,
	pipe_hold4fpc,
	pipe_hold4fprf,
	pipe_hold4mmu_cntl,
	pipe_hold4mmu_dp,
	pipe_hold4dc, pipe_hold4dc_l, fast_hld_terms,
	pipe_hold4ic,
	ihold_d1, dhold_d1, did_fetch,
	TRAP,
	iu_epc, inst_for_fpc,
	IU_in_trap, IU_in_trap4fpu, IU_in_trap4dc,
	FXACK,
	enbl_fetch,
	hld_dirreg,
	iu_event, iu_sup_mode,
//	input_clock, input_clock_buf,
	Miu_scan_in,
	Miu_scan_out
		);

// Added spare cells 

        spares  Miu_spares ();
	

// synopsys translate_off

// dummy logic used for simulation only
// nextWE - value of next cycle's WE pulse output from the IU



// synopsys translate_on


	wire tagchk_op = 0;
	wire hst_op = 0;


endmodule

//--------------------------------------------------------------------------
//--------------------------------------------------------------------------










	/* top level for functional model of IU */


module Miuchip(
	little_endian, // added May 29, 96
	sel_last_gen, sel_recirc,
	select_IU_DOUT, select_FP_DOUT, sel_ldstb_1, src3,
	ld_iu, iu_dva_e, iu_dva_e_dc,
	ic_ibus, iu_iva_g, icache_adr, icache_tag_in,
	iu_iflush_e, force_dva,
	it_hit_f, enbl_itag_match_f, iwait_f,
	imiss_in_progress, start_itag_inv, ic_force_ifill_g, mm_istat_avail,
	i_dva_req,
	i_nfillp,
	byte_mark0_e, byte_mark1_e, byte_mark2_e, byte_mark3_e,
	FHOLD,
	dc_shold,
	dt_hit_w, enbl_dtag_match_w, dwait_w, dwait_w_for_flush,
	iu_asi_e,
	ld_op_e, ld_op_e_mmu, ld_op_d, sgnd_ld_e,
	st_op_e, st_op_e_mmu, st_op_d,
	fpu_mem_e, size_e,
	ic_idle, mm_icache_enbl,
	mm_dacc_exc_w, mm_dacc_err_w, mm_dacc_mmu_miss_w, mm_dacc_wp_w,
	iu_mm_iacc_wp_exc_d,
	ic_mem_par, mm_fs_perr,
	mm_fs_lvl, mm_fs_iae, mm_fs_xerr, mm_fs_mmiss,
	mm_fs_sbe, mm_fs_sto, mm_fs_sptct,
	enbl_br_fold,
	ic_sup_only,
	iu_sfs_sup,
	iu_sfs_perr, iu_sfs_xerr, iu_sfs_mmiss,
	iu_sfs_iae, iu_sfs_sbe, iu_sfs_sto,
	iu_sfs_prtct, iu_sfs_priv, iu_sfs_lvl,
	ss_reset,
	FEXC,
	pfcc, pfccv,
	IRL,
	error_mode,
	ss_clock,
	ss_scan_mode,
	valid_decode, fold_annul,
	pipe_hold4fpc,
	pipe_hold4fprf,
	pipe_hold4mmu_cntl,
	pipe_hold4mmu_dp,
	pipe_hold4dc, pipe_hold4dc_l, fast_hld_terms,
	pipe_hold4ic,
	ihold_d1, dhold_d1, did_fetch,
	TRAP,
	iu_epc, inst_for_fpc,
	IU_in_trap, IU_in_trap4fpu, IU_in_trap4dc,
	FXACK,
	enbl_fetch,
	hld_dirreg,
	iu_event, iu_sup_mode,
//	input_clock, input_clock_buf,
	Miu_scan_in,
	Miu_scan_out
	);

output little_endian;   // added May 29, 96
output sel_last_gen ;
output sel_recirc ;
//output [63:0] iu_dout;		// data output bus
output select_IU_DOUT;
output select_FP_DOUT;
output sel_ldstb_1;
output [31:0] src3;

input [31:0] ld_iu;	// read data bus
output [31:0] iu_dva_e;		// D cache address for MMU
output [31:0] iu_dva_e_dc;	// for D$

input [63:0] ic_ibus;	// data from the insr cache
output [31:2] iu_iva_g;	// I cache address
output [13:3] icache_adr;
output [31:14] icache_tag_in;

output iu_iflush_e;		// IFLUSH in E
output force_dva;

input it_hit_f;
input enbl_itag_match_f;
input iwait_f;

input imiss_in_progress;
input start_itag_inv;
input ic_force_ifill_g;
input mm_istat_avail;
input i_dva_req;
input [4:3] i_nfillp;

//output [0:3] iu_byte_marks_e;	// which bytes to write
output byte_mark0_e;
output byte_mark1_e;
output byte_mark2_e;
output byte_mark3_e;

input FHOLD;			// FPU Hold input

input dc_shold;			// generic hold from d cache

input dt_hit_w;
input enbl_dtag_match_w;
input dwait_w;
input dwait_w_for_flush;

// signals for MMU
output [5:0] iu_asi_e;		// ASI for inst in E

output ld_op_e;
output ld_op_e_mmu;
output ld_op_d;
output sgnd_ld_e;
output st_op_e;
output st_op_e_mmu;
output st_op_d;

output fpu_mem_e;
output [1:0] size_e;

input ic_idle;
input mm_icache_enbl;

input mm_dacc_exc_w;		// data acc exception
input mm_dacc_err_w;		// data access error
input mm_dacc_mmu_miss_w;
input mm_dacc_wp_w;

output iu_mm_iacc_wp_exc_d;	// IU detected potential WP trap in D

input [1:0] ic_mem_par;
input [1:0] mm_fs_perr;
input [1:0] mm_fs_lvl;
input mm_fs_iae;
input mm_fs_xerr;
input mm_fs_mmiss;
input mm_fs_sbe;
input mm_fs_sto;
input mm_fs_sptct;
input enbl_br_fold;
input ic_sup_only;

output iu_sfs_sup;
output [1:0] iu_sfs_perr;
output iu_sfs_xerr;
output iu_sfs_mmiss;
output iu_sfs_iae;
output iu_sfs_sbe;
output iu_sfs_sto;
output iu_sfs_prtct;
output iu_sfs_priv;
output [1:0] iu_sfs_lvl;

input ss_reset;			// reset input active low

input FEXC;			// FPU Exception

input [1:0] pfcc;		// FPU cc's
input pfccv;			// FPU cc's Valid

input [3:0] IRL;		// Interrupt Request Level

output error_mode;			// Error State

// input [5:0] ss_clock_iu;			// system clock input
input ss_clock;		// system clock input  6-5-96 

input ss_scan_mode;		// scan mode for IU

output valid_decode;
output fold_annul;

//output iu_pipe_hold;		// tell things outside of IU
output [2:0] pipe_hold4fpc;
output pipe_hold4fprf;
output pipe_hold4mmu_cntl;
output pipe_hold4mmu_dp;
output pipe_hold4dc;
output [1:0] pipe_hold4dc_l;
output fast_hld_terms;
output pipe_hold4ic;

output ihold_d1;		// for MMU performance counters
output dhold_d1;
output did_fetch;

output TRAP;			// TRAP detected

output [31:2] iu_epc;		// execute PC
output [31:0] inst_for_fpc;	// inst for FPU
//input [63:0] fp_dout;		// Store data from FP
output IU_in_trap;		// Tell CC that IU is trapping
output IU_in_trap4fpu;		// Tell FP that IU is trapping
output IU_in_trap4dc;		// ditto to D$
output FXACK;			// ack FP exception for FPU

//output iu_fetch_f;              // fetch in F stage
output enbl_fetch;
output hld_dirreg;		// for FP - strobe in data
output iu_event;		// special event opcode detected
output iu_sup_mode;		// perf counter for MMU

// input input_clock;		// IU buffers input clock from PLL to CC
// output input_clock_buf;

input Miu_scan_in;
output Miu_scan_out;

	reg END;	// flag used to indicate the end of an
			// interactive task
//--------------------------------------------------------------------------

	wire Miu_scan_in, Mdecode_scan_out;
	wire Mhold_control_scan_out, Mqueue_scan_out;
	wire Mexec_scan_out, Mpc_scan_out;	//, Mdcacheif_scan_out
	wire Mregfile_scan_out;
	wire Miu_scan_out = Mregfile_scan_out;


// STUBS for some external pins which don't have function anymore



//------------------------------------------------------------------------------
// INST QUEUE MODEL
	wire [31:0] inst_for_int;
	wire [31:0] inst_for_fpc;
	wire [10:0] iexc_for_int;
	wire [31:22] inst_for_br;
	wire [31:22] nq1_entry_hi;
	wire [10:2] iexc_for_br;
	wire [10:2] niexc1_hi;
	wire [31:2] last_gen;
	wire [31:2] fold_aa;
	wire [31:2] alt_tag;
	wire [3:0] ccm;			// master latched condition codes
	wire [31:2] fpc;

	Mqueue queue (
	.inst_for_int	(inst_for_int),
	.inst_for_fpc	(inst_for_fpc),
	.iexc_for_int	(iexc_for_int),
	.inst_for_br	(inst_for_br),
	.nq1_entry_hi	(nq1_entry_hi),
	.iexc_for_br	(iexc_for_br),
	.niexc1_hi	(niexc1_hi),
	.ic_ibus	(ic_ibus),
	.alt_tag	(alt_tag),
	.nalttag_low	(nalttag_low),
	.q3_iae		(q3_iae),
	.q3_ptc		(q3_ptc),
	.q2_iae		(q2_iae),
	.q2_ptc		(q2_ptc),
	.q1_iae		(q1_iae),
	.q1_ptc		(q1_ptc),
	.fold_aa	(fold_aa),
	.last_gen	(last_gen),
	.fpc		(fpc),
	.ic_mem_par	(ic_mem_par),
	.mm_fs_perr	(mm_fs_perr),
	.mm_fs_lvl	(mm_fs_lvl),
	.mm_fs_iae	(mm_fs_iae),
	.mm_fs_xerr	(mm_fs_xerr),
	.mm_fs_mmiss	(mm_fs_mmiss),
	.mm_fs_sbe	(mm_fs_sbe),
	.mm_fs_sto	(mm_fs_sto),
	.mm_fs_sptct	(mm_fs_sptct),
	.ic_sup_only	(ic_sup_only),
	.sel_shift1	(sel_shift1),
	.sel_shift2	(sel_shift2),
	.sel_shift3	(sel_shift3),
	.sel_fold1	(sel_fold1),
	.sel_fold2	(sel_fold2),
	.sel_even1	(sel_even1),
	.sel_even2	(sel_even2),
	.sel_even3	(sel_even3),
	.sel_odd1	(sel_odd1),
	.sel_odd2	(sel_odd2),
	.sel_odd3	(sel_odd3),
	.hold_q1	(hold_q1),
	.hold_q2	(hold_q2),
	.hold_q3	(hold_q3),
	.hold_q4	(hold_q4),
	.hold		(hold),
	.fetch_alt	(fetch_alt),
	.hold_alt	(hold_alt),
	.hld_dirreg	(hld_dirreg),
	.hld_dum_dpc	(hld_dum_dpc),
	.hld_backup	(hld_backup),
	.take_icdata	(take_icdata),
	.fetch_ic_even	(fetch_ic_even),
	.fetch_ic_odd	(fetch_ic_odd),
	.fetch_TOQ	(fetch_TOQ),
	.fetch_SIQ	(fetch_SIQ),
	.ncant_unload	(ncant_unload),
	.sel_old_aa	(sel_old_aa),
	.hld_dir2	(hld_dir2),
	.ss_clock	(ss_clock),
	.ss_scan_mode	(ss_scan_mode),
//	.input_clock	(input_clock),
//	.input_clock_l	(input_clock_l),
	.Mqueue_scan_in	(Mpc_scan_out),
	.Mqueue_scan_out	(Mqueue_scan_out)
	);


//--------------------------------------------------------------------------

	wire [31:0] in_dec;		// instr in decode

// PC MODULE


	wire [31:2] tpc;		// Trap PC register
	wire [31:2] wpc;		// Write PC mregister
	wire [31:2] iu_epc;		// Decode PC
	wire [31:4] tbrm;		// tbr input to PC module
	wire [31:0] alu_shift;
	wire [31:2] iu_iva_g;		// I cache address
	wire [13:3] icache_adr;
	wire [31:14] icache_tag_in;
//	wire [11:2] low_D_cache_adr = iu_dva_e[11:2];

	Mpc pc (
	.tpc 		(tpc),
	.wpc 		(wpc),
	.iu_epc		(iu_epc),
	.fpc		(fpc),
	.fpc_low	(fpc_low),
	.nlta_low	(nlta_low),
	.ndpc_low	(ndpc_low),
	.last_gen	(last_gen),
        .alu_shift_hi30 (alu_shift[31:2]),
        .tbrm 		(tbrm),
        .sadr_tbr 	(sadr_tbr),
	.sadr_jmprett 	(sadr_jmprett),
	.sadr_zero 	(sadr_zero),
	.fold_aa	(fold_aa),
	.sel_last_gen	(sel_last_gen),
	.recirc2_default	(recirc2_default),
	.sel_inc_ll_gen	(sel_inc_ll_gen),
	.sel_inc_dpc	(sel_inc_dpc),
	.sel_inc_alttag	(sel_inc_alttag),
	.sel_gpc	(sel_gpc),
	.sel_recirc	(sel_recirc),
	.sel_recirc_inc	(sel_recirc_inc),
	.sel_lgen_iva	(sel_lgen_iva),
	.sel_gpc_ic	(sel_gpc_ic),
	.sel_recirc_ic	(sel_recirc_ic),
	.sel_recirc_inc_ic	(sel_recirc_inc_ic),
	.sadr_zero_ic	(sadr_zero_ic),
	.force_ifill	(force_ifill),
	.force_dva	(force_dva),
	.sel_lgen_ica	(sel_lgen_ica),
	.imiss_in_progress	(imiss_in_progress),
	.i_nfillp	(i_nfillp[4:3]),
	.sel_lta_fpc	(sel_lta_fpc),
	.sel_idpc_fpc	(sel_idpc_fpc),
	.sel_post_reset	(sel_post_reset),
	.sel_p_fpc	(sel_p_fpc),
	.sel_alt_tag	(sel_alt_tag),
	.sel_i1pfpc_fpc	(sel_i1pfpc_fpc),
	.sel_i2dpc_fpc	(sel_i2dpc_fpc),
	.alt_tag	(alt_tag),
        .hld_dpc 	(hld_dpc),
	.hld_car_mar	(hld_car_mar),
	.hld_lgens	(hld_lgens),
	.iu_iva_g	(iu_iva_g),
	.icache_adr	(icache_adr),
	.icache_tag_in	(icache_tag_in),
	.fwd_wpc	(fwd_wpc),
	.use_tpc	(use_tpc),
	.fwd_tpcm4	(fwd_tpcm4),
        .ss_clock	(ss_clock),
	.hold		(hold),
	.lta_hold	(lta_hold),
	.hold_ic	(hold_ic),
        .reset		(reset),
	.start_itag_inv	(start_itag_inv),
	.ss_scan_mode	(ss_scan_mode),
//	.input_clock_l	(input_clock_l),
//	.input_clock_buf	(input_clock_buf),
	.pc_scan_in	(Miu_scan_in),	// should be pc_scan_in
	.pc_scan_out	(Mpc_scan_out)	// should be pc_scan_out
	);

//---------------------------------------------------------------------------
// INSTRUCTION REGISTER MODULE

//	wire [1:0] e_op, w_op, r_op;	// OP fields
//	wire [5:0] e_op3, w_op3, r_op3;	// OP3 fields

//	wire [4:0] d_rs1;		// RS1 in decode
//	wire [4:0] e_rd, w_rd;			// RD field in Execute
//	wire [7:0] w_rdp, nr_rdp;	// Other RD fields


/*
 * Moved to Mdecode

	Mir ir (
		.e_op		(e_op),
		.e_op3		(e_op3),
		.w_op		(w_op),
		.w_op3		(w_op3),
		.d_rs1		(d_rs1),
		.nbrs1_decm	(nbrs1_decm),
		.brs3_d		(brs3_d),
		.e_rd		(e_rd),
		.w_rdm		(w_rd),
		.w_rdp		(w_rdp),
		.nr_rdp		(nr_rdp),
		.in_dec		(in_dec),
		.d_imm_l	(d_imm_l),
		.e_asim		(e_asim),
		.iu_sfs_sup	(iu_sfs_sup),
		.iu_sfs_perr	(iu_sfs_perr),
		.iu_sfs_xerr	(iu_sfs_xerr),
		.iu_sfs_mmiss	(iu_sfs_mmiss),
		.iu_sfs_iae	(iu_sfs_iae),
		.iu_sfs_sbe	(iu_sfs_sbe),
		.iu_sfs_sto	(iu_sfs_sto),
		.iu_sfs_prtct	(iu_sfs_prtct),
		.iu_sfs_priv	(iu_sfs_priv),
		.iu_sfs_lvl	(iu_sfs_lvl),
		.inst_for_int	(inst_for_int),
		.ndec_inst_traps	(ndec_inst_traps),
		.hld_dirreg	(hld_dirreg),
		.ecwpm_		(ecwpm_),
		.ncwpm_l	(ncwpm_l),
		.hnop_into_ex	(hnop_into_ex),
		.htrap_into_ex	(htrap_into_ex),
		.clr_e_iexc_nop	(clr_e_iexc_nop),
		.set_rd0m	(set_rd0m),
		.clear_rd0m	(clear_rd0m),
		.d_rd_hstd_sel	(d_rd_hstd_sel),
		.write_r15	(write_r15),
		.write_r18	(write_r18),
		.result_r0	(result_r0),
		.TRAP		(TRAP),
		.fold_annul	(fold_annul),
		.ss_clock	(ss_clock),
		.hold		(hold),
		.ss_scan_mode	(ss_scan_mode),
		.Mir_scan_in	(Mpc_scan_out),		// ir_scan_in (stitcher will connect)
		.Mir_scan_out	(Mir_scan_out)		// ir_scan_out (ditto)
		);

 */

//--------------------------------------------------------------------------
// DECODE MODULE

	wire [7:0] wimm;			// Window Invalid mask
	wire [2:0] cwp;			// Current Window Pointer
	wire [3:0] pil;			// Processor Interrupt Level (PSR)
	wire [4:0] alu_out_lsb5;	// alu output 5 lsb's
	wire s;				// Supervisor bit
	wire et;			// ET bit from PSR
	wire [7:0] trapcode;		// TT value for trap each cycle
	wire [7:0] sa;			// fully decoded controls for Shift a
	wire [8:0] sb;			// fully decoded controls for Shift b
	wire [31:0] y;			// Y register
	wire [5:0] alu_s2m_5_0;
	wire [31:0] src2m;		// RF port B output
	wire [3:0] alu_cc_next;		// new CC's from ALU to CC register
//	wire [0:3] byte_marks;		// byte marks out of decode

	wire [2:0] ym_lo3;			// Y register
	wire [2:0] wcwpm1;
	wire [2:0] cwpp1;
	wire [2:0] cwpm1;
	wire [2:0] wcwp;
        wire [31:0] src1m;              // register file data outputs
	wire [31:0] src3;
//	wire [4:0] shift_cnt;		// Shift amount from decode logic
	wire [1:0] alu_s1s_lsb2;	// low 2 bits of alu_s1s input
	wire [2:0] iu_inst_ft;
	wire [1:0] iu_inst_lvl;
	wire [31:0] result;	// ALU result for regfile
	wire result_MSB = result[31];
	wire [6:0] result_lo = result[6:0];

	wire [7:0] nr_rdp;
	wire [7:0] brs3_d;
	wire [4:0] nbrs1_decm;		// rs1 in decode for RF
	wire [4:0] nbrs2_decm = inst_for_int[4:0];
	wire [2:0] cwpm_l, ecwpm_, ncwpm_l;
					// various CWPs (active low)

	wire iu_sfs_sup;
	wire [1:0] iu_sfs_perr;
	wire iu_sfs_xerr;
	wire iu_sfs_mmiss;
	wire iu_sfs_iae;
	wire iu_sfs_sbe;
	wire iu_sfs_sto;
	wire iu_sfs_prtct;
	wire iu_sfs_priv;
	wire [1:0] iu_sfs_lvl;
	wire [21:0] in_dec_lo22;
	wire [1:0] w_op;	// OP fields
	wire [5:0] w_op3;	// OP3 fields

	wire sup_ex_trap;
	wire this_s;
	wire [11:0] ndec_inst_traps =
		{this_s, iexc_for_int[10:3], sup_ex_trap, iexc_for_int[1:0]};

	Mdecode decode(
		.hld_dirreg	(hld_dirreg),
		.hld_dirreg_rf	(hld_dirreg_rf),
		.cwpm_		(cwpm_l),
		.ecwpm_		(ecwpm_),
		.TRAP		(TRAP),
		.trapcode	(trapcode),
		.resultMSB	(result_MSB),
		.result_lo	(result_lo),
		.high_2_1	(high_2_1),
		.idiv_shiftin_low (idiv_shiftin_low),
		.alu_s1m_0	(alu_s1m_0),
		.byte_mark0_e	(byte_mark0_e),
		.byte_mark1_e	(byte_mark1_e),
		.byte_mark2_e	(byte_mark2_e),
		.byte_mark3_e	(byte_mark3_e),
		.sadr_tbr	(sadr_tbr),
		.sadr_jmprett	(sadr_jmprett),
		.sadr_zero	(sadr_zero),
		.hld_dpc	(hld_dpc),
		.hld_dum_dpc	(hld_dum_dpc),
		.alus1_b1m	(alus1_b1m),
		.alus1_b2m	(alus1_b2m),
		.alus1_b3m	(alus1_b3m),
		.alus1_datam	(alus1_datam),
		.alus1_rfm_b3m	(alus1_rfm_b3m),
		.alus1_setm	(alus1_setm),
		.alus2_b1m	(alus2_b1m),
		.alus2_b2m	(alus2_b2m),
		.alus2_b3m	(alus2_b3m),
		.alus2_datam	(alus2_datam),
		.byp_res3	(byp_res3),
		.byp_wr3	(byp_wr3),
		.byp_rf3	(byp_rf3),
		.a2top_default	(a2top_default),
		.rs2_passit	(rs2_passit),
		.alu_s2_reg_hold (alu_s2_reg_hold),
		.alu_s2m_5_0	(alu_s2m_5_0),
		.src2m_lo	(src2m[3:0]),
		.rs1_pass	(rs1_pass),
		.spc_mux_default	(spc_mux_default),
		.rs1_clear	(rs1_clear),
		.rs1_double	(rs1_double),
		.nrs1_negate	(nrs1_negate),
		.nrs1_negate_l	(nrs1_negate_l),
		.sel_srl2_mult	(sel_srl2_mult),
		.rs2_clear	(rs2_clear),
		.nsel_w_mult	(nsel_w_mult),
		.nsel_w_mult_l_b (nsel_w_mult_l_b),
		.nsel_w_mult_l_not_b (nsel_w_mult_l_not_b),
		.sel_sll1_divalu (sel_sll1_divalu),
		.sel_sll1_divalu_l (sel_sll1_divalu_l),
		.msign_bit	(msign_bit),
		.src1m_msb	(src1m[31]),
		.dsign_bit2	(dsign_bit2),
		.rf2_imm_data_msb (rf2_imm_data_msb),
		.dsign_bit1	(dsign_bit1),
		.hold_Wreg	(hold_Wreg),
		.eopc_hidiv3	(eopc_hidiv3),
		.use_hi_y	(use_hi_y),
		.use_hi_alu	(use_hi_alu),
		.use_hi_rs1_default (use_hi_rs1_default),
		.use_hi_rs2	(use_hi_rs2),
		.use_low_rs1	(use_low_rs1),
		.use_hi_rs2_default (use_hi_rs2_default),
		.not_rs2_rs1_default (not_rs2_rs1_default),
		.alus1_b2_shift	(alus1_b2_shift),
		.sel_rs1_shiftin (sel_rs1_shiftin),
		.alu_ADD	(alu_ADD),
		.alu_AND	(alu_AND),
		.alu_XNOR	(alu_XNOR),
		.shift_left	(shift_left),
		.arith_shift	(arith_shift),
		.ym		(ym_lo3[2:0]),
		.alu_cc_next	(alu_cc_next),
		.ccN_noninv	(ccN_noninv),
		.ccZ_noninv	(ccZ_noninv),
		.ccm		(ccm),
		.ne_mulsm	(ne_mulsm),
		.next_e_not_negmul (next_e_not_negmul),
		.hld_y		(hld_y), 
		.wr_y		(wr_y),
		.wr_mulscc	(wr_mulscc),
		.n_ymsb		(n_ymsb),
		.carry_in	(carry_in),
		.pass_hi_rs1	(pass_hi_rs1),
		.det_divovf	(det_divovf),
		.tagged_ovf	(tagged_ovf),
		.alu_sub	(alu_sub),
		.alu_s1s_lsb2	(alu_s1s_lsb2),
		.rs_from_sh	(rs_from_sh),
		.rs_from_alu	(rs_from_alu),
		.rs_from_else	(rs_from_else),
		.force_neg	(force_neg),
		.force_pos	(force_pos),
		.e_rdpsrm	(e_rdpsrm),
		.e_rdwimm	(e_rdwimm),