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/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
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/******************************************************************************/ 
/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)rfxlate.v
***
***
****************************************************************************
****************************************************************************/

// @(#)rfxlate.v	1.3 5/26/92
//-----------------------------------------------------------------------------
// REGISTER FILE LOGICAL TO PHYSICAL TRANSLATION MODULE
// Mrf_xlate


// m4 doesn't work on the rest of this file with the usual quotes
// because these are used by verilog defines.
// change the quotes to very unlikely characters.
// also have to  .




module Mrf_xlate(phys_reg_no, log_reg_no, cwp_);
output [7:0] phys_reg_no;	// physical register number 0 to 127
input [4:0] log_reg_no;		// logical register number 0 to 31
input [2:0] cwp_;		// current window pointer 0 to 6 (active low)

/*
 * old for 120 registers
	// cwp active low, -1, modulo 7
	wire [2:0] cwpp1_ =
		// synopsys translate_off
		((cwp_==3'b001 || cwp_==3'b000)===1'bx) ? 'bx :
		// synopsys translate_on
		(cwp_==3'b001 || cwp_==3'b000) ? 3'b111 : cwp_ - 3'b001;

	// new for 120 registers
	wire [2:0] cwpmm1 = cwp_ - 3'b001;

	wire [3:0] in_blk =
		// synopsys translate_off
		((cwp_==3'b001)===1'bx) ? 'bx :
		// synopsys translate_on
		(cwp_==3'b001) ? 4'b1110 : {cwpp1_,1'b0};
	wire [3:0] local_blk = {cwpmm1, 1'b1};
	wire [3:0] out_blk = {cwp_, 1'b0};
 */

	wire [3:0] cwpp1_ = ({1'b0,cwp_}) + 4'b0001;
	wire high_in = ~cwp_[0] & ~cwp_[1] & ~cwp_[2];

	wire [4:0] in_blk = {high_in,cwp_,1'b0};
	wire [4:0] local_blk = {1'b0,cwp_,1'b1};
	wire [4:0] out_blk = {cwpp1_,1'b0};


	// the GLOBAL block is block 0.

	wire [4:0] global_blk = 0;

	// Physical register number is determined by selecting
	// 1 of the 4 possible blocks, and 1 register of 8 within
	// the block

	wire [4:0] mux_out;
    // Expanded macro begin.
    // cmux4(mux, 5,  mux_out, 		global_blk,  out_blk,  local_blk,  in_blk, 		({log_reg_no[4], log_reg_no[3]}))
    function [5:1] mux ;
        input [5:1] in0_fn ;
        input [5:1] in1_fn ;
        input [5:1] in2_fn ;
        input [5:1] in3_fn ;
        input [1:0] select_fn ;
        reg [5:1] out_fn ;
        begin
            case (select_fn) 
                2'b00:  out_fn = in0_fn ;
                2'b01: out_fn = in1_fn ;
                2'b10:  out_fn = in2_fn ;
                2'b11: out_fn = in3_fn ;
                default: out_fn = 65'hx;
            endcase
            mux = out_fn ;
        end
    endfunction
    assign  mux_out = mux(		global_blk,  out_blk,  local_blk,  in_blk, 		({log_reg_no[4], log_reg_no[3]})) ;
    // Expanded macro end.


	wire [7:0] phys_reg_no = {mux_out, log_reg_no[2:0]};


endmodule