/******************************************************************************/ 
/*                                                                            */ 
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
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/******************************************************************************/ 
/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)decode.v
***
***
****************************************************************************
****************************************************************************/
// @(#)decode.v	1.168 4/8/94
// decode.v
//-----------------------------------------------------------------------------
/*
	DECODE

	This file contains the instruction decode logic.


	The content of this file is the property of Sun Microsystems.

*/

/* Used to switch between expanded and non expanded equation forms */






module Mdata_byp1_1 (
	d_hop3,
        d_imm,
        d_rs1,
        d_rs2,
	d_rd,
        e_call,
        e_no_write,
        e_rd,
	hold,
	ss_clock,
	valid_decode,
// outs
        alus1_b1m,
        alus1_set,
        alus1_setm,
        alus2_b1m,
        b1_eq_src1,
        b1_eq_src2,
	byp_res3,
	drd_eq_erd,
	dfrd_eq_efrd,
	nbyp_res3,
        rd_ex_g0
	);

input [8:0] d_hop3;
input d_imm;
input [4:0] d_rs1;
input [4:0] d_rs2;
input [4:0] d_rd;
input e_call;
input e_no_write;
input [4:0] e_rd;
input hold;
input ss_clock;
input valid_decode;
output alus1_b1m;
output alus1_set;
output alus1_setm;
output alus2_b1m;
output b1_eq_src1;
output b1_eq_src2;
output byp_res3;
output drd_eq_erd;
output dfrd_eq_efrd;
output nbyp_res3;
output rd_ex_g0;

	wire [5:0] d_hop2 = d_hop3[8:3];

// SETHI INPUT to SRC1

	wire alus1_set = d_hop2==`SETHI;
	wire alus1_setm = d_hop2==`SETHI;

// check to see if d_rd is same as e_rd - in case we
// have to interlock ld followed by dependant store

	wire drd_eq_erd;
	reg_cmp5 cmp_drd_erd_st (drd_eq_erd, d_rd, e_rd);

// similar, except for FP.  check only high 4 bits
	wire dfrd_eq_efrd;
	reg_cmp4 cmp_dfrd_eq_efrd (dfrd_eq_efrd, d_rd[4:1], e_rd[4:1]);

// BYPASS 1 SRC 1

	// compare RD in execute with %g0

	assign rd_ex_g0 = e_rd==5'h0;

	// specifier comparison except on calls

	reg_cmp5 cmp_b1_eq_src1 (b1_eq_src1, d_rs1, e_rd);

/*
 * Use reg_cmp5 for this now
	wire b1_eq_src1 = d_rs1 == e_rd;
 */

	// specifier comparison for calls

	wire b1_src1_15 = ~d_rs1==5'h10;

	// special cases which prevent bypass 1

// JMP has a hlp cycle so don't use this bypass (1) to forward data
// Can't forward ld data on bypass1. interlock and use ld bypass.
// Stores don't have a dest reg.  Pipeline some of it for
// timing purposes.

	wire n_no_bypass1 =
		valid_decode
		& (d_hop3==`JMP
		  | d_hop3[8:5]==`MEM | d_hop3[8:5]==`HMEM
		  )
		;

	wire no_bypass1;
	Mflipflop_1 no_bypass1_reg_1(no_bypass1,n_no_bypass1, 		ss_clock,hold) ;

	wire alus1_b1m =
		((b1_eq_src1 & ~rd_ex_g0 & ~e_call) | (b1_src1_15 & e_call))
		& ~e_no_write & ~no_bypass1 & ~alus1_set;


// BYPASS 1 SRC 2
	
	// specifier comparison except on calls

	reg_cmp5 cmp_b1_eq_src2 (b1_eq_src2, d_rs2, e_rd);

/*
 * Use reg_cmp5 now
	wire b1_eq_src2 = d_rs2 == e_rd;
 */
	
	// specifier comparison for calls 

	wire b1_src2_15 = ~d_rs2==5'h10;

// JMP has a hlp cycle so don't use this bypass (1) to forward data
// Can't forward ld data on bypass1. interlock and use ld bypass.
// Stores don't have a dest reg.

	wire alus2_b1m =
		((b1_eq_src2 & ~rd_ex_g0 & ~e_call) | (b1_src2_15 & e_call))
		& ~d_imm & ~e_no_write & ~no_bypass1;

// determine bypass for port 3 (store port).  if bypass 1 would be
// used for the store data with the store in D, then in the next
// cycle (with store in E), you must use W registered data for
// the store data.

	wire rd_match_erd;
	reg_cmp5 cmp_drd_erd (rd_match_erd, d_rd, e_rd);
	wire p3_src3_15 = ~d_rd==5'h10;

	wire nbyp_res3 =
		((rd_match_erd & ~rd_ex_g0 & ~e_call) | (p3_src3_15 & e_call))
		& ~e_no_write & ~no_bypass1;

	wire byp_res3;
	Mflipflop_1 byp_res3_reg_1(byp_res3,nbyp_res3,ss_clock,hold) ;

endmodule



module Mdata_byp1_2 (
        alus1_b1m,
        alus1_set,
        alus2_b1m,
	nbyp_res3,
	cwpm_,
        d_imm,
        d_rs1pm,
        d_rs2pm,
	d_rd,
        det_divovf,
        dopc_hidiv0_op,
        dopc_hidiv1_op,
        dopc_hidiv3_op,
        help_ctr,
        signed_div,
        w_hop3_8_5,
        w_no_write,
        w_rdp,
// outs
        alus1_b2m,
        alus2_b2m,
        b2_eq_src1,
        b2_eq_src2,
	byp_wr3,
	byp_rf3,
        rd_wr_g0,
	hold,
	ss_clock
	);

input alus1_b1m;
input alus1_set;
input alus2_b1m;
input nbyp_res3;
input [2:0] cwpm_;
input d_imm;
input [7:0] d_rs1pm;
input [7:0] d_rs2pm;
input [4:0] d_rd;
input det_divovf;
input dopc_hidiv0_op;
input dopc_hidiv1_op;
input dopc_hidiv3_op;
input [5:0] help_ctr;
input signed_div;
input [8:5] w_hop3_8_5;
input w_no_write;
input [7:0] w_rdp;
output alus1_b2m;
output alus2_b2m;
output b2_eq_src1;
output b2_eq_src2;
output byp_wr3;
output byp_rf3;
output rd_wr_g0;
input hold;
input ss_clock;


// BYPASS 2 SRC 1

	// compare RD in write with %g0

	wire rd_wr_g0 = w_rdp==8'h00;

	// specifier comparison

	reg_cmp8 cmp_b2_eq_src1 (b2_eq_src1, d_rs1pm, w_rdp);

/*
 * Use reg_cmp8 instead
	wire b2_eq_src1 = d_rs1pm == w_rdp;
 */

	// use bypass1 to pass Y into src1 for IDIV

	wire b2_yforidiv =
		  dopc_hidiv0_op & help_ctr==6'b000010 & ~signed_div
		| dopc_hidiv1_op & help_ctr==6'b000000
		;

	// use bypass 1 to pass correction info for IDIV into src2

	wire b2_corrforidiv =
		dopc_hidiv3_op & ~det_divovf
		;

	// special cases which prevent bypass 2
	// Can't have bypasses when have HIMUL in decode
	// separate no_bypass2 into separate signals for
	// src1 and src2. w_hop3_8_5 = w_hop3[8:5]

	wire no_bypass2_src1 =
		w_hop3_8_5==`MEM | w_hop3_8_5==`HMEM
		;

	wire no_bypass2_src2 =
		w_hop3_8_5==`MEM | w_hop3_8_5==`HMEM
		;

	wire alus1_b2m_term1 =
		(b2_eq_src1 | b2_yforidiv)
		& ~(rd_wr_g0 & ~b2_yforidiv)
		& ~(w_no_write & ~b2_yforidiv)
		& ~no_bypass2_src1
		& ~alus1_b1m & ~alus1_set
		;

	wire alus1_b2m =
		  alus1_b2m_term1
		& ~alus1_b1m
		& ~no_bypass2_src1
		;


// BYPASS 2 SRC 2

	// specifier comparison

	reg_cmp8 cmp_b2_eq_src2 (b2_eq_src2, d_rs2pm, w_rdp);
/*
 * use reg_cmp8 instead
	wire b2_eq_src2 = d_rs2pm == w_rdp;
 */

	wire alus2_b2m_term1 =
		(b2_eq_src2 | b2_corrforidiv)
		& ~(rd_wr_g0 & ~b2_corrforidiv)
		& ~(d_imm & ~b2_corrforidiv)
		& ~(w_no_write & ~b2_corrforidiv)
		;

	wire alus2_b2m =
		  alus2_b2m_term1
		& ~no_bypass2_src2
		& ~alus2_b1m
		;

// bypass from reg file write data reg to port 3 (store port)

	wire [7:0] d_rdp;
	Mrf_xlate rd_xlate (d_rdp, d_rd, cwpm_);

	wire drdp_match_wrdp;
	reg_cmp8 cmp_p3_drdp_wrdp (drdp_match_wrdp, d_rdp, w_rdp);

	wire nbyp_wr3 =
		  drdp_match_wrdp & ~rd_wr_g0
		& ~w_no_write
		& ~nbyp_res3
		;

	wire byp_wr3;
	Mflipflop_1 byp_wr3_reg_1(byp_wr3,nbyp_wr3,ss_clock,hold) ;

	wire nbyp_rf3 = ~nbyp_res3 & ~nbyp_wr3;
	wire byp_rf3;
	Mflipflop_1 byp_rf3_reg_1(byp_rf3,nbyp_rf3,ss_clock,hold) ;

endmodule




module Md_r_reg_cmp (src1_match, src2_match, r_rd,
			ecwpm_, cwpm_, w_rd, d_rs1, d_rs2,
			ss_clock,hold);

/*
	This module is used to do a fast register comparison
	between the src reg in D and the dest reg in R.  This
	is for fast bypass3 determination
*/

output src1_match;
output src2_match;
output [4:0] r_rd;
input [2:0] ecwpm_;
input [2:0] cwpm_;
input [4:0] w_rd;
input [4:0] d_rs1;
input [4:0] d_rs2;
input ss_clock;
input hold;

	wire [2:0] ecwpm_p1 = ecwpm_ + 3'b001;
	wire [2:0] ecwpm_m1 = ecwpm_ - 3'b001;

	wire [2:0] rcwpm_;
	Mflipflop_3 rcwpm_reg_3(rcwpm_,ecwpm_,ss_clock,hold) ;

	wire [2:0] rcwpm_p1;
	Mflipflop_3 rcwpm_p1_reg_3(rcwpm_p1,ecwpm_p1,ss_clock,hold) ;

	wire [2:0] rcwpm_m1;
	Mflipflop_3 rcwpm_m1_reg_3(rcwpm_m1,ecwpm_m1,ss_clock,hold) ;

	wire match_same, match_p1, match_m1;

	reg_cmp3 chk_same(match_same, rcwpm_, cwpm_);
	reg_cmp3 chk_p1(match_p1, rcwpm_p1, cwpm_);
	reg_cmp3 chk_m1(match_m1, rcwpm_m1, cwpm_);

// might not need this result_r0 garbage - if the puppy traps,
// we ain't gonna be doing any bypass 3's.  and if w_no_write
// is on, r_no_write will be on in the next cycle.
//	wire [4:0] wx_rd;
//	CMUX2(wx_rd_mux,5,wx_rd,w_rd,5'b0,result_r0)

	wire [4:0] r_rd;
	Mflipflop_5 r_rd_reg_5(r_rd,w_rd,ss_clock,hold) ;

// if both the src and dest reg are globals, make it look like the
// cwp's matched
	wire both_glob1 = ~(d_rs1[4] | d_rs1[3] | r_rd[4] | r_rd[3]);
	wire match_same_g1 = match_same | both_glob1;

	wire both_glob2 = ~(d_rs2[4] | d_rs2[3] | r_rd[4] | r_rd[3]);
	wire match_same_g2 = match_same | both_glob2;


	wire match_low_src1;
	reg_cmp3 chk_low_1(match_low_src1, d_rs1[2:0], r_rd[2:0]);

	wire match_low_src2;
	reg_cmp3 chk_low_2(match_low_src2, d_rs2[2:0], r_rd[2:0]);

// next line is on if D-reg is an out reg and R-reg is an in reg
	wire d1out_rin = ~d_rs1[4] & d_rs1[3] & r_rd[4] & r_rd[3];
	wire d2out_rin = ~d_rs2[4] & d_rs2[3] & r_rd[4] & r_rd[3];

// next line is on if D-reg is an in reg and R-reg is an out reg
	wire d1in_rout = d_rs1[4] & d_rs1[3] & ~r_rd[4] & r_rd[3];
	wire d2in_rout = d_rs2[4] & d_rs2[3] & ~r_rd[4] & r_rd[3];

// next line is on if D-reg and R-reg reference the same type
	wire d1same_rd, d2same_rd;
	reg_cmp2 chk_hi1 (d1same_rd, d_rs1[4:3], r_rd[4:3]);
	reg_cmp2 chk_hi2 (d2same_rd, d_rs2[4:3], r_rd[4:3]);

// next line is on if one of the D-reg or R-reg if none of the
// above lines are on.  (ie: one of the regs is a local and the
// other is not)
	wire other1 = ~d1out_rin & ~d1in_rout & ~d1same_rd;
	wire other2 = ~d2out_rin & ~d2in_rout & ~d2same_rd;

// the low three bits must match too
	wire s1_same = match_low_src1 & match_same_g1;
	wire s1_p1 = match_low_src1 & match_p1;
	wire s1_m1 = match_low_src1 & match_m1;

// may be able to get rid of the other1 select depending on
// how the mux is built - ie: if none of the selects are active,
// the output goes to 0.
	wire src1_match;
	
    // Expanded macro begin.
    // cmux4dnm(src1_match_mux, 1, src1_match,  		s1_same,  d1same_rd, 			s1_p1,  d1in_rout, 			s1_m1,  d1out_rin,  		1'b0,  other1)
    function [1:1] src1_match_mux ;
        input [1:1] in0_fn ;
        input s0_fn ;
        input [1:1] in1_fn ;
        input s1_fn ;
        input [1:1] in2_fn ;
        input s2_fn ;
        input [1:1] in3_fn ;
        input s3_fn ;
        reg [1:1] out_fn ;
        begin
            case ({ other1,  d1out_rin,  d1in_rout,  d1same_rd}) /* synopsys parallel_case */
                4'b0001:        out_fn = in0_fn;
                4'b0010: out_fn = in1_fn;
                4'b0100:        out_fn = in2_fn;
                4'b1000: out_fn = in3_fn;
                default: out_fn = 65'hx;
            endcase
            src1_match_mux = out_fn ;
        end
    endfunction
    assign src1_match = src1_match_mux( 		s1_same,  d1same_rd, 			s1_p1,  d1in_rout, 			s1_m1,  d1out_rin,  		1'b0,  other1) ;
    // Expanded macro end.

// ditto for src 2
	wire s2_same = match_low_src2 & match_same_g2;
	wire s2_p1 = match_low_src2 & match_p1;
	wire s2_m1 = match_low_src2 & match_m1;

	wire src2_match;
	
    // Expanded macro begin.
    // cmux4dnm(src2_match_mux, 1, src2_match,  		s2_same,  d2same_rd, 			s2_p1,  d2in_rout, 			s2_m1,  d2out_rin,  		1'b0,  other2)
    function [1:1] src2_match_mux ;
        input [1:1] in0_fn ;
        input s0_fn ;
        input [1:1] in1_fn ;
        input s1_fn ;
        input [1:1] in2_fn ;
        input s2_fn ;
        input [1:1] in3_fn ;
        input s3_fn ;
        reg [1:1] out_fn ;
        begin
            case ({ other2,  d2out_rin,  d2in_rout,  d2same_rd}) /* synopsys parallel_case */
                4'b0001:        out_fn = in0_fn;
                4'b0010: out_fn = in1_fn;
                4'b0100:        out_fn = in2_fn;
                4'b1000: out_fn = in3_fn;
                default: out_fn = 65'hx;
            endcase
            src2_match_mux = out_fn ;
        end
    endfunction
    assign src2_match = src2_match_mux( 		s2_same,  d2same_rd, 			s2_p1,  d2in_rout, 			s2_m1,  d2out_rin,  		1'b0,  other2) ;
    // Expanded macro end.

endmodule



module Mdata_byp2 (
        TRAP,
        alus1_b1m,
        alus1_set,
        alus2_b1m,
        b2_eq_src1,
        b2_eq_src2,
        d_imm,
        d_opcode,
        det_divovf,
        dopc_hidiv3_op,
        dopc_himul0_op,
        dopc_himul1_op,
        dopc_himul2_op,
        e_hop3,
	fold_annul,
        help_ctr,
        hold,
        r_no_write,
        r_rd,
        rd_wr_g0,
	src1_match,
	src2_match,
        ss_clock,
        valid_decode,
// outs
        alus1_b3m,
        alus1_datam,
        alus2_b3m,
        alus2_datam,
        e_hldd,
        e_ldd,
        e_load,
        write_r15
	);

input TRAP;
input alus1_b1m;
input alus1_set;
input alus2_b1m;
// input alus2_rfm;
input b2_eq_src1;
input b2_eq_src2;
input d_imm;
input [10:0] d_opcode;
// input [7:0] d_rs1pm;
// input [7:0] d_rs2pm;
input det_divovf;
input dopc_hidiv3_op;
input dopc_himul0_op;
input dopc_himul1_op;
input dopc_himul2_op;
input [8:0] e_hop3;
input fold_annul;
input [5:0] help_ctr;
input hold;
input r_no_write;
input [4:0] r_rd;
input rd_wr_g0;
input src1_match;
input src2_match;
input ss_clock;
// input ss_scan_mode;
input valid_decode;
output alus1_b3m;
output alus1_datam;
output alus2_b3m;
output alus2_datam;
// output alus2_rfm_im_b3m;
output e_hldd;
output e_ldd;
output e_load;
output write_r15;

	wire [8:0] d_hop3 = d_opcode[10:2];

	wire [2:0] e_hop = e_hop3[8:6];

// LOAD DATA BYPASS

	// detect opcodes in Decode and pipe into Execute and Write

	wire d_load_op =
		  d_hop3==`LDSB | d_hop3==`LDSBA | d_hop3==`LDUB | d_hop3==`LDUBA
		| d_hop3==`LDSH | d_hop3==`LDSHA | d_hop3==`LDUH | d_hop3==`LDUHA
		| d_hop3==`LD | d_hop3==`LDA
		;

	wire d_load = valid_decode & d_load_op;

	wire e_load;
	Mflipflop_1 e_load_ff_1( e_load, d_load, 		ss_clock, hold) ;

		// e_load is used to determine load-data interlock.
		// there is not such an interlock for SWAP or LDSTB
		// because these are multi-cycle instructions.
		// IN FACT it is necessary to prevent an interlock
		// between these instructions and their OWN helps!
		// Especially in the cases where the destination register
		// is the same as one of the sources.
		// Therefore SWAP and LDSTB are excluded from e_load.

	wire e_atomic =
		  e_hop3==`SWAP | e_hop3==`SWAPA
		| e_hop3==`LDSTB | e_hop3==`LDSTBA
		;
	
	wire e_ldatom = (e_load | e_atomic) & ~fold_annul;

	wire w_load;
	Mflipflop_1 w_load_ff_1( w_load, e_ldatom, 		ss_clock, hold) ;

		// w_load is used to determine data bypasses. Such
		// bypasses DO occur for SWAP and LDSTB, therefore
		// these are included in this equation.
	
	wire e_ldd = (e_hop3==`LDD | e_hop3==`LDDA) & ~fold_annul;

	wire w_ldd;
	Mflipflop_1 w_ldd_ff_1( w_ldd, e_ldd, 		ss_clock, hold) ;

	wire d_hldd_op =
		d_opcode==`HLDD | d_opcode==`HLDDA;

	wire d_hldd = valid_decode & d_hldd_op;

	wire e_hldd;
	Mflipflop_1 e_hldd_ff_1( e_hldd, d_hldd, 		ss_clock, hold) ;

	wire w_hldd;
	wire w_hldd_ff_sdin;
	Mflipflop_1 w_hldd_ff_1( w_hldd, e_hldd, 		ss_clock, hold) ;

	// DATA BYPASS into SRC1

	// data bypasses have lower priority than bypass 1, and
	// by design will not conflict with bypass 2.

	wire alus1_datam_normal_term0 =
		(w_load | w_ldd | w_hldd)
		;

	wire alus1_datam_normal_term1 =
		  alus1_datam_normal_term0
		& b2_eq_src1 & ~rd_wr_g0
		;

	wire alus1_datam_normal_term2 =
		~alus1_b1m & ~alus1_set;

	wire alus1_datam =	// ~ss_scan_mode &
		 alus1_datam_normal_term1 & alus1_datam_normal_term2;


	// DATA BYPASS into SRC2

	wire alus2_datam_normal_term0 =
		(w_load | w_ldd | w_hldd)
		;

	wire alus2_datam_normal_term1 =
		  alus2_datam_normal_term0
		& b2_eq_src2 & ~rd_wr_g0
		& ~d_imm
		;

	wire alus2_datam = 	//~ss_scan_mode &
		  alus2_datam_normal_term1
		& ~alus2_b1m
		;

// BYPASS 3 SRC 1

	// compare RD in result with %g0
	wire rd_rs_g0 = r_rd==5'b00;

	// specifier comparison
/*
 * old - too slow for warthog - see Md_r_reg_cmp for src1_match
	reg_cmp8 cmp_b3_eq_src1 (b3_eq_src1, d_rs1pm, r_rdp);
 */


/*
 * too slow
// prevent bypass3 when have help instructions for imul or idiv
	wire rd_rs_g0 = r_rdp==8'h00;

	wire alus1_b3m =
		  b3_eq_src1 & ~rd_rs_g0
		& ~r_no_write & ~alus1_b2m & ~alus1_datam_normal
		& ~alus1_b1m & ~alus1_set
		& ~himul_in_d
		& ~hidiv_in_d
		;
 */

/*
 * diff mux structure for warthog

	wire alus1_b3m_term1 =
		  b3_eq_src1 & ~rd_rs_g0
		& ~r_no_write & ~alus1_b2m
		;

	wire alus1_b3m =
		  ~alus1_datam_normal_term1
		& alus1_datam_normal_term2
		& alus1_b3m_term1
		;
 */

	// this register is accessible only through scan.  if
	// it is set (Q=1), it forces the RF to bypass
	// the data in register to the output (src1) for that
	// first cycle only.  it will immediately clear on
	// the next clock edge.
	wire force_alus1b3m;
	Mflipflop_1 force_alus1b3m_reg_1(force_alus1b3m,1'b0,ss_clock,1'b0) ;

	wire alus1_b3m =
		  src1_match & ~rd_rs_g0 & ~r_no_write
		| force_alus1b3m
		;

// BYPASS 3 SRC 2

	// specifier comparison

/*
 * old - too slow for warthog - see Md_r_reg_cmp for src2_match
	reg_cmp8 cmp_b3_eq_src2 (b3_eq_src2, d_rs2pm, r_rdp);
 */

/*
 * use reg_cmp8 instead
	wire b3_eq_src2 = d_rs2pm == r_rdp;
 */


/*
 * too slow
	wire alus2_b3m =
		  b3_eq_src2 & ~rd_rs_g0
		& ~d_imm & ~r_no_write
		& ~alus2_b2m & ~alus2_datam_normal
		& ~alus2_b1m
		& ~himul_in_d
		& ~hidiv_in_d
		;
 */

/*
 * not for warthog
	wire alus2_b3m_term1 =
		  b3_eq_src2 & ~rd_rs_g0
		& ~d_imm & ~r_no_write
		;

	wire alus2_b3m =
		  alus2_b3m_term1
		& ~alus2_b1m
		& ~alus2_datam_normal_term1
		& ~alus2_b2m
		;
 */
	// this register is accessible only through scan.  if
	// it is set (Q=1), it forces the RF to bypass
	// the data in register to the output (src2) for that
	// first cycle only.  it will immediately clear on
	// the next clock edge.
	wire force_alus2b3m;
	Mflipflop_1 force_alus2b3m_reg_1(force_alus2b3m,1'b0,ss_clock,1'b0) ;

	wire alus2_b3m =
		  src2_match & ~rd_rs_g0 & ~r_no_write
		| force_alus2b3m;


// ALU SRC 2 IMMEDIATE

//	wire alus2_im =
//		  d_imm
//		& ~((dopc_himul0_op & help_ctr>6'b0) | dopc_himul1_op
//			| dopc_himul2_op
//			| dopc_hidiv3_op & ~det_divovf
//		   )
//		;
//
//	wire alus2_rfm_im_b3m = alus2_rfm | alus2_im;


// ALU SRC 2 FROM SHIFT AMOUNT

        // RD control
 
	wire e_hopcall = e_hop==`CALL;
 
        wire write_r15 = e_hopcall & ~TRAP;
 
/*****/
/*
 * See after instanciation of Mdata_source for definition of write_r17
 * and write_r18
        wire write_r17 = TRAP;
        wire write_r18 = trap_cyc1;
 *
 */
 
/*****/

endmodule


module Mdata_rf (
        ANNUL,
        TRAP,
	alus2_datam,
	cwpm_,
        d_nop,
        d_opcode,
        d_rs1,
        d_rs2,
        d_trap,
        del_resetm,
        dhop3_idivbasic_op,
        dhop3_imulbasic_op,
	fold_annul,
	mispredicted,
        dopc_hidiv0_op,
        dopc_hidiv1_op,
        dopc_hidiv2_op,
        dopc_himul0_op,
        dopc_himul1_op,
        dopc_himul2_op,
        hold,
        interlock,
        iacc_exc_mmumiss_d,
	reset,
	rs2_clear,
        ss_scan_mode,
        ss_clock,
        trap_cyc2,
        w_opcode,
//outs
        alu_s2_reg_hold,
        d_rs1pm,
        d_rs2pm,
        e_no_write,
        r_no_write,
        result_r0,
        rf_we_w,
	rs2_passit,
        w_no_write,
	wr_lddatam_l
	);

input ANNUL;
input TRAP;
input alus2_datam;
input [2:0] cwpm_;
input d_nop;
input [10:0] d_opcode;
input [4:0] d_rs1;
input [4:0] d_rs2;
input d_trap;
input del_resetm;
input dhop3_idivbasic_op;
input dhop3_imulbasic_op;
input fold_annul;
input mispredicted;
input dopc_hidiv0_op;
input dopc_hidiv1_op;
input dopc_hidiv2_op;
input dopc_himul0_op;
input dopc_himul1_op;
input dopc_himul2_op;
input hold;
input interlock;
input iacc_exc_mmumiss_d;
input reset;
input rs2_clear;
input ss_scan_mode;
input ss_clock;
input trap_cyc2;
input [10:0] w_opcode;
output alu_s2_reg_hold;
output [7:0] d_rs1pm;
output [7:0] d_rs2pm;
output e_no_write;
output r_no_write;
output result_r0;
output rf_we_w;
output rs2_passit;
output w_no_write;
/*output m3b3;                     // select for mux3 from byte 3
output m3b2;                     // select for mux3 from byte 2
output m3b1;                     // select for mux3 from byte 1
output m3b0;                     // select for mux3 from byte 0
output m20;                      // select for mux2 from 0
output m2b2;                     // select for mux2 from byte 2
output m2b0;                     // select for mux2 from byte 0
output m2s0;                     // select for mux2 from sign 0
output m2s2;                     // select for mux2 from sign 2
output m0m10;                    // select for mux0 & 1 from 2
output m0m1b0b1;                 // select for mux0 & 1 from byte 0 byte 1
output m0m1s0;                   // select for mux0 & 1 from sign 0
output m0m1s2;                   // select for mux0 & 1 from sign 2
output m0m1m2s1;                 // select for mux0 & 1 & 2 from sign 1
output m0m1m2s3;                 // select for mux0 & 1 & 2 from sign 3
*/
output wr_lddatam_l;             // select for write from result


	wire [5:0] d_hop2 = d_opcode[10:5];
	wire [8:0] d_hop3 = d_opcode[10:2];

	wire [8:0] w_hop3 = w_opcode[10:2];

// DUPLICATE REGISTER-FILE SOURCE SPECIFIER TRANSLATIONS

	/*
		The logic below duplicates logic in the register file
		which performs the register file logical to physical
		translation for the source addresses. This is required
		in order to do the bypass comparisons.
	*/

	wire [7:0] d_rs1pm;
	wire [4:0] d_rs1, d_rs2;

	Mrf_xlate rs1_xlate (d_rs1pm, d_rs1, cwpm_);

	wire [7:0] d_rs2pm;

	Mrf_xlate rs2_xlate (d_rs2pm, d_rs2, cwpm_);



// instructions and situations which don't write the IU register file

	wire d_no_write_op =
		  d_hop2==`BICC | d_hop2==`BFCC
		| d_hop3[8:4]==`MEMF
		| d_opcode==`HLDA
		| d_hop3[8:2]==`STI | d_hop3[8:2]==`STIA
		| d_hop3[8:2]==`HSTI | d_hop3[8:2]==`HSTIA
		| d_opcode==`HLDSTB | d_opcode==`HLDSTBA
		| d_opcode==`HSWAP | d_opcode==`HSWAPA
		| d_hop3[8:2]==`WR
		| d_hop3==`RETT | d_hop3==`TICC
		| d_hop3==`IFLUSH
		| d_opcode==`HIFLUSH0	// | d_opcode==HIFLUSH1
		| d_opcode==`HSTA0	// | d_opcode==HSTA1
		| d_opcode==`HRETT | d_opcode==`HJMP
		| d_hop3==`FPOP | d_hop3==`FPCMP
		| dhop3_imulbasic_op
		| dopc_himul0_op | dopc_himul1_op
		| dhop3_idivbasic_op
		| dopc_hidiv0_op | dopc_hidiv1_op
		| dopc_hidiv2_op
		;

// OLD		| d_hop3[8:6]==HSHIFTX	// HJMP and HRETT
//		| d_hop3[8:4]==HMEMF

	wire d_help = d_hop3[8];
	// if have inst in E with a help in D that gets annuled,
	// make sure to kill D write too.
	wire no_d_wr_fld_anl = d_help & fold_annul;

	wire d_no_write =
		  del_resetm | d_nop | iacc_exc_mmumiss_d | interlock
		| d_trap | ANNUL
		| d_no_write_op
		| TRAP
		| mispredicted & ~d_help
		| no_d_wr_fld_anl
		;