/******************************************************************************/
/* */
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/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)ir.v
***
***
****************************************************************************
****************************************************************************/
// @(#)ir.v 1.23 4/15/93
// ir.v
//----------------------------------------------------------------------------
/*
Instruction Register Pipeline
This file describes the instruction register pipeline from
the Decode IR register to the result IR slave.
It includes all of the datapath logic for the register file
source and destination pipelines, and the opcode pipeline (except
the help bits which are in decode.v (control).
*/
// m4 doesn't work on the rest of this file with the usual quotes
// because these are used by verilog defines.
// change the quotes to very unlikely characters.
// also have to .
![[Up: Mdecode ir]](v2html-up.gif)
module Mir
(
//-------------------------------------------------------------------------
// PORTS
// OUTPUTS
e_op, e_op3,
w_op, w_op3,
d_rs1, nbrs1_decm, brs3_d,
e_rd, w_rdm, w_rdp, nr_rdp,
in_dec, d_imm_l,
e_asim,
iu_sfs_sup,
iu_sfs_perr, iu_sfs_xerr, iu_sfs_mmiss,
iu_sfs_iae, iu_sfs_sbe, iu_sfs_sto,
iu_sfs_prtct, iu_sfs_priv, iu_sfs_lvl,
// INPUTS
inst_for_int, ndec_inst_traps, hld_dirreg,
ecwpm_, ncwpm_l,
// CONTROL
hnop_into_ex, htrap_into_ex, clr_e_iexc_nop,
set_rd0m, clear_rd0m,
d_rd_hstd_sel,
write_r15, write_r18,
result_r0,
TRAP, fold_annul,
// MISC
ss_clock, hold
);
//-----------------------------------------------------------------------------o
// PORT DECLARATIONS
// OUTPUTS
output [1:0] e_op; // op field in execute
output [5:0] e_op3; // op3 field in execute
output [1:0] w_op; // op field in write
output [5:0] w_op3; // op3 field in write
output [4:0] d_rs1; // RS1 for decode logic
output [4:0] nbrs1_decm; // RS1 for RF
output [7:0] brs3_d;
//output [4:0] brs2_decm; // RS2 for RF
output [4:0] e_rd; // RD in execute cycle (to comparators)
output [4:0] w_rdm;
output [7:0] w_rdp; // RD in write cycle (to comparators)
output [7:0] nr_rdp;
output [31:0] in_dec; // instruction in decode (to FPU)
output d_imm_l; // d_imm active low
output [5:0] e_asim; // ASI field in the E cycle
output iu_sfs_sup;
output [1:0] iu_sfs_perr;
output iu_sfs_xerr;
output iu_sfs_mmiss;
output iu_sfs_iae;
output iu_sfs_sbe;
output iu_sfs_sto;
output iu_sfs_prtct;
output iu_sfs_priv;
output [1:0] iu_sfs_lvl;
// INPUTS
input [31:0] inst_for_int; // next instruction to decode (from queue)
input [11:0] ndec_inst_traps;
input hld_dirreg; // hold due to DIR
input [2:0] ecwpm_; // CWP for RD address translation (active low)
input [2:0] ncwpm_l;
// CONTROL
input hnop_into_ex; // force HNOP into E stage
input htrap_into_ex; // force HTRAP into E stage
input clr_e_iexc_nop; // force 0 into trap status for e stage
input set_rd0m; // force rd[0] =v 1
input clear_rd0m; // force rd[0] = 0
input d_rd_hstd_sel;
input write_r15; // force dest specifier in write stage to 15
// input write_r17; // force dest specifier in write stage to 17
// write_r17 is same as TRAP
input write_r18; // force dest specifier in write stage to 18
input result_r0; // force result write to %g0
input TRAP; // force HNOP in W and R opcodes
input fold_annul;
// MISC
input ss_clock; // system clock
input hold; // chip hold
/*
* NOTES
For synopsys, several signals that were outputs of this
module that are groupings of fields of the instruction
registers have been removed. instead, they are instanced
at the iu.v level with the actual instruction register
name (eg: in_dec) rather than as individual fields
(eg: disp22 -> in_dec[21:0]).
Follow are the collapsed names:
d_op in_dec[31:30]
d_rd in_dec[29:25]
d_op3 in_dec[24:19]
d_imm in_dec[13]
d_asi in_dec[12:5]
d_rs2 in_dec[4:0]
d_anl in_dec[29]
d_cond in_dec[28:25]
disp22 in_dec[21:0]
brs1_decm (same as d_rs1, which is special)
brs2_decm in_dec[4:0] (just like d_rs2)
*
*/
//------------------------------------------------------------------------------
// DECODE stage
// DIR register
// OP RD OP3 RS1 IMM ASI RS2
wire [31:0] in_dec;
wire [1:0] d_op = in_dec[31:30];
wire [4:0] d_rd_almost = in_dec[29:25];
wire [4:0] d_rd_inc = ({in_dec[29:26],1'b1});
wire [4:0] d_rd;
// Expanded macro begin.
// cmux2(d_rd_mux, 5, d_rd, d_rd_almost, d_rd_inc, d_rd_hstd_sel)
function [5:1] d_rd_mux ;
input [5:1] in0_fn ;
input [5:1] in1_fn ;
input select_fn ;
reg [5:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
d_rd_mux = out_fn ;
end
endfunction
assign d_rd = d_rd_mux(d_rd_almost, d_rd_inc, d_rd_hstd_sel) ;
// Expanded macro end.
wire [5:0] d_op3 = in_dec[24:19];
wire d_imm_l = ~in_dec[13];
// synopsys translate_off
wire d_imm = in_dec[13];
wire [7:0] d_asi = in_dec[12:5];
wire [4:0] d_rs2 = in_dec[4:0];
// synopsys translate_on
wire [4:1] e_rdm; // Forward declaration
wire [4:0] e_rs1m; // Forward declaration
// compute physical RF address for store read data from read port 3.
// this will be piped to the E stage where the reg is read.
// for STD - need to increment this by 1 on the second reg.
wire [2:0] cwpm_l;
Mflipflop_3 cwpm_l_reg_3(cwpm_l,ncwpm_l,ss_clock,hold) ;
wire [7:0] brs3_dxl;
Mrf_xlate rs_st_xlate (brs3_dxl, d_rd, cwpm_l);
wire [7:0] lbrs3_d_xl;
Mflipflop_8 lbrs3_d_xl_reg_8(lbrs3_d_xl,brs3_dxl,ss_clock,hold) ;
wire [7:0] brs3_d;
// Expanded macro begin.
// cmux2(brs3_d_mux, 8, brs3_d, brs3_dxl, ({lbrs3_d_xl[7:1],1'b1}), d_rd_hstd_sel)
function [8:1] brs3_d_mux ;
input [8:1] in0_fn ;
input [8:1] in1_fn ;
input select_fn ;
reg [8:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
brs3_d_mux = out_fn ;
end
endfunction
assign brs3_d = brs3_d_mux(brs3_dxl, ({lbrs3_d_xl[7:1],1'b1}), d_rd_hstd_sel) ;
// Expanded macro end.
wire hld_dirreg_real = hld_dirreg | hold;
wire [4:0] d_rs1;
Mflipflop_5 d_rs1_reg_5(d_rs1,inst_for_int[18:14],ss_clock,hld_dirreg_real) ;
// need a duplicate copy of d_rs1 because we don't have enough
// drive to drive both control and the RF.
// REGWIRE [4:0] brs1_decm;
// REG(d_brs1_reg,5,brs1_decm,nd_rs1,ss_clock,hld_drs1_reg)
// Don't register in Mir anymore - move this reg to Mregfile
// it is possible that nbrs1_decm can simply be connected to
// inst_for_int[18:14]
wire [4:0] nbrs1_decm = inst_for_int[18:14];
// This signal used be from eir. Changed to dir in SUNERGY.
// synopsys translate_off
wire [21:0] disp22 = in_dec[21:0];
// synopsys translate_on
Mflipflop_32 dir_reg_32( in_dec, inst_for_int, ss_clock, hld_dirreg_real) ;
// synopsys translate_off
wire ifori_dummy31, ifori_dummy24, ifori_dummy21;
wire ifori_dummy20, ifori_dummy19;
Mflipflop_1 ifori_dummy31_reg_1(ifori_dummy31,inst_for_int[31],ss_clock, hld_dirreg_real) ;
Mflipflop_1 ifori_dummy24_reg_1(ifori_dummy24,inst_for_int[24],ss_clock, hld_dirreg_real) ;
Mflipflop_1 ifori_dummy21_reg_1(ifori_dummy21,inst_for_int[21],ss_clock, hld_dirreg_real) ;
Mflipflop_1 ifori_dummy20_reg_1(ifori_dummy20,inst_for_int[20],ss_clock, hld_dirreg_real) ;
Mflipflop_1 ifori_dummy19_reg_1(ifori_dummy19,inst_for_int[19],ss_clock, hld_dirreg_real) ;
// synopsys translate_on
wire [11:0] d_iexc;
Mflipflop_12 d_iexc_reg_12(d_iexc,ndec_inst_traps,ss_clock,hld_dirreg_real) ;
// need a duplicate copy of d_rs2 because we don't have enough
// drive to drive both control and the RF.
// REGWIRE [4:0] brs2_decm;
// REG(brs2_reg,5,brs2_decm,inst_for_int[4:0],ss_clock,hld_dirreg_real)
// Don't register in Mir anymore - move this reg to Mregfile
// hook nbrs2_decm direct to inst_for_int[4:0]
// OPCODE mux for inserting HNOP and HTRAP
wire [7:0] dx_opop3;
wire [1:0] dx_op = dx_opop3[7:6]; // op from mux into E stage
wire [5:0] dx_op3 = dx_opop3[5:0]; // op3 from mux into E stage
// default control passes {d_op, d_op3} into E stage
wire dec_into_ex = ~(hnop_into_ex | htrap_into_ex);
// Expanded macro begin.
// cmux3dnm(hnop_mux, 8, dx_opop3, ({d_op, d_op3}), dec_into_ex, `ONOP, hnop_into_ex, `OTRAP, htrap_into_ex)
function [8:1] hnop_mux ;
input [8:1] in0_fn ;
input s0_fn ;
input [8:1] in1_fn ;
input s1_fn ;
input [8:1] in2_fn ;
input s2_fn ;
reg [8:1] out_fn ;
begin
case ({ htrap_into_ex, hnop_into_ex, dec_into_ex}) /* synopsys parallel_case */
3'b001: out_fn = in0_fn;
3'b010: out_fn = in1_fn;
3'b100: out_fn = in2_fn;
default: out_fn = 65'hx;
endcase
hnop_mux = out_fn ;
end
endfunction
assign dx_opop3 = hnop_mux( ({d_op, d_op3}), dec_into_ex, `ONOP, hnop_into_ex, `OTRAP, htrap_into_ex) ;
// Expanded macro end.
// also clear the iexc from D to E if both invalid address error and
// protection violation is on - this indicates a watchpoint trap and
// no status needs to be returned to the MMU.
wire clr_e_iexc =
htrap_into_ex
| clr_e_iexc_nop
| d_iexc[6] & d_iexc[3]
;
wire [11:0] const_0 = 12'b0;
wire [11:0] ne_iexc;
// Expanded macro begin.
// cmux2(ne_iexc_mux, 12, ne_iexc, d_iexc, const_0, clr_e_iexc)
function [12:1] ne_iexc_mux ;
input [12:1] in0_fn ;
input [12:1] in1_fn ;
input select_fn ;
reg [12:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
ne_iexc_mux = out_fn ;
end
endfunction
assign ne_iexc = ne_iexc_mux(d_iexc, const_0, clr_e_iexc) ;
// Expanded macro end.
// synopsys translate_off
wire d_anl = d_rd[4];
wire [3:0] d_cond = d_rd[3:0];
// synopsys translate_on
//------------------------------------------------------------------------------
// EXECUTE stage
// EIR master
// OP RD OP3 RS1 IMM ASI RS2
wire [31:0] in_ex_scanm;
wire [1:0] e_op;
wire [5:0] e_op3;
wire [14:0] in_rs_scan; // used to be a reg
wire [31:0] in_ex_scan; // used to be a reg
wire eira_mux_sdin;
wire [5:0] e_asi;
Mflipflop_6 e_asim_all_reg_6(e_asi,in_dec[10:5],ss_clock,hold) ;
wire [5:0] e_asim = e_asi[5:0];
Mflipflop_4 e_rdm_reg_4(e_rdm[4:1],in_dec[29:26], ss_clock, hold) ;
wire ne_rd0_r = (set_rd0m | in_dec[25]) & ~clear_rd0m;
wire e_rd0_r;
Mflipflop_1 e_rd0_r_reg_1(e_rd0_r,ne_rd0_r, ss_clock,hold) ;
wire [1:0] eir_op_mux_out = dx_op;
wire eir_op_mux_sdin;
Mflipflop_2 eir_op_mas_2( e_op, eir_op_mux_out, ss_clock, hold) ;
wire [5:0] eir_op3_mux_out = dx_op3;
wire eir_op3_mux_sdin;
Mflipflop_6 eir_op3_mas_6( e_op3, eir_op3_mux_out, ss_clock, hold) ;
// logic to control the lsb of RD for LDD and STD
wire [4:0] e_rd;
assign e_rd[4:1] = e_rdm[4:1];
assign e_rd[0] = e_rd0_r;
// assign e_rd[0] = (set_rd0m | e_rdm[0]) & ~clear_rd0m;
// crossover mux
/* Data path for SUNERGY. This signal should come from dir instead of eir master.
wire [21:0] disp22 = in_exam[21:0];
*/
assign in_ex_scan = in_ex_scanm;
// defined for convenience
wire [31:0] in_ex = {e_op, e_rd, e_op3,6'h0, 2'b0, e_asi,5'b0};
wire [11:0] e_iexc;
Mflipflop_12 e_iexc_reg_12(e_iexc,ne_iexc,ss_clock,hold) ;
// rd mux for introducing trap and call register constants
wire [4:0] ex_rd;
wire [4:0] const_15 = 5'd15; // simplify mux argument
wire [4:0] const_17 = 5'd17; // simplify mux argument
wire [4:0] const_18 = 5'd18; // simplify mux argument
wire write_r17 = TRAP;
// Expanded macro begin.
// cmux4dnm(rd_mux, 5, ex_rd, e_rd, ~(write_r15 | write_r17 | write_r18), const_15, write_r15, const_17, write_r17, const_18, write_r18)
function [5:1] rd_mux ;
input [5:1] in0_fn ;
input s0_fn ;
input [5:1] in1_fn ;
input s1_fn ;
input [5:1] in2_fn ;
input s2_fn ;
input [5:1] in3_fn ;
input s3_fn ;
reg [5:1] out_fn ;
begin
case ({ write_r18, write_r17, write_r15, ~(write_r15 | write_r17 | write_r18)}) /* synopsys parallel_case */
4'b0001: out_fn = in0_fn;
4'b0010: out_fn = in1_fn;
4'b0100: out_fn = in2_fn;
4'b1000: out_fn = in3_fn;
default: out_fn = 65'hx;
endcase
rd_mux = out_fn ;
end
endfunction
assign ex_rd = rd_mux( e_rd, ~(write_r15 | write_r17 | write_r18), const_15, write_r15, const_17, write_r17, const_18, write_r18) ;
// Expanded macro end.
// mux for inserting NOP into the W stage on TRAP or folded annul
wire [7:0] ex_opop3;
wire [1:0] ex_op = ex_opop3[7:6];
wire [5:0] ex_op3 = ex_opop3[5:0];
wire hnop_to_w = fold_annul | TRAP;
// Expanded macro begin.
// cmux2(hnop_wr_mux, 8, ex_opop3, ({e_op, e_op3}), `ONOP, hnop_to_w)
function [8:1] hnop_wr_mux ;
input [8:1] in0_fn ;
input [8:1] in1_fn ;
input select_fn ;
reg [8:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
hnop_wr_mux = out_fn ;
end
endfunction
assign ex_opop3 = hnop_wr_mux( ({e_op, e_op3}), `ONOP, hnop_to_w) ;
// Expanded macro end.
wire [11:0] nw_iexc;
// Expanded macro begin.
// cmux2(nw_iexc_mux, 12, nw_iexc, e_iexc, const_0, hnop_to_w)
function [12:1] nw_iexc_mux ;
input [12:1] in0_fn ;
input [12:1] in1_fn ;
input select_fn ;
reg [12:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
nw_iexc_mux = out_fn ;
end
endfunction
assign nw_iexc = nw_iexc_mux(e_iexc, const_0, hnop_to_w) ;
// Expanded macro end.
//-------------------------------------------------------------------------
// WRITE stage
// WIR master
wire [20:0] in_wr_scanm;
wire [18:6] wir_in = ({ex_op, ex_rd, ex_op3});
wire [1:0] w_op;
Mflipflop_2 w_op_reg_2(w_op,wir_in[18:17],ss_clock,hold) ;
wire [4:0] w_rdm;
Mflipflop_5 w_rdm_reg_5(w_rdm,wir_in[16:12],ss_clock,hold) ;
wire [5:0] w_op3;
Mflipflop_6 w_op3_reg_6(w_op3,wir_in[11:6],ss_clock,hold) ;
wire hld_wiexc = hold & ~TRAP;
wire [11:0] w_iexc;
Mflipflop_12 w_iexc_reg_12(w_iexc,nw_iexc,ss_clock,hld_wiexc) ;
wire iu_sfs_sup = w_iexc[11];
wire [1:0] iu_sfs_perr = w_iexc[10:9];
wire iu_sfs_xerr = w_iexc[8];
wire iu_sfs_mmiss = w_iexc[7];
wire iu_sfs_iae = w_iexc[6];
wire iu_sfs_sbe = w_iexc[5];
wire iu_sfs_sto = w_iexc[4];
wire iu_sfs_prtct = w_iexc[3];
wire iu_sfs_priv = w_iexc[2];
wire [1:0] iu_sfs_lvl = w_iexc[1:0];
// Write PORT register file logical to physical translation
wire [7:0] w_rdp; // write stage RD physical address
Mrf_xlate rd_xlate (w_rdp, w_rdm, ecwpm_);
// WIR slave
// RD_mux for forcing %G0 into RD
wire [7:0] wx_rdp;
wire [7:0] eight_zeros = 8'h00; // simplify mux argument
// Expanded macro begin.
// cmux2(rd_muxz, 8, wx_rdp, w_rdp, eight_zeros, result_r0)
function [8:1] rd_muxz ;
input [8:1] in0_fn ;
input [8:1] in1_fn ;
input select_fn ;
reg [8:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
rd_muxz = out_fn ;
end
endfunction
assign wx_rdp = rd_muxz( w_rdp, eight_zeros, result_r0) ;
// Expanded macro end.
// synopsys translate_off
wire [5:0] w_asim;
Mflipflop_6 w_asim_reg_6(w_asim,e_asi,ss_clock,hold) ;
// defined for convenience
wire [5:0] w_asi = w_asim;
wire [31:0] in_wr = {w_op,5'b0, w_op3, 6'h0, 2'b0, w_asi, 5'b0};
// mux for inserting HNOP into R on TRAP
wire [7:0] wx_opop3;
wire [1:0] wx_op = wx_opop3[7:6];
wire [5:0] wx_op3 = wx_opop3[5:0];
// Expanded macro begin.
// cmux2(hnop_rs_mux, 8, wx_opop3, ({w_op, w_op3}), `ONOP, TRAP)
function [8:1] hnop_rs_mux ;
input [8:1] in0_fn ;
input [8:1] in1_fn ;
input select_fn ;
reg [8:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
hnop_rs_mux = out_fn ;
end
endfunction
assign wx_opop3 = hnop_rs_mux( ({w_op, w_op3}), `ONOP, TRAP) ;
// Expanded macro end.
// synopsys translate_on
//------------------------------------------------------------------------
// RESULT stage
// RIR master
// synopsys translate_off
wire [14:0] rir_in = ({wx_op, wx_rdp[6:0], wx_op3});
// synopsys translate_on
wire [7:0] nr_rdp = wx_rdp;
// synopsys translate_off
// not part of design
wire [7:0] r_rdp;
Mflipflop_8 r_rdp_reg_8(r_rdp,wx_rdp,ss_clock,hold) ;
// synopsys translate_on
// RIR slave
// synopsys translate_off
wire [14:0] in_rs_scanm;
Mflipflop_15 rir_mas_15( in_rs_scanm, rir_in, ss_clock, hold) ;
wire [1:0] r_op = in_rs_scan[14:13];
// wire [6:0] r_rdp = in_rs_scan[12:6];
wire [5:0] r_op3 = in_rs_scan[5:0];
assign in_rs_scan = in_rs_scanm;
// defined for convenience
wire [31:0] in_rs = {r_op, 5'b0, r_op3, 19'h0};
// synopsys translate_on
//---------------------------------------------------------------------------
// DISPLAY TASK
// synopsys translate_off
task disp;
begin
// DECODE
// D: 12345678 123456 12 1234
$display(" OPCODE Rd SRC1 SRC2");
$write("D: ");
Mdisassemble.disp_instr(
{`IU.iuchip.decode.mm_iacc_exc_d, in_dec},
`IU.iuchip.decode.ir_control.d_hhn,
`IU.iuchip.decode.d_nop
);
if(d_op==2'h1) begin // CALL
$write("OFFSET=0x%x words",
{d_rd, d_op3, d_rs1, d_imm, d_asi, d_rs2});
end
else if(d_op==2'h0) begin // FORMAT 2
if(d_op3[5:3]==3'b100) begin
// SETHI
$write(" %x", d_rd);
$write(" %x",
{d_op3[2:0],d_rs1, d_imm, d_asi, d_rs2, 10'b0});
end
else begin // BRANCH
$write(" %x", d_rd);
$write(" OFFSET=0x%x words",
{d_op3[2:0],d_rs1, d_imm, d_asi, d_rs2});
end
end
else begin // FORMAT 3
$write(" %x", d_rd);
$write(" %x", d_rs1);
if(d_imm)
$write(" %x", {d_asi, d_rs2});
else
$write(" %x", d_rs2);
end
$write(" ");
if(hnop_into_ex)$write("hnop_into_ex ");
if(htrap_into_ex)$write("htrap_into_ex ");
if(set_rd0m)$write("set_rd0 ");
if(clear_rd0m)$write("clear_rd0 ");
// if(crossoverm) $write("crossover ");
$display;
// EXECUTE
$write("E: ");
Mdisassemble.disp_instr( {1'b0, in_ex}, `IU.iuchip.decode.ir_control.e_hhn, 0);
$write(" %x", e_rd);
$write(" ");
if(write_r15) $write("write_r15 ");
if(write_r17) $write("write_r17 ");
if(write_r18) $write("write_r18 ");
$display("ecwpm=%x", ~ecwpm_);
// WRITE
$write("W: ");
Mdisassemble.disp_instr( {1'b0, in_wr}, `IU.iuchip.decode.ir_control.w_hhn, 0);
$write(" ");
if(w_op==2'h0 && w_op3[5:3]!= 3'b100) // BRANCH
$write("%x", w_rdp);
else Mtask.disp_laddr(Mtask.phy2log(w_rdp));
$write(" ");
if(result_r0) $write("result_r0 ");
$display;
// RESULT
$write("R: ");
Mdisassemble.disp_instr({1'b0, in_rs}, `IU.iuchip.decode.ir_control.r_hhn, 0);
$write(" ");
if(r_op==2'h0 && r_op3[5:3]!= 3'b100) // BRANCH
$write("%x", r_rdp);
else Mtask.disp_laddr(Mtask.phy2log(r_rdp));
$display;
$display("---------------------------------------------------------------------------");
#0 Mclocks.STOP = ~Mclocks.STOP;
end
endtask
// synopsys translate_on
endmodule
/*
* bring d_rs1 into register instead - mux one cycle before below stuff
// wire no_crossover = ~crossoverm & ~pcrossoverm;
// wire crossover1 = crossoverm & ~pcrossoverm;
wire [4:0] d_rs1;
wire [4:0] nc_d_rs1 = in_dec[18:14]; // simplify mux argument
wire [4:0] e_rdm_clr = {e_rdm[4:1],1'b0};
wire [4:0] p_e_rdm = {e_rdm[4:1],1'b1}; // simplify mux argument
CMUX4D(dest_reg_mux,5, d_rs1, nc_d_rs1, no_crossover, e_rdm, crossover_sm, e_rdm_clr, crossover_dm, p_e_rdm, pcrossoverm)
// During crossover operations (eg: store), the rd field is used
// to READ the register file in the next cycle. Bring the rd field
// from e cycle to the d cycle rs1. On STD, need to read the
// next register, so use pcrossoverm (pipelined version of crossoverm)
// to do set up the correct register for d_rs1.
wire [4:0] nc_f_rs1 = inst_for_int[18:14];
wire [4:0] r_rd_clr = {in_dec[29:26],1'b0};
wire [4:0] p_d_rd = {in_dec[29:26],1'b1};
wire [4:0] nd_rs1;
CMUX4D(dest_reg_mux,5,nd_rs1, nc_f_rs1, no_crossover, in_dec[29:25], crossover_sm, r_rd_clr, crossover_dm, p_d_rd, pcrossoverm)
*
*/
| This page: |
Created: | Thu Aug 19 12:01:35 1999 |
| From: |
../../../sparc_v8/ssparc/iu/Mdecode/rtl/ir.v
|