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// @(#)rl_cyc_ctr.v	1.6 4/30/93

// Cycle Counter


module rl_cyc_ctr (
    terminal_count_l,
    hold_count,

    ss_scan_mode,
    ss_scan_in,
    ss_scan_out,

    rcc_rst_even_l,
    rcc_clk
) ;

    output terminal_count_l ;
    input hold_count ;
    input rcc_rst_even_l ;
    input rcc_clk ;

    input ss_scan_mode ;
    input ss_scan_in ;
    output ss_scan_out ;

    // Counter
    wire [31:0] count, count_a1 ;
    assign count_a1[31:0] = count[31:0] + 32'd1 ;
//    Mflipflop_srh_32 cc_reg(count[31:0], count[31:0]+1,
//		    ss_scan_mode, /*scan-in*/, hold_count,
//		    rcc_rst_even_l, rcc_clk) ;
    Mflipflop_rh_32 cc_reg(count[31:0], count[31:0]+1,
		    hold_count,
		    rcc_rst_even_l, rcc_clk) ;


    // Active when the next enabled clock will wrap the count around to 0.
    wire terminal_count_l = ~(count[31:0]==-32'd1) ;

    // Set on counter overflow, read by scan 
//    Mflipflop_srh ovfl_ff(overflow, (overflow | ~terminal_count_l),
//		    ss_scan_mode, /*scan-in*/, hold_count,
//		    rcc_rst_even_l, rcc_clk) ;
    Mflipflop_rh ovfl_ff(overflow, (overflow | ~terminal_count_l),
		    hold_count,
		    rcc_rst_even_l, rcc_clk) ;


endmodule