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/******************************************************************************/
// *************************************************************************
// @(#)rl_dpc_cont.v 1.31 10/15/93
// rl_dpc_cont.v
//
// Description:
// This is the bulk of the control logic in the DPC block, governing the
// operation of the major components in there. It controls:
// - When the data input & output registers should clock the data.
// - When and which of the tristate buffers should drive the bd_mdata
// bus.
// - How the 64 bit mux should arrange the data to be written to memory.
// This will select the appropriate bytes of a read data to be
// replaced by the write data presented for a 8/16bit write, when a
// read-mod-write cycle is being performed.
// In tha case of 64/32bit data writes, byte replacement is not used.
// During reads, the data read from memory is allowed to pass through
// the mux, to the parity block in order to check it against the
// received parity bit.
// - When to drive the pads as outputs.
// - When the parity check results is valid and if an error is detected,
// allow it to be presented on dp_perr.
//
// Dependencies:
// defines.v mem_cells.vpp
//
//
//
// *************************************************************************
![[Up: rl_dpc_logic ctrl]](v2html-up.gif)
module rl_dpc_cont
(out_hld , in_hld , dp_buf0_en_dly , par_en , dp_ben,
mux_sel ,
mc_dpct, mc_curr_st, mc_odat_hld,
ss_scan_mode, ss_clock,
quad_sel,
mm_issue_req, mm_mreq, mm_2nd_wd, mc_mbsy,
quad_sel_dwd, gr_hld, gr_out_sel, mm_fb_req,
mm_parity_en, pcic_afxm_db_oen,
am_gnt_l, valid_l, am_read,
sync_t0);
output [3:0] out_hld; // The clock-disable of OUT0 and OUT1 registers.
output [1:0] in_hld; // The clock-disable of IN0 and IN1 registers.
output [1:0] par_en; // Gate the result of parity check on par_err.
output [3:0] mux_sel; // Byte selects for 64bit mux (repeat every 32).
// output dp_buf0_en; // The enable to MMU for DPC tri-buff 0.
output dp_buf0_en_dly; // The enable to MMU for DPC tri-buff 0, 1 cycle late.
// output in_dly1; // Use as "par_hld" in module "rl_par_genchk32".
// output in_dly2; // Use as "sel_src" in module "rl_par_genchk32".
output dp_ben; // External Tri-enable control to IO-pads.
output quad_sel;
output quad_sel_dwd;
output [1:0] gr_hld; // bit 0 hold for gr0,1; bit 1 hold for gr2,3.
output gr_out_sel; //select dram or graphics data
// input mdata_en0;
// input mdata_en1 ;
input ss_scan_mode;
input ss_clock; // Free running system clock.
input [8:0] mc_curr_st; // MCB current state.
// input mc_cyc_reg_4; // MCB cycle type in progress.
input mc_odat_hld; // MCB in Idle when 0.
input [5:0] mc_dpct; // DPC control bus from MCB. See table below:
input mm_issue_req; //
input [3:0] mm_mreq; //
input mm_2nd_wd;
input mc_mbsy;
input mm_fb_req;
input mm_parity_en;
input pcic_afxm_db_oen; //IIep 2.0: dma_rd par c
input am_gnt_l; // IIe signal : DRAM data bus is grant to Falcon
//2.0: add valid_l and am_read inputs for dma read par chk
input valid_l;
input am_read;
input sync_t0; //IIep 2.0: for dma read par chk
//
// mc_dpct |
// bit(s) | Description
//----------+-----------------------------------------------------
// 1:0 | Latched PA[1:0] from MCB. Used in R-M-W cycles
// | for mux sel and determine the bytes..
// 2 | Latched PA[2]. Select high or low word to gate first.
// 4:3 | Op size (00=byte, 01=hword, 1x=word/dword)
// 5 | Sel Rd (1) or Wr (0) op.
wire in_dly1;
wire Gnd = 1'b0;
wire ct2_reg_hld, ct2_din, dpct2;
/* Generate delayed version of "mc_odat_hld".*/
/*====================================================================*/
// remove hold pin
// GReg1 ffh_dathld(dat_hld_dly, mc_odat_hld, ss_clock, Gnd);
// GReg1 ffh_dathld2(dat_hld_dly2, dat_hld_dly, ss_clock, Gnd);
Mflipflop_noop_1 ffh_dathld(dat_hld_dly, mc_odat_hld, ss_clock);
Mflipflop_noop_1 ffh_dathld2(dat_hld_dly2, dat_hld_dly, ss_clock);
// GReg1 ffh_dathld3(dat_hld_dly3, dat_hld_dly2, ss_clock, Gnd);
/* mc_dpct[2] is used to control the sequence of the words placed on
* bd_mdata after an lword read. (This is mm_pa[02]).
* A 2 stage delayed version of it is needed, to hold it valid
* after mcb return 'not busy' to mmu.
* In the case of multi-read requests from mmu, we sequence the data,
* depending on mm_pa[02], only for first 64bits. For remaining cycles
* the sequence must be as if mm_pa[02]=0. Hence the folowing logic. */
/*====================================================================*/
/* Allow Dpct2 register state change during a multi-rd cycle or at its
end (also end of any Rd), or during IDLE (for initialization).
------------------------------------------------------------------*/
assign ct2_reg_hld = ( ((mc_curr_st==`L3_RDM01) ||
(mc_curr_st==`L3_RDP02A)||
(mc_curr_st==`L3_RDP02B)||
(mc_curr_st==`L3_GRDT5)||
(mc_curr_st==`L3_GRDTN)||
(mc_curr_st==`L3_GRDTX)||
(mc_curr_st==`L1_IDLE) ) ? 1'b0 : 1'b1 );
/* Dpct2 register will be set during this state in a multi-rd cycle
(reg hold is negated, see above) and will remain 0 any other time!
--------------------------------------------------------------------*/
assign ct2_din = ( ((mc_curr_st==`L3_RDM01)|(mc_curr_st==`L3_GRDT5))
? 1'b0 : 1'b1);
GReg1 ffh_dpct2 ( ct2_out, ct2_din, ss_clock, ct2_reg_hld);
/* The dpct2 will be forced to 0 when ct2_out is 0, else it'll reflect
mc_dpct[2] value. This will force dpct2 to be reset to 0, after 1st
lword of a multi-rd, correcting the order of the remaining lwords
per SSPARC hw-spec.
--------------------------------------------------------------------*/
assign dpct2 = ct2_out & mc_dpct[2] ;
// WAS this before, remove 1 register for synopsys.
//
// GReg2 ffh_dpct2dly( {dpct2_dly2,dpct2_dly1}, {dpct2_dly1, dpct2},
// ss_clock, Gnd);
// remove hold pin
// GReg1 ffh_dpct1dly ( dpct2_dly1, dpct2, ss_clock, Gnd);
Mflipflop_noop_1 ffh_dpct1dly ( dpct2_dly1, dpct2, ss_clock);
// This is replaced by the above, to force the value of "dpct2_dly2" to 0
// after first 64-bit Rd in multi-rd cycles.
// /* Generate delayed version of mc_dpct[2], holding it valid for 2 more
// * clocks after it is released (released when mbsy->0, in Mcb_SM. */
// /*====================================================================*/
// GReg2 ffh_dpct2dly(
// {dpct2_dly2,dpct2_dly1}, {dpct2_dly1, mc_dpct[2]},
// ss_clock, Gnd);
/* Hold the contents of out-registers (to memory) as a new MMU cycle
* starts. This is keyed from 'mc_odat_hld' signal.
* 'out_hld' is normally high (hold), it goes low (load)
* as 'mc_odat_hld' goes low when MCB is in IDLE.
* Holding them at start of every MMU cycle is ok, since only MMU
* does writes, and if the cycle turned out not to be a write or rd_m_wr,
* we will never use it anyway.
* Also, out_hld[0] will be negated when mm_data_view=0, to allow data
* to freely flow from internal data-bus to the pins. out_hld[1] doesn't
* need it since there is only 32 bits to see.*/
// The third write word is always load in out2 reg. which will be the hi-order
// bits 63:32(low word) of the double word. The next word will be loaded in
// out3 reg. which is the lo-order bit(hi-word). The hold signals will be one
// cycle later each case.
/*====================================================================*/
/* old
assign quad_sel = (mc_curr_st==`L3_WRP04 );
assign out_hld[1] = (( mc_odat_hld & (mc_dpct[2]==1'b0))|
( ~mm_wbstben1 & mm_wbstben0)|
( dat_hld_dly & (mc_dpct[2]==1'b1)))&
~quad_sel ;
assign out_hld[0] = (( mc_odat_hld & (mc_dpct[2]==1'b1))|
( dat_hld_dly & (mc_dpct[2]==1'b0)))&
~quad_sel ;
assign out_hld[2] = dat_hld_dly2;
assign out_hld[3] = dat_hld_dly3;
*/
wire prev_wd_sel;
// add G_REQ to hold reg. for graphics d_write
// assign prev_wd_sel = (`MM_REQ)&&(`MM_WR8|`MM_WR16);
assign prev_wd_sel = ((`G_REQ)|(`MM_REQ))&&(`MM_WR8|`MM_WR16);
// This is for rl_memif_minor
//
assign quad_sel_dwd = prev_wd_sel | quad_sel;
// end rl_memif_minor
// graphics quad_sel at wrt3 also.
// assign quad_sel = (mc_curr_st==`L3_WRP04 );
assign quad_sel = (mc_curr_st==`L3_WRP04 ) || (mc_curr_st==`L3_GWRT3 ) ;
// (mc_curr_st==L3_GWRTC) ;
// changed for gypsy to get rid of output spike.
//
// assign out_hld[1] = (( mc_odat_hld & (mc_dpct[2]==1'b0))&
// ~quad_sel) | mm_2nd_wd ;
assign out_hld[1] = (( mc_odat_hld )&
~quad_sel) | mm_2nd_wd ;
// to add pio, asi path; hold out1 if mm_2nd_wd is asserted
// assign out_hld[1] = (( mc_odat_hld & (mc_dpct[2]==1'b0))|
// ((`MM_REQ)&&(`MM_WR8|`MM_WR16))) &
// ~quad_sel ;
assign out_hld[0] = ( mc_odat_hld )&
~quad_sel ;
// use out_hld[2] to store the store 1st store double data.
// assign out_hld[2] = dat_hld_dly;
assign out_hld[2] = dat_hld_dly & mc_mbsy;
assign out_hld[3] = dat_hld_dly2;
/* Always hold the contents of in-registers (from memory) except at
* the end of a read from memory. This must happen as CASes are negated
* at the end of a read MMU rd multi_rd or rd_m_wr) cycle. 'in_hld'
* goes low for 1 clock.*/
/*====================================================================*/
assign in_hld[0] = ~( (mc_curr_st==`L3_RDP02A)|(mc_curr_st==`L3_RDP02B)|
(mc_curr_st==`L3_RDM01 )|(mc_curr_st==`L3_RDM04 )|
(mc_curr_st==`L3_RDM07 )|(mc_curr_st==`L3_RMWP01)|
(mc_curr_st==`L3_GRDT5 )|(mc_curr_st==`L3_GRDTB )|
(mc_curr_st==`L3_GRDTH )|(mc_curr_st==`L3_GRDTN )|
//2.0: add dma read state
//(mc_curr_st==`L3_GRDTX )
(mc_curr_st==`L3_GRDTX )|(~valid_l & am_read& ~pcic_afxm_db_oen)
);
assign in_hld[1] = in_hld[0] ;
wire in_hld_par;
assign in_hld_par = ~( (mc_curr_st==`L3_RDP02A)|(mc_curr_st==`L3_RDP02B)|
(mc_curr_st==`L3_RDM01 )|(mc_curr_st==`L3_RDM04 )|
(mc_curr_st==`L3_RDM07 )|(mc_curr_st==`L3_RMWP01)
//2.0: add dma read state
| (~valid_l & am_read & ~pcic_afxm_db_oen)
);
/* Generate two delayed version of 'in_hld' (1 and 2 clocks delay).
* These will signal when data is expected on internal D-bus. Used for
* controlling the buffers.*/
/*====================================================================*/
/*
GReg2 ffh_in_dly(
{in_dly2, in_dly1}, {in_dly1, in_hld[0]}, ss_clock, Gnd);
*/
// remove hold pin
// GReg1 ffh_in_dly(in_dly1, in_hld[0], ss_clock, Gnd);
//
// GReg1 ffh_in_par_dly(in_par_dly, in_hld_par, ss_clock, Gnd);
Mflipflop_noop_1 ffh_in_dly(in_dly1, in_hld[0], ss_clock);
//2.0: hold in_par_dly to sync with (~sync_t0 & ~am_gnt_l)
//Mflipflop_noop_1 ffh_in_par_dly(in_par_dly, in_hld_par, ss_clock);
//Mflipflop_1 ffh_in_par_dly(in_par_dly, in_hld_par, ss_clock, ~sync_t0);
Mflipflop_1 ffh_in_par_dly(in_par_dly, in_hld_par, ss_clock, ~sync_t0 & ~am_gnt_l);
/* New signal "dp_buf0_en" to MMU, this changes one clock_edge before
* the tri-state buffs for DPC should be selected. MMU sould re-clock
* this in a FF and use the output as "dpc_buf0_en" and "~dpc_buf1_en"
* going to the DPC tri-states.*/
/*====================================================================*/
wire dp_buf0_en;
// wire dp_buf0_en_dly;
// address bit 2 was swapped. bit 2 = 0 means bit 63:32
// assign dp_buf0_en = ~( ((dpct2==1'b0)&(~in_hld[0])) |
// ((dpct2_dly1==1'b1)&(~in_dly1)) );
// GReg1 dp_buf0_en_reg(dp_buf0_en_dly, dp_buf0_en, ss_clock, Gnd);
assign dp_buf0_en = ( ((dpct2==1'b1)&(~in_hld[0])) |
((dpct2_dly1==1'b0)&(~in_dly1)) );
// remove hold
// GReg1 dp_buf0_en_reg(dp_buf0_en_dly, dp_buf0_en, ss_clock, Gnd);
Mflipflop_noop_1 dp_buf0_en_reg(dp_buf0_en_dly, dp_buf0_en, ss_clock);
/* The parity error may be set only when 'par_en' is '1'. This allows
* to wait for a valid parity to be present before we let the result out.
* Parity for each word is gated with the word on the internal bd_mdata
* bus.*/
/*====================================================================*/
// assign par_en[1] = ( ((dpct2_dly1==1'b0)&(~in_dly1)) |
// ((dpct2_dly2==1'b1)&(~in_dly2)) );
//
// assign par_en[0] = ( ((dpct2_dly1==1'b1)&(~in_dly1)) |
// ((dpct2_dly2==1'b0)&(~in_dly2)) );
// used mdata_en1 before
// assign par_en[1] = (mdata_en1==1'b1) & (~in_dly1 | ~in_dly2);
// assign par_en[0] = (mdata_en0==1'b1) & (~in_dly1 | ~in_dly2);
//
// Use reg. version of parity_enable from MMU.
//
// remove hold
// GReg1 dp_mm_parity_en(mm_parity_en_reg, mm_parity_en, ss_clock, Gnd);
Mflipflop_noop_1 dp_mm_parity_en(mm_parity_en_reg, mm_parity_en, ss_clock);
/*
assign par_en[1] = ~in_dly1 & mm_parity_en_reg ;
assign par_en[0] = ~in_dly1 & mm_parity_en_reg ;
*/
assign par_en[1] = ~in_par_dly & mm_parity_en_reg ;
assign par_en[0] = ~in_par_dly & mm_parity_en_reg ;
// The following logic is restructured again to eliminate the parity
// and data out path. rid is only gated on RMW, else rod is gated.
wire mux_sel_rmw_3;
wire mux_sel_rmw_2;
wire mux_sel_rmw_1;
wire mux_sel_rmw_0;
//def. of mux_sel_rmw_* is to changed to select rid.
assign mux_sel_rmw_3 = ((
(`WR_RMW & `HWORD & ~(`PA1==1'b0))|
(`WR_RMW & `BYTE & ~((`PA1==1'b0) & (`PA0==1'b0)))
) ? 1'b1 : 1'b0);
assign mux_sel_rmw_2 = ((
(`WR_RMW & `HWORD & ~(`PA1==1'b0))|
(`WR_RMW & `BYTE & ~((`PA1==1'b0) & (`PA0==1'b1)))
) ? 1'b1 : 1'b0);
assign mux_sel_rmw_1 = ((
(`WR_RMW & `HWORD & ~(`PA1==1'b1))|
(`WR_RMW & `BYTE & ~((`PA1==1'b1) & (`PA0==1'b0)))
) ? 1'b1 : 1'b0);
assign mux_sel_rmw_0 = ((
(`WR_RMW & `HWORD & ~(`PA1==1'b1))|
(`WR_RMW & `BYTE & ~((`PA1==1'b1) & (`PA0==1'b1)))
) ? 1'b1 : 1'b0);
// remove hold
// GReg1 ffh_mux_sel_reg_3(mux_sel_reg_3, mux_sel_rmw_3, ss_clock, Gnd);
// GReg1 ffh_mux_sel_reg_2(mux_sel_reg_2, mux_sel_rmw_2, ss_clock, Gnd);
// GReg1 ffh_mux_sel_reg_1(mux_sel_reg_1, mux_sel_rmw_1, ss_clock, Gnd);
// GReg1 ffh_mux_sel_reg_0(mux_sel_reg_0, mux_sel_rmw_0, ss_clock, Gnd);
Mflipflop_noop_1 ffh_mux_sel_reg_3(mux_sel_reg_3, mux_sel_rmw_3, ss_clock);
Mflipflop_noop_1 ffh_mux_sel_reg_2(mux_sel_reg_2, mux_sel_rmw_2, ss_clock);
Mflipflop_noop_1 ffh_mux_sel_reg_1(mux_sel_reg_1, mux_sel_rmw_1, ss_clock);
Mflipflop_noop_1 ffh_mux_sel_reg_0(mux_sel_reg_0, mux_sel_rmw_0, ss_clock);
// & WR could be taken away since it only selected in0, in1 @ idle
// defaulted to out0, out1
assign mux_sel[3] = ( (mux_sel_reg_3
) ? 1'b0 : 1'b1 );
assign mux_sel[2] = ( (mux_sel_reg_2
) ? 1'b0 : 1'b1 );
assign mux_sel[1] = ( (mux_sel_reg_1
) ? 1'b0 : 1'b1 );
assign mux_sel[0] = ( (mux_sel_reg_0
) ? 1'b0 : 1'b1 );
/* Mux selects for input to Parity check/gen and to do RmW cycles.
* Mux select is set so that when a mux_sel[x] is '1', the input
* connected to 'rod' is enabled, otherwise 'rid' is gated. */
/*====================================================================*/
// This logic is changed to remove parity long path.
// GReg1 ffh_dathld(dat_hld_dly, mc_odat_hld, ss_clock, Gnd);
/*
wire mux_sel_rmw_3;
wire mux_sel_rmw_2;
wire mux_sel_rmw_1;
wire mux_sel_rmw_0;
assign mux_sel_rmw_3 = ((
(`WR_RMW & `HWORD & (`PA1==1'b0))|
(`WR_RMW & `BYTE & (`PA1==1'b0) & (`PA0==1'b0))
) ? 1'b1 : 1'b0);
assign mux_sel_rmw_2 = ((
(`WR_RMW & `HWORD & (`PA1==1'b0))|
(`WR_RMW & `BYTE & (`PA1==1'b0) & (`PA0==1'b1))
) ? 1'b1 : 1'b0);
assign mux_sel_rmw_1 = ((
(`WR_RMW & `HWORD & (`PA1==1'b1))|
(`WR_RMW & `BYTE & (`PA1==1'b1) & (`PA0==1'b0))
) ? 1'b1 : 1'b0);
assign mux_sel_rmw_0 = ((
(`WR_RMW & `HWORD & (`PA1==1'b1))|
(`WR_RMW & `BYTE & (`PA1==1'b1) & (`PA0==1'b1))
) ? 1'b1 : 1'b0);
GReg1 ffh_mux_sel_reg_3(mux_sel_reg_3, mux_sel_rmw_3, ss_clock, Gnd);
GReg1 ffh_mux_sel_reg_2(mux_sel_reg_2, mux_sel_rmw_2, ss_clock, Gnd);
GReg1 ffh_mux_sel_reg_1(mux_sel_reg_1, mux_sel_rmw_1, ss_clock, Gnd);
GReg1 ffh_mux_sel_reg_0(mux_sel_reg_0, mux_sel_rmw_0, ss_clock, Gnd);
assign mux_sel[3] = ( ((`WR_RMWD_DWRD|mux_sel_reg_3) & `WR
) ? 1'b1 : 1'b0 );
assign mux_sel[2] = ( ((`WR_RMWD_DWRD|mux_sel_reg_2) & `WR
) ? 1'b1 : 1'b0 );
assign mux_sel[1] = ( ((`WR_RMWD_DWRD|mux_sel_reg_1) & `WR
) ? 1'b1 : 1'b0 );
assign mux_sel[0] = ( ((`WR_RMWD_DWRD|mux_sel_reg_0) & `WR
) ? 1'b1 : 1'b0 );
*/
/*
assign mux_sel[3] = ( ( (`WR_RMW & `WRD_DWRD)|
(`WR_RMW & `HWORD & (`PA1==1'b0))|
(`WR_RMW & `BYTE & (`PA1==1'b0) & (`PA0==1'b0))
) ? 1'b1 : 1'b0 );
assign mux_sel[2] = ( ( (`WR_RMW & `WRD_DWRD)|
(`WR_RMW & `HWORD & (`PA1==1'b0))|
(`WR_RMW & `BYTE & (`PA1==1'b0) & (`PA0==1'b1))
) ? 1'b1 : 1'b0 );
assign mux_sel[1] = ( ( (`WR_RMW & `WRD_DWRD)|
(`WR_RMW & `HWORD & (`PA1==1'b1))|
(`WR_RMW & `BYTE & (`PA1==1'b1) & (`PA0==1'b0))
) ? 1'b1 : 1'b0 );
assign mux_sel[0] = ( ( (`WR_RMW & `WRD_DWRD)|
(`WR_RMW & `HWORD & (`PA1==1'b1))|
(`WR_RMW & `BYTE & (`PA1==1'b1) & (`PA0==1'b1))
) ? 1'b1 : 1'b0 );
*/
/* dp_ben controls the I/O pin 3-state buffers for output. It is
* asserted when a write is about to happen (mc_dpct[5]=0) or when
* in diag mode (mm_data_view=1) and current cycle is CBR or NONE.
* When asserted to 1, the 3-state buffer will turn on. */
/*====================================================================*/
// assign dp_ben = ~ss_scan_mode &
// (~mc_dpct[5] | ((mm_data_view)&(mc_cyc_reg_4==1'b1)));
wire wrt1, wrt1_n, wrt1_2n, wrt1_3n, wrt1_4n, wrt1_5n ;
// wire wrtg, wrtg_n, wrtg_2n;
// wire wrth, wrth_n;
wire wrt7, wrt7_n, wrt7_2n;
wire afx_data_en_p, afx_data_en;
assign afx_data_en_p = wrt1_2n | wrt1_3n | wrt1_4n | (mc_curr_st==`L3_GWRT6) |
// (mc_curr_st==L3_GWRTF) |
(mc_curr_st==`L3_GWRT7) | wrt7_n ;
// remove hold
// GReg1 ffh_afx_data_en(afx_data_en, afx_data_en_p, ss_clock, Gnd);
Mflipflop_noop_1 ffh_afx_data_en(afx_data_en, afx_data_en_p, ss_clock);
wire afx_data_dis_p, afx_data_dis;
assign afx_data_dis_p = ~wrt1 & ~wrt1_n;
// remove hold
// GReg1 ffh_afx_data_dis(afx_data_dis, afx_data_dis_p, ss_clock, Gnd);
Mflipflop_noop_1 ffh_afx_data_dis(afx_data_dis, afx_data_dis_p, ss_clock);
// IIe note : am_gnt_l is added to the dp_ben equation, so that the mem_oe of m_data's
// tri-state driver is disabled during a Falcon DMA write.
assign dp_ben = ~ss_scan_mode & am_gnt_l &
((~mc_dpct[5] &
~(mc_curr_st==`L3_WRP01) & ~wrt1 & afx_data_dis) |
afx_data_en);
// reduce path delay.
//
// assign dp_ben = ~ss_scan_mode &
// ((~mc_dpct[5] &
// ~(mc_curr_st==`L3_WRP01) & ~wrt1 & ~wrt1_n & ~wrt1_2n) |
// (wrt1_3n | wrt1_4n | wrt1_5n | wrt8 | wrt8_n |
// (mc_curr_st==`L3_GWRT7) | wrtg | wrtg_n | wrtg_2n ));
// graphics control for dp
assign wrt1 = (mc_curr_st==`L3_GWRT1);
// remove hold
// GReg1 ffh_wrt1_n(wrt1_n, wrt1, ss_clock, Gnd);
// GReg1 ffh_wrt1_2n(wrt1_2n, wrt1_n, ss_clock, Gnd);
// GReg1 ffh_wrt1_3n(wrt1_3n, wrt1_2n, ss_clock, Gnd);
// GReg1 ffh_wrt1_4n(wrt1_4n, wrt1_3n, ss_clock, Gnd);
// GReg1 ffh_wrt1_5n(wrt1_5n, wrt1_4n, ss_clock, Gnd);
Mflipflop_noop_1 ffh_wrt1_n(wrt1_n, wrt1, ss_clock);
Mflipflop_noop_1 ffh_wrt1_2n(wrt1_2n, wrt1_n, ss_clock);
Mflipflop_noop_1 ffh_wrt1_3n(wrt1_3n, wrt1_2n, ss_clock);
Mflipflop_noop_1 ffh_wrt1_4n(wrt1_4n, wrt1_3n, ss_clock);
Mflipflop_noop_1 ffh_wrt1_5n(wrt1_5n, wrt1_4n, ss_clock);
assign wrt7 = (mc_curr_st==`L3_GWRT7);
// remove hold
// GReg1 ffh_wrt7_n(wrt7_n, wrt7, ss_clock, Gnd);
// GReg1 ffh_wrt7_2n(wrt7_2n, wrt7_n, ss_clock, Gnd);
Mflipflop_noop_1 ffh_wrt7_n(wrt7_n, wrt7, ss_clock);
Mflipflop_noop_1 ffh_wrt7_2n(wrt7_2n, wrt7_n, ss_clock);
// assign wrt8 = wrt7_n;
// GReg1 ffh_wrt8_n(wrt8_n, wrt8, ss_clock, Gnd);
// assign wrtg = (mc_curr_st==L3_GWRTG);
// assign wrth = (mc_curr_st==L3_GWRTH);
// GReg1 ffh_wrth_n(wrth_n, wrth, ss_clock, Gnd);
// GReg1 ffh_wrtg_n(wrtg_n, wrtg, ss_clock, Gnd);
// GReg1 ffh_wrtg_2n(wrtg_2n, wrtg_n, ss_clock, Gnd);
assign gr_hld[0] = (mc_curr_st==`L3_GWRT5) | wrt1_n;
assign gr_hld[1] = (mc_curr_st==`L3_GWRT7) | wrt7_n |
wrt1_3n | wrt1_4n;
wire gr_out_sel_en;
assign gr_out_sel_en = wrt1_3n | wrt1_4n | wrt1_5n | wrt7_2n | wrt7_n;
assign gr_out_sel = (mc_curr_st==`L3_GWRT7) | gr_out_sel_en ;
/*
assign gr_out_sel = (mc_curr_st==`L3_GWRT7) | (mc_curr_st==`L3_GWRT8) |
wrt1_3n | wrt1_4n | wrt1_5n | wrt8_n;
*/
endmodule
| This page: |
Created: | Thu Aug 19 12:01:44 1999 |
| From: |
../../../sparc_v8/ssparc/memif/rtl/rl_dpc_cont.v
|