end
            else if ( dec_ct_ras == 1'b1 ) begin  /* count up.*/
                        f_decr_ras    = ras_dec - 3'b001; // Modulo-2 counter.
                end 
        end
    endfunction
//remove hold
//    GReg2   ffh_col_inc_ras (ras_dec[1:0], incr_w_ras[1:0], ss_clock, Gnd );
    Mflipflop_noop_3   ffh_col_inc_ras (ras_dec[2:0], incr_w_ras[2:0], ss_clock );
    //-------------------------------------------------------------
    assign  incr_w_ras = f_decr_ras(sp_sel,sp_sel_1,sp_sel_2,ras_dec,ld_ct_ras,dec_ct_ras,cyc_reg);
// end RAS04 counter

// WRP05, WRP02  counter specific.
    wire       [1:0] incr_w_wr5;
        wire    ld_ct_wr5, dec_ct_wr5;
        assign dec_ct_wr5 = ((curr_st==`L3_WRP02) || (curr_st==`L3_WRP05));
        assign ld_ct_wr5 = ~dec_ct_wr5;
        
    //------------- incr function --------------------------------
    //  Is a 1 bit loadable-decrementor used for decrementing the
    //  column address in block type accesses (I$, D$, SBus).
    //-------------------------------------------------------------
    function  	[1:0]   f_decr_wr5;
        input           sp_sel, sp_sel_1, sp_sel_2;
        input 	[1:0]   wr5_dec;
        input           ld_ct_wr5, dec_ct_wr5;
 
        begin
            f_decr_wr5 = wr5_dec;
            if ( ld_ct_wr5 == 1'b1 ) begin  /* load the input. */
 
// add 1 cycle @ 85 MHz for timing on IO cell and board may be too big.
                case (({sp_sel_2, sp_sel_1,sp_sel}))      //PARALLEL_CASE
                        3'b000:  f_decr_wr5 = 2'b00;
                        3'b001:  f_decr_wr5 = 2'b01;
                        3'b010:  f_decr_wr5 = 2'b01;
                        3'b011:  f_decr_wr5 = 2'b01;
                        3'b100:  f_decr_wr5 = 2'b10;
                        3'b101:  f_decr_wr5 = 2'b10;
                        3'b110:  f_decr_wr5 = 2'b10;
                        3'b111:  f_decr_wr5 = 2'b10;
                        endcase
                end
            else if ( dec_ct_wr5 == 1'b1 ) begin  /* count up.*/
                        f_decr_wr5    = wr5_dec - 2'b01; // Modulo-2 counter.
                end 
        end
    endfunction
//remove hold
//    GReg1   ffh_col_inc_wr5 (wr5_dec, incr_w_wr5, ss_clock, Gnd );
    Mflipflop_noop_2   ffh_col_inc_wr5 (wr5_dec[1:0], incr_w_wr5[1:0], ss_clock );
    //-------------------------------------------------------------
    assign  incr_w_wr5 = f_decr_wr5(sp_sel,sp_sel_1,sp_sel_2,wr5_dec,ld_ct_wr5,dec_ct_wr5);
// end WRP05 counter

// WRP06, WRP02W  counter specific.
    wire [1:0]      incr_w_wr6;
        wire    ld_ct_wr6, dec_ct_wr6;
        assign dec_ct_wr6 = ((curr_st==`L3_WRP02W) || (curr_st==`L3_WRP06));
        assign ld_ct_wr6 = ~dec_ct_wr6;
        
    //------------- incr function --------------------------------
    //  Is a 2 bit loadable-decrementor used for decrementing the
    //  column address in block type accesses (I$, D$, SBus).
    //-------------------------------------------------------------
    function    [1:0]  f_decr_wr6;
        input           sp_sel, sp_sel_1, sp_sel_2;
        input   [1:0]     wr6_dec;
        input           ld_ct_wr6, dec_ct_wr6;
 
        begin
            f_decr_wr6 = wr6_dec;
            if ( ld_ct_wr6 == 1'b1 ) begin  /* load the input. */
 
                case (({sp_sel_2,sp_sel_1,sp_sel}))      //PARALLEL_CASE
                        3'b000:  f_decr_wr6 = 2'b00;
                        3'b001:  f_decr_wr6 = 2'b01;
                        3'b010:  f_decr_wr6 = 2'b01;
                        3'b011:  f_decr_wr6 = 2'b01;
                        3'b100:  f_decr_wr6 = 2'b10;
                        3'b101:  f_decr_wr6 = 2'b10;
                        3'b110:  f_decr_wr6 = 2'b11;
                        3'b111:  f_decr_wr6 = 2'b11;
                        endcase
                end
            else if ( dec_ct_wr6 == 1'b1 ) begin  /* count up.*/
                        f_decr_wr6    = wr6_dec - 2'b01 ; // Modulo-2 counter.
                end 
        end
    endfunction
//remove hold
//    GReg1   ffh_col_inc_wr6 (wr6_dec, incr_w_wr6, ss_clock, Gnd );
    Mflipflop_noop_2   ffh_col_inc_wr6 (wr6_dec[1:0], incr_w_wr6[1:0], ss_clock );
    //-------------------------------------------------------------
    assign  incr_w_wr6 = f_decr_wr6(sp_sel,sp_sel_1,sp_sel_2,wr6_dec,ld_ct_wr6,dec_ct_wr6);
// end WRP06 counter

// r175_dec   counter specific.
    wire       incr_w_175;
        wire    ld_ct_175, dec_ct_175;
        assign dec_ct_175 = (curr_st==`L3_RDP01S);
        assign ld_ct_175 = ~dec_ct_175;

    //------------- incr function --------------------------------
    //  Is a 2 bit loadable-decrementor used for decrementing the
    //  column address in block type accesses (I$, D$, SBus).
    //-------------------------------------------------------------
    function    f_decr_175;
        input           sp_sel, sp_sel_1, sp_sel_2;
        input        r175_dec;
        input           ld_ct_175, dec_ct_175;

        begin
            f_decr_175 = r175_dec;
            if ( ld_ct_175 == 1'b1 ) begin  /* load the input. */

                case (({sp_sel_2,sp_sel_1,sp_sel}))      //PARALLEL_CASE
                        3'b000:  f_decr_175 = 1'b0;
                        3'b001:  f_decr_175 = 1'b0;
                        3'b010:  f_decr_175 = 1'b0;
                        3'b011:  f_decr_175 = 1'b0;
                        3'b100:  f_decr_175 = 1'b0;
                        3'b101:  f_decr_175 = 1'b0;
                        3'b110:  f_decr_175 = 1'b1;
                        3'b111:  f_decr_175 = 1'b1;
                        endcase
                end  
            else if ( dec_ct_175 == 1'b1 ) begin  /* count up.*/
                        f_decr_175    = ~175 ; // Modulo-2 counter.
                end  
        end
    endfunction
//remove hold 
//    GReg1   ffh_col_inc_175 (r175_dec, incr_w_175, ss_clock, Gnd );
    Mflipflop_noop_1   ffh_col_inc_175 (r175_dec, incr_w_175, ss_clock );
    //-------------------------------------------------------------
    assign  incr_w_175 = f_decr_175(sp_sel,sp_sel_1,sp_sel_2,r175_dec,ld_ct_175,dec_ct_175);
// end r175_dec counter

// RDM02, RDM05, RDM08  counter specific.
    wire  [1:0]     incr_w_cas;
        wire    ld_ct_cas, dec_ct_cas;
        assign dec_ct_cas = ((curr_st==`L3_RDM02) || (curr_st==`L3_RDM05) ||
			     (curr_st==`L3_RDM08));
        assign ld_ct_cas = ~dec_ct_cas;
        
    //------------- incr function --------------------------------
    //  Is a 2 bit loadable-decrementor used for decrementing the
    //  column address in block type accesses (I$, D$, SBus).
    //-------------------------------------------------------------
    function   [1:0] f_decr_cas;
        input           sp_sel, sp_sel_1, sp_sel_2;
        input  [1:0]      cas_dec;
        input           ld_ct_cas, dec_ct_cas;
 
        begin
            f_decr_cas = cas_dec;
            if ( ld_ct_cas == 1'b1 ) begin  /* load the input. */
 
                case (({sp_sel_2,sp_sel_1,sp_sel}))      //PARALLEL_CASE
                        3'b000:  f_decr_cas = 2'b00;
                        3'b001:  f_decr_cas = 2'b00;
                        3'b010:  f_decr_cas = 2'b01;
                        3'b011:  f_decr_cas = 2'b01;
                        3'b100:  f_decr_cas = 2'b01;
                        3'b101:  f_decr_cas = 2'b01;
                        3'b110:  f_decr_cas = 2'b10;
                        3'b111:  f_decr_cas = 2'b10;
                        endcase
                end
            else if ( dec_ct_cas == 1'b1 ) begin  /* count up.*/
                        f_decr_cas    = cas_dec - 2'b01; // Modulo-2 counter.
                end 
        end
    endfunction
//remove hold
//    GReg1   ffh_col_inc_cas (cas_dec, incr_w_cas, ss_clock, Gnd );
    Mflipflop_noop_2   ffh_col_inc_cas (cas_dec[1:0], incr_w_cas[1:0], ss_clock );
    //-------------------------------------------------------------
    assign  incr_w_cas = f_decr_cas(sp_sel,sp_sel_1,sp_sel_2,cas_dec,ld_ct_cas,dec_ct_cas);
// end RDM02 counter

// WRP01 (loaded at RDP02B) counter specific.
    wire    [2:0]   incr_w_bus;
        wire    ld_ct_bus, dec_ct_bus;
	assign dec_ct_bus = !(bus_dec == 3'b000);
//        assign dec_ct_bus = (curr_st==`L3_RDP02B) ;
        assign ld_ct_bus = ((curr_st==`L3_RDP02B) || (curr_st==`L3_G_RDP02B)) | rst;
        
    //------------- incr function --------------------------------
    //  Is a 3 bit loadable-decrementor used for decrementing the
    //  column address in block type accesses (I$, D$, SBus).
    //-------------------------------------------------------------
    function [2:0] f_decr_bus;
        input           sp_sel, sp_sel_1, sp_sel_2;
        input [2:0]     bus_dec;
        input           ld_ct_bus, dec_ct_bus;

        begin
            f_decr_bus = bus_dec;
            if ( ld_ct_bus == 1'b1 ) begin  /* load the input. */

                case (({sp_sel_2,sp_sel_1,sp_sel}))      //PARALLEL_CASE
                        3'b000:  f_decr_bus = 3'b010;
                        3'b001:  f_decr_bus = 3'b010;
                        3'b010:  f_decr_bus = 3'b011;
                        3'b011:  f_decr_bus = 3'b100;
                        3'b100:  f_decr_bus = 3'b101;
                        3'b101:  f_decr_bus = 3'b101;
                        3'b110:  f_decr_bus = 3'b110;
                        3'b111:  f_decr_bus = 3'b111;
                        endcase
 
                end
            else if ( dec_ct_bus == 1'b1 ) begin  /* count up.*/
                        f_decr_bus    = bus_dec - 3'b001; // Modulo-2 counter.
                end
        end
    endfunction
//remove hold
//    GReg3   ffh_col_inc_bus (bus_dec[2:0], incr_w_bus[2:0], ss_clock, Gnd );
    Mflipflop_noop_3   ffh_col_inc_bus (bus_dec[2:0], incr_w_bus[2:0], ss_clock );
    //-------------------------------------------------------------
    assign  incr_w_bus = f_decr_bus(sp_sel,sp_sel_1,sp_sel_2,bus_dec,ld_ct_bus,dec_ct_bus);
// end bus counter

// CBR02  counter specific.
// do not load at cbr01 to overwrite load at SRF01
    wire    [2:0]   incr_w_cbr;
        wire    ld_ct_cbr, dec_ct_cbr;
        assign dec_ct_cbr = ((curr_st==`L3_CBR02));
        assign ld_ct_cbr = ~dec_ct_cbr & !(curr_st==`L3_CBR01)  ;

    //------------- incr function --------------------------------
    //  Is a 3 bit loadable-decrementor used for decrementing the
    //  column address in block type accesses (I$, D$, SBus).
    //-------------------------------------------------------------
    function [2:0] f_decr_cbr;
        input           sp_sel, sp_sel_1, sp_sel_2;
        input [2:0]     cbr_dec;
        input           ld_ct_cbr, dec_ct_cbr;
        input [6:0]     cyc_reg;

        begin
            f_decr_cbr = cbr_dec;
            if ( ld_ct_cbr == 1'b1 ) begin  /* load the input. */

                case (({sp_sel_2,sp_sel_1,sp_sel}))      //PARALLEL_CASE
                        3'b000:  f_decr_cbr = 3'b000;
                        3'b001:  f_decr_cbr = 3'b000;
                        3'b010:  f_decr_cbr = 3'b000;
                        3'b011:  f_decr_cbr = 3'b010;
                        3'b100:  f_decr_cbr = 3'b100;
                        3'b101:  f_decr_cbr = 3'b100;
                        3'b110:  f_decr_cbr = 3'b101;
                        3'b111:  f_decr_cbr = 3'b110;
                        endcase
		if (curr_st==`L3_SRF01) begin
			f_decr_cbr = 3'b011;
			end

                end
            else if ( dec_ct_cbr == 1'b1 ) begin  /* count up.*/
                        f_decr_cbr    = cbr_dec - 3'b001; // Modulo-2 counter.
                end
        end
    endfunction
//remove hold
//    GReg2   ffh_col_inc_cbr (cbr_dec[1:0], incr_w_cbr[1:0], ss_clock, Gnd );
    Mflipflop_noop_3   ffh_col_inc_cbr (cbr_dec[2:0], incr_w_cbr[2:0], ss_clock );
    //-------------------------------------------------------------
    assign  incr_w_cbr = f_decr_cbr(sp_sel,sp_sel_1,sp_sel_2,cbr_dec,ld_ct_cbr,dec_ct_cbr,cyc_reg);
// end CBR02 counter

 
endmodule
                            


module afx_count(afx_limit, curr_st, sync_t0, rst, ss_clock);

	output		afx_limit;
	input	[8:0]	curr_st;
	input		sync_t0;
	input		rst;
	input		ss_clock;

	wire	[3:0]	afx_count;
	wire	[3:0]	curr_afx_count;
        wire            Gnd = 0 ;

	function [3:0]	inc_afx_cnt;
		input	[3:0]	afx_count;
		input	[8:0]	curr_st;
		input	     	sync_t0;
		input		rst;

		begin
			if (rst || (curr_st==`L1_IDLE) ||
				   (curr_st==`L2_CYCEND)) begin
				inc_afx_cnt = 4'b0000;
			end
			else if ((curr_st==`L3_G_RDP01) && sync_t0) begin
				inc_afx_cnt = afx_count + 4'b0001;
			end
			else begin
				inc_afx_cnt = afx_count;
			end
		end
	endfunction

	Mflipflop_noop_4   curr_count(afx_count[3:0], curr_afx_count[3:0], ss_clock);
	assign curr_afx_count = inc_afx_cnt(afx_count, curr_st, sync_t0, rst);
	//2.0: up curr_afx_count to 4'h8 
	//assign afx_limit = (curr_afx_count == 3'b100);
	assign afx_limit = (curr_afx_count == 4'h8);

endmodule