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/******************************************************************************/
// @(#)rl_mcb_sm.v 1.40 8/29/94
/*****************************************************************************
* rl_mcb_sm.v
*
* Description:
* The state-machine (sm) for the memory subsystem of the SingleSPARC.
* The "rl_mcb_sm" module contains the arbitration-sm (function L_St)
* which detects requests and performs the required memory cycles.
* The i/o from this module communicate with rl_mcb_lgc module, to
* generate RAS/CAS and other memory signals in correct sequence plus
* the logic to control the RAM address muxes (defined in rl_col_row_addr
* module) and the RAM to SingleSPARC internal data-bus datapath (defined
* in rl_dpc.v module).
*
* Refer to SingleSPARC Hardware Spec, section 2.7.3 for block diagram
* and more information.
*
*
* Dependencies:
* defines.v mem_cells.vpp rl_mcb_page.v
*
*
*
****************************************************************************/
/****************************************************************************
* IIe implemenation notes :
*
* New states to support a AFX master (Falcon) is added to the IIe. These
* new states repone to the AFX bus requests from Falcon and they are
* synchronized with g_clk. The synchronization is done using the sync_t2,
* which is the last phase of the gclk and generated for graphic accesses.
* In order to support these new states, the cycle type register (cyc_reg)
* and the cycle type signal (cyctype) have been increased from 6 bits
* to 7 bits. The state bits have also been changed to 9 bits, with the
* 9th bit representing these new states. The RAS/CAS timing for AFX
* master cycle will also be different from the CPU access. The following
* table illustrates the number of ref_clk required :
*
*
* first column = RefClk aligned
* second = Gclk aligned
*
* RefClk Cycles
*
* @70 MHz @85 MHz @100 MHz @125 MHz
*
* RAS (rd) 10 12 11 12 13 15 16 18
* RAS (wr) 9 9 9 9 11 12 14 15
* CAS (rd) 4 6 5 6 6 6 7 9
* CAS (wr) 3 3 3 3 4 6 5 6
*
*
*
* Rev. 0 : 8/17/95 - T. Ho
*
*
*****************************************************************************/
![[Up: rl_mcb_lgc mcb_sm]](v2html-up.gif)
module rl_mcb_sm
( curr_st_2,
next_st,
cyc_reg_2,
cyctype,
mbsy,
mstb_l,
is_page,
cas_dec,
wr5_dec,
rmw_dec,
bus_dec,
mm_issue_req,
mm_issue_req2,
mm_mreq,
mm_page,
rf_rreq_l,
rf_cbr,
ss_clock,
rst,
sp_sel,
sp_sel_1,
sp_sel_2,
precharge_p,
mm_rf_cntl_3,
mm_issue_req_early,
sync_t0,
sync_t1,
sync_t2,
fifo_full,
dead_cyc,
read_single,
mm_fb_req,
mm_fb_page,
mm_afx_req, // Falcon bus request.
mm_afx_read, // Falcon bus request for read.
mm_afx_gnt, // Falcon bus grant.
afx_rst_page_vld, // reset page valid registers
am_gnt_l, // Falcon bus grant (am_gnt_l to PAD).
ras_dis, // Ras disable, used to reset the page mode signal.
prom_wr_bsy,
mm_lst_cyc_afx,
pa25_flag);
//pa25_flag_delay);
output [8:0] curr_st_2; // From L_St storage flops.
output [8:0] next_st; // To L_St storage flops.
// IIe : changed to 9 bit with
// 9th bit defines Falcon states.
output [6:0] cyc_reg_2; // From cycle-type storage flops.
output [6:0] cyctype; // To cycle-type storage flops
// IIe : chnaged to 7 bit with
// the 7th bit defines Falcon
// cycles.
output mbsy; // Output to mmu indicating the memif is busy.
output mstb_l; // Output to mmu indicating the mdata strobe.
output is_page; // from IsPage instance of MCB_Page.
output [1:0] cas_dec; // counter for state RDM02 etc.
output [1:0] wr5_dec; // counter for state WRP05 etc.
output [2:0] rmw_dec; // counter for state RAS01X etc.
output [2:0] bus_dec;
output mm_afx_gnt; // Falcon bus grant.
output afx_rst_page_vld; // reset page valids in mmu
input mm_issue_req; // Valid-request from MMU.
input mm_issue_req2; // Valid-request from MMU.
input [3:0] mm_mreq;
input mm_page;
input rf_rreq_l; // refresh request
input rf_cbr;
input ss_clock; // The CPU system clock.
input rst; // Main RESET input.
input sp_sel; // Speed select pin 1.
input sp_sel_1; // Speed select pin 2.
input sp_sel_2; // Speed select pin 3.
input precharge_p;
input mm_rf_cntl_3; //
input mm_issue_req_early; //
input sync_t0; // 1st phase of the g_clk
input sync_t1; // 2nd phase of the g_clk
input sync_t2; // 3rd phase of the g_clk
input fifo_full; // a24 FIFO full based on p_reply - s_reply
input dead_cyc; //
input read_single; //
input mm_fb_req; //
input mm_fb_page; //
input mm_afx_req; // Falcon bus request.
input mm_afx_read; // Falcon bus request for read.
input am_gnt_l; // Falcon bus grant (am_gnt_l to PAD).
input ras_dis; //
input prom_wr_bsy; //
input mm_lst_cyc_afx; //
input pa25_flag;
//input pa25_flag_delay;
wire [8:0] curr_st; // mcb state bit, increased to 9 bit for IIe.
// failed banks.s ras's are disabled after a graphics operation, but
// the page registers were still valid. pntool bug 19
wire afx_rst_page_vld = (curr_st == `L3_G_RAS01) ? 1'b1 : 1'b0;
wire [6:0] cyc_reg; // bus cycle type, increased to 7 bit for IIe.
wire afx_limit; // Indicated total Falcon DMA cycle reaches the
// four cycle limit.
wire [2:0] read_dec;
wire [2:0] ras_dec;
wire [1:0] wr6_dec;
wire r175_dec;
wire [2:0] bus_dec;
wire [2:0] cbr_dec;
wire Gnd = 1'b0;
wire cyc_hld; // The hold for cycle-type flops.
wire cyc_hld_read; // The hold for cycle-type flops.
wire sync_t2; // The last phase of g_clk.
// ------------- l_st_fn function --------------------------------
// The logic to control the memory state machine.
// IIe note : The cyctype bit is increased by 1, and the state bits
// is increased by 1 bits. The function now returns 19 bits as defined by :
// l_st_fn [8:0] : New states for input to 'l_st' register.
// Bit 8 is the new bit for Falcon.
// l_st_fn [15:09] : Contains the type of the request, for history.
// Bit 15 is the new bit for Falcon.
// l_st_fn [16] : MBSY signal for the 'mm_busy' ff
// l_st_fn [17] : MSTB signal for the 'mm_mstb_l' ff.
// l_st_fn [18] : Falcon bus grant signal.
//
// the old definition is :
// l_st_fn [7:0] : New states for input to 'l_st' register.
// l_st_fn [13:08] : Contains the type of the request, for history.
// 1 more bit added for graphics instructions
// l_st_fn [14] : MBSY signal for the 'mm_busy' ff
// l_st_fn [15] : MSTB signal for the 'mm_mstb_l' ff.
// l_st_fn [old] : RST_COUNT signal for the '1st_uflow & 2nd_uflow' ff.
// l_st_fn [old] : load_max_rst signal for the 'rst of load_max' ff.
//
// The outputs l_st_fn[14:13] from this function are dealt with as wires
// even though verilog thinks of them as regs. Synpsys will consider
// them as o/p of combo logic and will treat them as wires. Since each
// o/p is toggled in one state and toggled back in the next, it will
// look like 1 clock long pulse in both verilog and sunopsys.
//-------------------------------------------------------------------
function [18:0] l_st_fn; // Level 1 state machine.
input [8:0] curr_st;
input [6:0] cyc_reg;
input mm_issue_req2; // Valid-request from MMU.
input [3:0] mm_mreq;
input is_page;
input rf_cbr;
input rf_rreq_l;
input rst; // Main RESET input.
input sp_sel; // {sp_sel_2, sp_sel_1, sp_sel)
input sp_sel_1; // 000 = 70MHz
input sp_sel_2; // 001 = 85MHz
// 010 = 100MHz
// 011 = 125MHz
// 100 = 150MHz
// 110 = 175MHz
// 111 = 200MHz
input precharge_p;
input mm_rf_cntl_3;
input mm_issue_req_early;
input [2:0] read_dec;
input [2:0] rmw_dec;
input [2:0] ras_dec;
input [1:0] wr5_dec;
input [1:0] wr6_dec;
input r175_dec;
input [1:0] cas_dec;
input [2:0] bus_dec;
input [2:0] cbr_dec;
// Graphic inputs
input sync_t0; // g_clk phase 1; ss_clk cycle 1
input sync_t1; // g_clk phase 2; ss_clk cycle 2
input sync_t2; // g_clk phase 3; ss_clk cycle 3
input fifo_full; //
input dead_cyc; //
input read_single; //
input mm_fb_req; //
input g_issue_req_p; //
input g_page_p; //
input mm_fb_page;
// Falcon inputs
input mm_afx_req; // Falcon bus request.
input mm_afx_read; // Falcon bus request for read.
input am_gnt_l; // Falcon bus grant (am_gnt_l to PAD).
reg [8:0] state ;
reg [6:0] cyctype;
reg mbsy;
reg mstb_l;
reg mm_afx_gnt;
// Level 1 (L1_) of the state machine always resets to RESET state (9'h000)
// wait 200us before going to WAIT state (9'h001), then proceeds to 8 CAS
// before RAS (CBR state 9'h002) refresh cycles.
//
begin
if ( rst == 1'b1) // The big RESET ! Power up or hardware reset.
begin
mbsy = 1; // Signal busy to MMU.
mstb_l = 1;
mm_afx_gnt = 0;
state = `L1_RESET; // Set to L1_RESET state.
cyctype = `NONE;
end
else
begin
mbsy = 1; // Default.
mstb_l = 1;
mm_afx_gnt = ~am_gnt_l; // register current grant state.
state = curr_st; // register the current state.
cyctype = cyc_reg; // register the current cycletype.
case (state ) //synopsys parallel_case
`L1_RESET: begin // The initial state of the MCB state
// machine after power up.
state = `L1_WAIT ;
cyctype = `NONE;
end
`L1_WAIT: begin // Wait a cycle.
// Left-over from old power up seq.
cyctype = `NONE;
state = `L1_CBR;
end
`L1_CBR: begin // Loop and do 8 CbR refresh,
// for RAM init after wait.
if ( (rf_cbr == 1'b0) ) // If RAM init done, go to L1_IDLE.
begin
mbsy = 0;
cyctype = `NONE;
state = `L1_IDLE ;
end
else if (`RF_REQ) // If refresh is needed, do ref-cyc.
begin
state = `L3_RAS01;
cyctype = `CBR;
end
else // Wait for the refresh request.
begin
state = `L1_CBR;
end
end
`L1_IDLE: begin // This is the default state; The only state
// when MCB is not busy.
mbsy = 0;
cyctype = `NONE;
// As this state, the MCB state machine will also arbitrate
// for the next bus rquest from mmu, graphic and refresh. The
// IIe's implemenation adds the Falcon arbitration at this
// level and the priorities are :
//
// 1. If no pending cycle request, MCB states in IDLE state until
// a request is detected.
// 2. If one request is detected and no outstanding cycle pending,
// MCB will grant the request and begins a memory cycle.
// 3. When two or more requests are detected :
//
// i. MMU has the highest priority except when
// the current cycle is also MMU request. Then it
// will go the lowest priority.
// ii. Falcon has the second highest priority except when
// the current and the last cycles were also a Falcon
// request.
// iii. Refresh will has the lowest priority, except when
// the current cycle is MMU or FALCON request then
// refrech request will be granted next.
//
// The Falcon DMA request is treated as mmu request, except
// all RAS and CAS generation will be synchronized with g_clk.
// The synchornization is done using the sync_t2 generated
// for the graphic implemenation.
if ( `MM_REQ2 ) // For all MMU request, start here.
// Arbitration is done here and at
// the end of any mmu cycles.
begin
// If MM_REQ & IS_PAGE & ~sp_sel_1 & ~sp_sel_2 default any read to paged 8 byte
// DRAM Rd (DRD8P) and L3_RDP01T for not knowing the size.
// 1 byte and 2 byte writes are done with read modify write. Therefore,
// It started with a READ cycle.
mbsy = 1;
case (1'b1) //synopsys parallel_case
(~(dead_cyc | sp_sel_1 | sp_sel_2) & `IS_PAGE &
(`MM_RDX| `MM_WR1|`MM_WR2)):
begin // Case 1.
state = `L3_RDP01T ; // This is the default state and cycle
cyctype = `DRD8P; // type.
// If the request is for writing, set up the cycle type register.
case (1'b1) //synopsys parallel_case
`MM_WR1: begin
cyctype = `DRMW1P; // Read follow by write.
end
`MM_WR2: begin
cyctype = `DRMW2P; // Read follow by write.
end
endcase
end // End of case 1.
// If MM_REQ & IS_PAGE & ~sp_sel_1, again default any read to paged
// 8 byte DRAM Rd (DRD8P). However, there is a dead cycle, state machine
// will switch to L3_RDP01.
// For Speed 100, 125, and 150, 175, 200Mhz
((dead_cyc | (sp_sel_1 & ~sp_sel_2) | sp_sel_2 ) & `IS_PAGE &
(`MM_RDX| `MM_WR1|`MM_WR2) ):
begin // Case 2.
state = `L3_RDP01S ;
cyctype = `DRD8P;
// If the request is for 1 byte or 2 byte write, set up the
// for read modify write cycle to type register.
case (1'b1) //synopsys parallel_case
`MM_WR1: begin
cyctype = `DRMW1P;
end
`MM_WR2: begin
cyctype = `DRMW2P;
end
endcase
end // End of case 2.
((~(dead_cyc == 1'b0) | ~(bus_dec == 3'b000)) &
`IS_PAGE & (`MM_WR4|`MM_WR8|`MM_WR16) ):
begin // Case 3. When detected a write request.
state = `L3_WRP01 ;
case (1'b1) //synopsys parallel_case
`MM_WR4: begin
cyctype = `DWR4P;
end
`MM_WR8: begin
cyctype = `DWR8P;
end
`MM_WR16: begin
cyctype = `DWR16P;
end
endcase
end // End of case 3.
// Replace the following with dead cycle count on bus.
// Store double from store buffer and sbc now works the same.
((dead_cyc == 1'b0) & `IS_PAGE & (`MM_WR4|`MM_WR8|`MM_WR16) &
(bus_dec == 3'b000)) :
begin // Case 4
state = `L3_WRP02 ;
case (1'b1) //synopsys parallel_case
`MM_WR4: begin
cyctype = `DWR4P;
end
`MM_WR8: begin
cyctype = `DWR8P;
end
`MM_WR16: begin
cyctype = `DWR16P;
end
endcase
end // End of case 4
// Since size of read is unknown.
// If MM_REQ & NO_PAGE default any read to 8n and L3_RAS01
// for not knowing the size.
// This is the same as the page mode.
((`NO_PAGE ) & ~(precharge_p==1'b1)):
begin // Case 5
state = `L3_RAS01 ;
cyctype = `DRD8N;
case (1'b1) //synopsys parallel_case
`MM_WR1: begin
cyctype = `DRMW1N;
end
`MM_WR2: begin
cyctype = `DRMW2N;
end
`MM_WR4: begin
cyctype = `DWR4N;
end
`MM_WR8: begin
cyctype = `DWR8N;
end
`MM_WR16: begin
cyctype = `DWR16N;
end
endcase
end // End of case 5
((`NO_PAGE ) & (precharge_p==1'b1)):
begin // Case 6
state = `L3_RAS01X ;
cyctype = `DRD8N;
case (1'b1) //synopsys parallel_case
`MM_WR1: begin
cyctype = `DRMW1N;
end
`MM_WR2: begin
cyctype = `DRMW2N;
end
`MM_WR4: begin
cyctype = `DWR4N;
end
`MM_WR8: begin
cyctype = `DWR8N;
end
`MM_WR16: begin
cyctype = `DWR16N;
end
endcase
end // End of case 6
endcase // End of all 6 MMU transfer cases..
end // End of any MMU requests.
// add graphics request here, preceding check
// All graphic request is 3rd in priority
else if ( `G_REQ2 )
begin
mbsy = 1;
case (1'b1) //synopsys parallel_case
(`G_PAGE & `MM_RDX):
begin
cyctype = `GRD8P;
state = `L3_GRDT1;
end
(`G_PAGE & ~`MM_RDX):
begin
state = `L3_GWRT1;
case (1'b1) //synopsys parallel_case
`MM_WR1: begin
cyctype = `GWR1P;
end
`MM_WR2: begin
cyctype = `GWR2P;
end
`MM_WR4: begin
cyctype = `GWR4P;
end
`MM_WR8: begin
cyctype = `GWR8P;
end
`MM_WR16: begin
cyctype = `GWR16P;
end
endcase
end
(`NG_PAGE & `MM_RDX) :
begin
cyctype = `GRD8H;
state = `L3_GHIT1;
end
(`NG_PAGE & ~`MM_RDX):
begin
state = `L3_GHIT1;
case (1'b1) //synopsys parallel_case
`MM_WR1: begin
cyctype = `GWR1H;
end
`MM_WR2: begin
cyctype = `GWR2H;
end
`MM_WR4: begin
cyctype = `GWR4H;
end
`MM_WR8: begin
cyctype = `GWR8H;
end
`MM_WR16: begin
cyctype = `GWR16H;
end
endcase
end
endcase
if (dead_cyc | (~sync_t0) | fifo_full)
begin
state = `L3_SYNC;
end
end // end of graphics request
else if ( `AFX_REQ ) // If falcon request is detected,
// check if outstanding mmu requests
// were detected before proceeding.
begin
mbsy = 1;
state = `L1_CHECK ;
end // End of Falcon request.
// Refresh request is the lowest prioity, but became
// the highest when the current cycle is mmu or afx
// request. Arbitration is done at the end of the
// current cycle.
else if ( `RF_REQ )
begin
mbsy = 1;
state = `L1_CHECK ;
end // End of refresh request.
else if ( `SREF_REQ )
begin
mbsy = 1;
state = `L3_RAS01 ;
cyctype = `SREF ;
end // End of self refresh request.
end // End of L1_IDLE state.
// When a refresh request detected from the IDLE state, the state machine
// always check if any late MMU a request is pending. For IIe implemenation,
// the a late AFX request will also be granted at this state.
`L1_CHECK: begin // L1_CHECK state starts here.
// No need to set mbsy here, it was set at IDLE state, just
// before branching to L1_CHECK.
// The following logic is the same as the L1_IDLE state.
if ( `MM_REQ2 ) // Check for any MMU requests, again MMU will have
// the highest priority.
begin
// If MM_REQ & IS_PAGE & ~sp_sel_1 default any read to 8p
// & ~sp_sel_2
// and L3_RDP01T for not knowing the size.
case (1'b1) //synopsys parallel_case
(~(dead_cyc | sp_sel_1 | sp_sel_2) & `IS_PAGE & (`MM_RDX| `MM_WR1|`MM_WR2)):
begin // case 1 : a page read of sub-word write.
state = `L3_RDP01T ;
cyctype = `DRD8P;
// Detect cyctype & clock it in cyc_reg for sub-word write.
case (1'b1) //synopsys parallel_case
`MM_WR1: begin
cyctype = `DRMW1P;
end
`MM_WR2: begin
cyctype = `DRMW2P;
end
endcase
end
// If MM_REQ & IS_PAGE & ~sp_sel_1 default any read to 8p and
// 100, 125, 150, 175 and 200Mhz
// L3_RDP01T for not knowing the size.
((dead_cyc | (sp_sel_1 & ~sp_sel_2) | sp_sel_2) & `IS_PAGE & (`MM_RDX| `MM_WR1|`MM_WR2) ):
begin
state = `L3_RDP01S ;
cyctype = `DRD8P;
// detect cyctype & clock it in cyc_reg for write cases.
case (1'b1) //synopsys parallel_case
`MM_WR1: begin
cyctype = `DRMW1P;
end
`MM_WR2: begin
cyctype = `DRMW2P;
end
endcase
end
((~(dead_cyc == 1'b0) | ~(bus_dec == 3'b000)) &
`IS_PAGE & (`MM_WR4|`MM_WR8|`MM_WR16) ) :
begin
state = `L3_WRP01 ;
case (1'b1) //synopsys parallel_case
`MM_WR4: begin
cyctype = `DWR4P;
end
`MM_WR8: begin
cyctype = `DWR8P;
end
`MM_WR16: begin
cyctype = `DWR16P;
end
endcase
end
((dead_cyc == 1'b0) & `IS_PAGE & (`MM_WR4|`MM_WR8|`MM_WR16) &
(bus_dec == 3'b000) ):
begin
state = `L3_WRP02 ;
case (1'b1) //synopsys parallel_case
`MM_WR4: begin
cyctype = `DWR4P;
end
`MM_WR8: begin
cyctype = `DWR8P;
end
`MM_WR16: begin
cyctype = `DWR16P;
end
endcase
end
(`NO_PAGE):
begin
state = `L3_RAS01 ;
cyctype = `DRD8N;
case (1'b1) //synopsys parallel_case
`MM_WR1: begin
cyctype = `DRMW1N;
end
`MM_WR2: begin
cyctype = `DRMW2N;
end
`MM_WR4: begin
cyctype = `DWR4N;
end
`MM_WR8: begin
cyctype = `DWR8N;
end
`MM_WR16: begin
cyctype = `DWR16N;
end
endcase
end
endcase
end // End of any MMU requests
// Graphics request here, preceding check.
else if ( `G_REQ2 )
begin
case (1'b1) //synopsys parallel_case
(`G_PAGE & `MM_RDX):
begin
cyctype = `GRD8P;
state = `L3_GRDT1;
end
(`G_PAGE & ~`MM_RDX):
begin
state = `L3_GWRT1;
case (1'b1) //synopsys parallel_case
`MM_WR1: begin
cyctype = `GWR1P;
end
`MM_WR2: begin
cyctype = `GWR2P;
end
`MM_WR4: begin
cyctype = `GWR4P;
end
`MM_WR8: begin
cyctype = `GWR8P;
end
`MM_WR16: begin
cyctype = `GWR16P;
end
endcase
end
(`NG_PAGE & `MM_RDX) :
begin
cyctype = `GRD8H;
state = `L3_GHIT1;
end
(`NG_PAGE & ~`MM_RDX):
begin
state = `L3_GHIT1;
case (1'b1) //synopsys parallel_case
`MM_WR1: begin
cyctype = `GWR1H;
end
`MM_WR2: begin
cyctype = `GWR2H;
end
`MM_WR4: begin
cyctype = `GWR4H;
end
`MM_WR8: begin
cyctype = `GWR8H;
end
`MM_WR16: begin
cyctype = `GWR16H;
end
endcase
end
endcase
if (dead_cyc | (~sync_t0) | fifo_full | prom_wr_bsy)
begin
state = `L3_SYNC;
end
end // end of graphics request
else if ( `AFX_REQ ) // If Falcon request the afx bus for DMA.
// Falcon requests only 8 byte write/read.
begin // mbsy was set at IDLE state.
// All requests from Falcon are considered non-page. The exceptions
// are the burst request, which must be valid as soon as IIe drives
// valid_l (data strobe). The Falcon can burst up to 32 bytes before
// going back for re-arbitration.
cyctype = (`AFX_WR8)? `FDWR8N :`FDRD8N;
// L3_G_SYNC state is used to synchronize with g_clk.
state = (sync_t2) ? `L3_G_RAS01 : `L3_G_SYNC ;
end // End of all Falcon requests.
// If no other late request pending, start refresh cycle.
else if ( `RF_REQ )
begin
state = `L3_RAS01 ;
cyctype = `CBR;
end // end of refresh request
// Default to L1_CHECK, should never happen?
// IIe note : To prevent the withdraw of AFX_REQ, the default will
// return to IDLE state.
else begin
state = `L1_IDLE;
end
end // End of L1_CHECK state
`L3_SYNC: begin
// need to add issue_p
if (g_page_p)
begin
case (1'b1) //synopsys parallel_case
`MM_RD8: begin
cyctype = `GRD8P;
end
`MM_RD16: begin
cyctype = `GRD16P;
end
`MM_RD32: begin
cyctype = `GRD32P;
end
endcase
end
if (~g_page_p)
begin
case (1'b1) //synopsys parallel_case
`MM_RD8: begin
cyctype = `GRD8H;
end
`MM_RD16: begin
cyctype = `GRD16H;
end
`MM_RD32: begin
cyctype = `GRD32H;
end
endcase
end
if (dead_cyc | (~sync_t0) | fifo_full)
begin
state = `L3_SYNC;
end
// is it ok? should I make a sync_n state?
else
begin
if ((~g_issue_req_p && `GRDPX)||
(g_issue_req_p && `GRDPXT))
begin
state = `L3_GRDT1;
end
if (`GWRPX)
begin
state = `L3_GWRT1;
end
if ((`GWRHX) ||
(g_issue_req_p && `GRDHXT) ||
(~g_issue_req_p && `GRDHX)
)
begin
state = `L3_GHIT1;
end
end
end // end of graphics request
`L3_GWRT1: begin
state = `L3_GWRT2;
if ((cyc_reg==`GWR16P)||(cyc_reg==`GWR16H))
begin
mbsy = 1;
end
else if (
(cyc_reg==`GWR1H)||(cyc_reg==`GWR2H)||
(cyc_reg==`GWR4H)||(cyc_reg==`GWR8H)||
(cyc_reg==`GWR1P)||(cyc_reg==`GWR2P)||
(cyc_reg==`GWR4P)||(cyc_reg==`GWR8P))
begin
if (~`RF_REQ ) begin
state = `L3_GWRT2;
// mbsy = 0;
end
else if ( `RF_REQ ) begin
state = `L3_GWRTB;
end
end
end
`L3_GWRT2: begin
state = `L1_IDLE;
if ((cyc_reg==`GWR16P)||(cyc_reg==`GWR16H))
begin
if (sync_t2 && ~fifo_full && ~prom_wr_bsy) begin
state = `L3_GWRT3;
end
else begin
state = `L3_GWRT2;
end
end
else if (
(cyc_reg==`GWR1H)||(cyc_reg==`GWR2H)||
(cyc_reg==`GWR4H)||(cyc_reg==`GWR8H)||
(cyc_reg==`GWR1P)||(cyc_reg==`GWR2P)||
(cyc_reg==`GWR4P)||(cyc_reg==`GWR8P))
begin // IIe note : Check for Falcon request.
if (prom_wr_bsy) begin
state = `L3_GWRT2;
end
else if (`AFX_REQ) begin
state = `L3_GRDTN;
end
else begin
state = `L1_IDLE;
mbsy = 0;
end
end
end
`L3_GWRT3: begin
state = `L3_GWRT4;
end
`L3_GWRT4: begin
state = `L3_GWRT5;
end
`L3_GWRT5: begin
state = `L3_GWRT6;
end
`L3_GWRT6: begin
state = `L3_GWRT7;
end
`L3_GWRT7: begin
if (~`RF_REQ ) begin
state = `L3_GWRT8;
// mbsy = 0;
end
else if ( `RF_REQ ) begin
state = `L3_GWRTB;
end
end
// IIe note : For prom write access, the cycle will not terminated until
// prom_wr_bsy (p_reply == 10) is low.
`L3_GWRT8: begin // IIe note : Check for Falcon request.
if (prom_wr_bsy) begin
state = `L3_GWRT8;
end
else if (`AFX_REQ) begin
state = `L3_GRDTN;
end
else begin
state = `L1_IDLE;
mbsy = 0;
end
end
`L3_GHIT1: begin
state = `L3_GHIT2;
case (1'b1) //synopsys parallel_case
`MM_RD8: begin
cyctype = `GRD8H;
end
`MM_RD16: begin
cyctype = `GRD16H;
end
`MM_RD32: begin
cyctype = `GRD32H;
end
endcase
end
`L3_GHIT2: begin
state = `L3_GROT3;
end
`L3_GROT3: begin
state = `L3_GWRT1;
if (`GRDHX)
begin
state = `L3_GRDT1;
end
end
`L3_GRDT1: begin
state = `L3_GRDT2;
case (1'b1) //synopsys parallel_case
`MM_RD8: begin
cyctype = `GRD8P;
end
`MM_RD16: begin
cyctype = `GRD16P;
end
| This page: |
Created: | Thu Aug 19 12:03:24 1999 |
| From: |
../../../sparc_v8/ssparc/memif/rtl/rl_mcb_sm.v
|