`MM_RD32: begin
cyctype = `GRD32P;
end
endcase
end
`L3_GRDT2: begin
state = `L3_GRDT3;
end
`L3_GRDT3: begin
state = `L3_GRDT4;
end
`L3_GRDT4: begin
state = `L3_GRDT4;
if (sync_t1 & read_single)
begin
mstb_l = 0;
state = `L3_GRDT5;
if ((cyc_reg==`GRD8H)||(cyc_reg==`GRD8P))
begin
if ( ~`RF_REQ ) begin
state = `L3_GRDTN;
end
else if ( `RF_REQ ) begin
state = `L3_GRDTX;
end
end
else if ((cyc_reg==`GRD16H)||(cyc_reg==`GRD16P)||
(cyc_reg==`GRD32H)||(cyc_reg==`GRD32P))
begin
state = `L3_GRDT5;
end
end
end
`L3_GRDT5: begin
state = `L3_GRDT6;
end
`L3_GRDT6: begin
state = `L3_GRDT7;
end
`L3_GRDT7: begin
state = `L3_GRDT8;
end
`L3_GRDT8: begin
state = `L3_GRDT9;
end
`L3_GRDT9: begin
state = `L3_GRDTA;
end
`L3_GRDTA: begin
state = `L3_GRDTA;
if (sync_t1 & read_single) begin
mstb_l = 0;
if ((cyc_reg==`GRD16H)||(cyc_reg==`GRD16P))
begin
if ( ~`RF_REQ ) begin
state = `L3_GRDTN;
end
else if ( `RF_REQ ) begin
state = `L3_GRDTX;
end
end
else if ((cyc_reg==`GRD32H)||(cyc_reg==`GRD32P))
begin
state = `L3_GRDTB;
end
end
end
`L3_GRDTB: begin
state = `L3_GRDTC;
end
`L3_GRDTC: begin
state = `L3_GRDTD;
end
`L3_GRDTD: begin
state = `L3_GRDTE;
end
`L3_GRDTE: begin
state = `L3_GRDTF;
end
`L3_GRDTF: begin
state = `L3_GRDTG;
end
`L3_GRDTG: begin
state = `L3_GRDTG;
if (sync_t1 & read_single)
begin
mstb_l = 0;
state = `L3_GRDTH;
end
end
`L3_GRDTH: begin
state = `L3_GRDTI;
end
`L3_GRDTI: begin
state = `L3_GRDTJ;
end
`L3_GRDTJ: begin
state = `L3_GRDTK;
end
`L3_GRDTK: begin
state = `L3_GRDTL;
end
`L3_GRDTL: begin
state = `L3_GRDTM;
end
`L3_GRDTM: begin
state = `L3_GRDTM;
if (sync_t1 & read_single)
begin
mstb_l = 0;
if ( ~`RF_REQ ) begin
state = `L3_GRDTN;
end
else if ( `RF_REQ ) begin
state = `L3_GRDTX;
end
end
end
`L3_GRDTN: begin // IIe note : Check for Falcon request.
if (`AFX_REQ) begin
state = (sync_t2) ? `L3_G_RAS01 : `L3_G_SYNC;
cyctype = (`AFX_WR8) ? `FDWR8N : `FDRD8N;
end
else begin
state = `L1_IDLE;
mbsy = 0;
end
end
// states for cyc_end
`L3_GRDTX: begin
state = `L2_CYCEND ;
end
`L3_GWRTB: begin
state = (prom_wr_bsy) ? `L3_GWRTB : `L2_CYCEND;
end
// end of graphic states
`L3_RDP01T: begin
state = `L3_RDP01;
if (read_dec == 3'b000) begin
state = `L3_RDP01;
end
else begin
state = `L3_RDP01T;
end
// detect cyctype & clock it in cyc_reg for delay read
case (1'b1) //synopsys parallel_case
`MM_RD8: begin
cyctype = `DRD8P;
end
`MM_RD16: begin
cyctype = `DRD16P;
end
`MM_RD32: begin
cyctype = `DRD32P;
end
endcase
end
`L3_RDP01S: begin
if ((dead_cyc == 1'b0) & (r175_dec == 1'b0)) begin
state = `L3_RDP01T;
end
else begin
state = `L3_RDP01S;
end
// detect cyctype & clock it in cyc_reg for delay read
case (1'b1) //synopsys parallel_case
`MM_RD8: begin
cyctype = `DRD8P;
end
`MM_RD16: begin
cyctype = `DRD16P;
end
`MM_RD32: begin
cyctype = `DRD32P;
end
endcase
end
`L3_RDP01: begin
state = `L3_RDP02B ;
if ((cyc_reg==`DRD8P )|(cyc_reg==`DRD8N )) begin
mstb_l = 0;
if ( `RF_REQ | `AFX_REQ) begin
state = `L3_RDP02A ; // cycs pending.
end
else begin
state = `L3_RDP02B ; // no cycs pending.
end
end
if ( (cyc_reg==`DRD16P)|(cyc_reg==`DRD16N)
|(cyc_reg==`DRD32P)|(cyc_reg==`DRD32N)) begin
mstb_l = 0;
state = `L3_RDM01;
end
if ( (cyc_reg==`DRMW1P)|(cyc_reg==`DRMW2P)
|(cyc_reg==`DRMW1N)|(cyc_reg==`DRMW2N) ) begin
state = `L3_RMWP01 ;
end
end // of L3_RDP01
`L3_RDP02A: begin /* entered if other req is pending.*/
if (`AFX_REQ) begin
state = (sync_t2) ? `L3_G_RAS01 : `L3_G_SYNC;
cyctype = (`AFX_WR8) ? `FDWR8N : `FDRD8N;
end
else begin
state = `L2_CYCEND ;
end
end
`L3_RDP02B: begin /* entered if no RFR req .*/
if (`AFX_REQ) begin
state = (sync_t2) ? `L3_G_RAS01 : `L3_G_SYNC;
cyctype = (`AFX_WR8) ? `FDWR8N : `FDRD8N;
end
else begin
mbsy = 0;
state = `L1_IDLE ;
end
end
`L3_RDM01: begin
state = `L3_RDM02;
end
`L3_RDM02: begin
state = `L3_RDM03T;
if (!(cas_dec == 2'b00)) begin
state = `L3_RDM02;
end
else begin
state = `L3_RDM03T;
end
end
`L3_RDM03T: begin
state = `L3_RDM03;
if (read_dec == 3'b000) begin
state = `L3_RDM03;
end
else begin
state = `L3_RDM03T;
end
end
`L3_RDM03: begin
mstb_l = 0;
state = `L3_RDM04;
if ((cyc_reg==`DRD16P)|(cyc_reg==`DRD16N)) begin
if ( `RF_REQ | `AFX_REQ) begin
state = `L3_RDP02A ; /* cycs pending.*/
end
else begin
state = `L3_RDP02B ; /* no cycs pending.*/
end
end
end
`L3_RDM04: begin
state = `L3_RDM05;
end
`L3_RDM05: begin
state = `L3_RDM06T;
if (!(cas_dec == 2'b00)) begin
state = `L3_RDM05;
end
else begin
state = `L3_RDM06T;
end
end
`L3_RDM06T: begin
state = `L3_RDM06;
if (read_dec == 3'b000) begin
state = `L3_RDM06;
end
else begin
state = `L3_RDM06T;
end
end
`L3_RDM06: begin
mstb_l = 0;
state = `L3_RDM07;
end
`L3_RDM07: begin
state = `L3_RDM08;
end
`L3_RDM08: begin
state = `L3_RDM09T;
if (!(cas_dec == 2'b00)) begin
state = `L3_RDM08;
end
else begin
state = `L3_RDM09T;
end
end
`L3_RDM09T: begin
state = `L3_RDM09;
if (read_dec == 3'b000) begin
state = `L3_RDM09;
end
else begin
state = `L3_RDM09T;
end
end
`L3_RDM09: begin
mstb_l = 0;
if ( `RF_REQ | `AFX_REQ) begin
state = `L3_RDP02A ; /* cycs pending.*/
end
else begin
state = `L3_RDP02B ; /* no cycs pending.*/
end
end
`L3_RMWP01: begin
state = `L3_RMWP02;
end /* of L3_RMWP01. */
`L3_RMWP02: begin
state = `L3_RMWP02X;
end /* of L3_RMWP02. */
`L3_RMWP02X: begin
state = `L3_WRP01;
if (rmw_dec == 3'b000) begin
state = `L3_WRP01;
end
else begin
state = `L3_RMWP02X;
end
end
`L3_WRP01: begin
state = `L3_WRP02;
if ((bus_dec == 3'b000) & (dead_cyc == 1'b0))
begin
state = `L3_WRP02;
end
else begin
state = `L3_WRP01;
end
end
`L3_WRP02: begin
state = `L3_WRP02W;
if (wr5_dec == 2'b00) begin
state = `L3_WRP02W;
end
else begin
state = `L3_WRP02;
end
end
//Add simple if statement without changing previous paths.
`L3_WRP02W: begin
state = `L3_WRP02W;
if ((wr6_dec == 2'b00)) begin
if ((cyc_reg==`DWR16P)|(cyc_reg==`DWR16N)) begin
state = `L3_WRP03C ;
end
else if ( `RF_REQ | `AFX_REQ ) begin
state = `L3_WRP03A ; /* cycs pending.*/
end
else begin
state = `L3_WRP03B ; // no cycs pending.
end
end
end
`L3_WRP03A: begin
if (`AFX_REQ) begin
state = (sync_t2) ? `L3_G_RAS01 : `L3_G_SYNC;
cyctype = (`AFX_WR8) ? `FDWR8N : `FDRD8N;
end
else begin
state = `L2_CYCEND ;
end
end
`L3_WRP03B: begin
if (`AFX_REQ) begin
state = (sync_t2) ? `L3_G_RAS01 : `L3_G_SYNC;
cyctype = (`AFX_WR8) ? `FDWR8N : `FDRD8N;
end
else begin
mbsy = 0;
state = `L1_IDLE ;
end
end
`L3_WRP03C: begin
state = `L3_WRP04 ;
end
`L3_WRP04: begin
state = `L3_WRP05 ;
end
`L3_WRP05: begin
state = `L3_WRP06;
if (wr5_dec == 2'b00) begin
state = `L3_WRP06;
end
else begin
state = `L3_WRP05;
end
end
//Add simple if statement without changing previous paths.
`L3_WRP06: begin
if (!(wr6_dec == 2'b00)) begin
state = `L3_WRP06;
end
else if ( `RF_REQ | `AFX_REQ ) begin
state = `L3_WRP03A ; /* cycs pending.*/
end
else begin
state = `L3_WRP03B ; // no cycs pending.
end
end
`L3_RAS01: begin
state = `L3_RAS01X; /* No L3_RAS02 state!!!*/
/* detect cyctype & clock it in cyc_reg for delay read*/
case (1'b1) //synopsys parallel_case
`MM_RD8: begin
cyctype = `DRD8N;
end
`MM_RD16: begin
cyctype = `DRD16N;
end
`MM_RD32: begin
cyctype = `DRD32N;
end
endcase
end /* of L3_RAS01.*/
`L3_RAS01X: begin
state = `L3_RAS02;
if (rmw_dec == 3'b000) begin
state = `L3_RAS02;
end
else begin
state = `L3_RAS01X;
end
/* detect cyctype & clock it in cyc_reg for delay read*/
case (1'b1) //synopsys parallel_case
`MM_RD8: begin
cyctype = `DRD8N;
end
`MM_RD16: begin
cyctype = `DRD16N;
end
`MM_RD32: begin
cyctype = `DRD32N;
end
endcase
end
`L3_RAS02: begin
state = `L3_RAS03;
case (cyc_reg) //synopsys parallel_case
`CBR: begin
state = `L3_RAS02X;
end
`SREF: begin
state = `L3_RAS02X;
end
endcase /* of cyctype in L3_RAS02. */
end /* of L3_RAS02.*/
`L3_RAS02X: begin
state = `L3_CBR01 ;
end
`L3_RAS03: begin
if (~sp_sel_2) begin
state = `L3_RAS04 ;
end
else begin
state = `L3_RAS03X;
end
end /* of `L3_RAS03 */
`L3_RAS03X: begin
state = `L3_RAS04 ;
end /* of `L3_RAS03X */
`L3_RAS04: begin
state = `L3_RAS05;
if (ras_dec == 3'b000) begin
if ( (cyc_reg==`DWR8N)|(cyc_reg==`DWR4N)|
(cyc_reg==`DWR16N) ) begin
state = `L3_WRP02;
end
else begin
state = `L3_RAS05;
end
end
else begin
state = `L3_RAS04;
end
end
`L3_RAS05: begin
state = `L3_RDP01T ;
if ((sp_sel_1 == 1'b1 & sp_sel_2 == 1'b0) | sp_sel_2 == 1'b1) begin
state = `L3_RDP01S;
end
else begin
state = `L3_RDP01T ;
end
end
`L3_CBR01: begin
state = `L3_CBR02;
if ((cyc_reg==`SREF)&& ( `SREF_REQ )) begin
state = `L3_SRF01 ;
end
end
`L3_SRF01: begin
mbsy = 0;
if (mm_rf_cntl_3 == 1'b0) begin /* if not initial 8 CbR cycs*/
state = `L3_CBR01;
end
else begin
state = `L3_SRF01;
end
end
`L3_CBR02: begin
state = `L3_CBR03;
if (cbr_dec == 3'b000) begin
state = `L3_CBR03;
end
else begin
state = `L3_CBR02;
end
end
`L3_CBR03: begin
state = `L3_CBR04;
end
`L3_CBR04: begin
state = `L3_CBR05;
end
`L3_CBR05: begin
state = `L3_CBR06;
end
`L3_CBR06: begin
state = `L3_CBR07;
if (rf_cbr == 1'b0) begin /* if not initial 8 CbR cycs*/
end
end
`L3_CBR07: begin
if (rf_cbr == 1'b0) begin /* if not initial 8 CbR cycs*/
if (`AFX_REQ) begin
state = (sync_t2) ? `L3_G_RAS01 : `L3_G_SYNC;
cyctype = (`AFX_WR8) ? `FDWR8N : `FDRD8N;
end
else begin
state = `L1_IDLE;
mbsy = 0;
end
end
else begin
state = `L1_CBR;
end
end
// IIe note : These are new states created for the Falcon access.
// They are same as the MMU request, except they will
// progress to the new state if and only if sync_t2
// is enabled (next ss_clock is the rising edge of g_clk).
// For non-page mode and RAS prechage, the DRAM access begins with
// RAS cycle here.
`L3_G_SYNC: begin // The state is only used to synchronized with g_clk.
if (`AFX_REQ) begin
state = (sync_t2) ? `L3_G_RAS01 : `L3_G_SYNC;
end
else begin // Before committing to Falcon grant, make sure
// Falcon is still requesting the memory bus.
// Otherwise, return to IDLE.
state = `L1_IDLE;
mbsy = 0;
end
end
`L3_G_RAS01: begin // The RAS are synchronized with g_clk.
// If speed select is 1 then 1 more g_clk
// to pre-charge.
mm_afx_gnt = 1'b1;
state = (sync_t2 && (sp_sel_2 == 1'b1 )) ? `L3_G_RAS01XX :
(sync_t2 && (sp_sel_1 == 1'b1)) ? `L3_G_RAS01X :
(sync_t2) ? `L3_G_RAS02 : `L3_G_RAS01;
end
`L3_G_RAS01XX: begin // Total precharge cycle == 9.5.
state = (sync_t2 )? `L3_G_RAS01X : `L3_G_RAS01XX;
end
`L3_G_RAS01X: begin // Total precharge cycle == 6.5.
state = (sync_t2 )? `L3_G_RAS02 : `L3_G_RAS01X;
end
`L3_G_RAS02: begin // Start RAS active cycle
// For 85Mhz or below suring a write operation,
// only 5.5 refclk cycles are needed. Therefore
// RAS03 state is bypassed.
state = (sync_t2 && ({sp_sel_2, sp_sel_1} == 2'b00) &&
(cyc_reg == `FDWR8N)) ? `L3_G_RAS04 :
(sync_t2) ? `L3_G_RAS03 : `L3_G_RAS02;
end
`L3_G_RAS03: begin
state = (sync_t2 && ((({sp_sel_1, sp_sel} == 2'b11) &&
(cyc_reg == `FDRD8N)) | sp_sel_2 == 1'b1))? `L3_G_RAS03X :
(sync_t2) ? `L3_G_RAS04 : `L3_G_RAS03;
end
`L3_G_RAS03X: begin // This state adds 3 RAS active cycles for 125MHz and above.
state = (sync_t2) ? `L3_G_RAS04 : `L3_G_RAS03X;
end
`L3_G_RAS04: begin // For a write cycle, RAS cycle active requirement is
// met after this state.
// For read cycle and speed select is 0 (lowest), RAS
// cycle requirement is also met.
state = (sync_t2 & // (
// ((cyc_reg==`FDRD8N)&&({sp_sel_2, sp_sel_1, sp_sel} == 3'b000)) ||
((cyc_reg==`FDWR8N) && sp_sel_2 == 1'b0)) ? // deleted 1 ) before ?
`L3_G_RDP01 : (sync_t2) ? `L3_G_RAS05 : `L3_G_RAS04;
end
`L3_G_RAS05: begin
state = (sync_t2) ? `L3_G_RDP01 : `L3_G_RAS05;
end
// The maximum Falcon burst transfers (any combination of read or write)
// are 32 bytes without go to another arbitrate state (IDLE or RDM09).
// The new Falcon protocol will drive the request as soon as valid_l is
// enable. So that the can make the arbitration during the read, hence save
// 1 gclk for burst transfer.
// With the g_clk slew, the IIe will sample all falcon signals at t1, elevate
// them at t2.
`L3_G_RDP01: begin
if (sync_t2) begin
// Check if any outstanding Falcon requests are pending. The IIe will
// allow Falcon to keep the bus for up to 4 cycles.
if (mm_afx_req & ~afx_limit) begin
//if ({sp_sel_2,sp_sel_1} == 2'b11) begin
if (sp_sel_2 == 1'b1) begin // fix for cas low less than 4 cycles at 150Mhz
state = `L3_G_CAS175;
cyctype = (mm_afx_read) ? `FDRD8N :`FDWR8N;
end
else begin
state = `L3_G_RDM01;
cyctype = (mm_afx_read) ? `FDRD8N :`FDWR8N;
end
end
//else if ({sp_sel_2,sp_sel_1} == 2'b11) begin
else if (sp_sel_2 == 1'b1) begin // fix for cas low less than 4 cycles at 150Mhz
state = `L3_G_RDP175;
end
else if (`RF_REQ) begin
state = `L3_G_RDP02A ;
end
else begin
state = `L3_G_RDP02B ;
end
end
else begin
state = `L3_G_RDP01;
end
end
// begin
`L3_G_CAS175: begin
if (sync_t2) begin
state = `L3_G_RDM01;
end
else begin
state = `L3_G_CAS175;
end
end
`L3_G_RDP175: begin
if (sync_t2) begin
if (`RF_REQ) begin
state = `L3_G_RDP02A ;
end
else begin
state = `L3_G_RDP02B ;
end
end
else begin
state = `L3_G_RDP175;
end
end
// end
`L3_G_RDM01: begin
// For 70Mhz operation, only 3 refclk cycles are needed for CAS.
// for up to 200Mhz, 6 refclk cycles is enough for CAS. don't need change logic.
state = (sync_t2 & // ( to solve burst rd problem at 70Mhz.
// ((cyc_reg==`FDRD8N)&&({sp_sel_2, sp_sel_1, sp_sel} == 3'b000)) ||
((cyc_reg==`FDWR8N) && (sp_sel_2 == 1'b0))) ? // deleted 1 ) before ?
`L3_G_RDP01 : (sync_t2) ? `L3_G_RDM02 : `L3_G_RDM01;
end
`L3_G_RDM02: begin
state = (sync_t2) ? `L3_G_RDP01 : `L3_G_RDM02;
end
`L3_G_RDP02A: begin
state = (sync_t2)? `L3_G_WAIT1 : `L3_G_RDP02A;
mm_afx_gnt = (sync_t2)? 0 : 1;
end
`L3_G_RDP02B: begin
state = (sync_t2)? `L3_G_WAIT2 : `L3_G_RDP02B;
mm_afx_gnt = (sync_t2)? 0 : 1;
end
`L3_G_WAIT1: begin
state = (sync_t2)? `L2_CYCEND : `L3_G_WAIT1;
end
`L3_G_WAIT2: begin
state = (sync_t2)? `L1_IDLE : `L3_G_WAIT2;
mbsy = (~sync_t0) ? 1'b0 : 1'b1;
end
// End of state for Falcon request cycles.
`L2_CYCEND: begin
cyctype = `CBR;
state = `L3_RAS01;
end
endcase
end // End of the "else" for rst=0
l_st_fn[18:0] = {mm_afx_gnt, mbsy, mstb_l, cyctype[6:0], state[8:0]};
end // End of the first begin, in the function.
endfunction
/*---------------------------------------------------------------------*/
wire g_issue_req
;
wire g_issue_req_p;
wire g_page, g_page_p;
/* Call the l_st_fn function in the module and assign it to the wires. */
/*==================================================================*/
assign
{mm_afx_gnt, mbsy, mstb_l, cyctype, next_st}
= l_st_fn(curr_st, cyc_reg, mm_issue_req2, mm_mreq, is_page,
rf_cbr, rf_rreq_l, rst, sp_sel, sp_sel_1, sp_sel_2, precharge_p,
mm_rf_cntl_3, mm_issue_req_early, read_dec,
rmw_dec, ras_dec, wr5_dec, wr6_dec, r175_dec, cas_dec, bus_dec,
cbr_dec, sync_t0, sync_t1, sync_t2, fifo_full,
dead_cyc, read_single, mm_fb_req,
g_issue_req_p, g_page_p, mm_fb_page,
mm_afx_req, mm_afx_read, am_gnt_l);
/* Registers for the cycle-type and current-state. Used by the l_st_fn
state machine function and other signals.*/
// open cyc_reg regiters 3:0 after issue req due to graphics instrcutions.
/*==================================================================*/
//remove hold
// GReg8 ffh_l_st(curr_st[7:0], next_st[7:0], ss_clock, Gnd);
Mflipflop_noop_9 ffh_l_st(curr_st[8:0], next_st[8:0], ss_clock);
// GReg5 ffh_srcreg(cyc_reg[4:0], cyctype[4:0], ss_clock, cyc_hld);
// GReg3 ffh_srcreg53(cyc_reg[5:3], cyctype[5:3], ss_clock, cyc_hld);
// GReg3 ffh_srcreg210(cyc_reg[2:0], cyctype[2:0], ss_clock, cyc_hld_read);
GReg3 ffh_srcreg54(cyc_reg[6:4], cyctype[6:4], ss_clock, cyc_hld);
GReg4 ffh_srcreg30(cyc_reg[3:0], cyctype[3:0], ss_clock, cyc_hld_read);
// for timing, duplicate above registers and used for SM only
//remove hold
// GReg8 ffh_l_st_2(curr_st_2[7:0], next_st[7:0], ss_clock, Gnd);
Mflipflop_noop_9 ffh_l_st_2(curr_st_2[8:0], next_st[8:0], ss_clock);
GReg3 ffh_srcreg54_2(cyc_reg_2[6:4], cyctype[6:4], ss_clock, cyc_hld);
GReg4 ffh_srcreg30_2(cyc_reg_2[3:0], cyctype[3:0], ss_clock, cyc_hld_read);
//remove hold
// GReg1 ffh_sync_t2(sync_t2, sync_t1, ss_clock, Gnd);
Mflipflop_noop_1 ffh_sync_t2(sync_t2, sync_t1, ss_clock);
/* The hold signal for cycle_type register (cyc_hld) */
/*==================================================================*/
assign cyc_hld = ~( (rst==1'b1) ||
(curr_st==`L1_RESET) ||
(curr_st==`L1_WAIT) ||
( (curr_st==`L1_CBR)&&
( (rf_cbr==1'b0)||(`RF_REQ) ) ) ||
(curr_st==`L1_IDLE) ||
(curr_st==`L1_CHECK) ||
(curr_st==`L3_GRDTN) ||
(curr_st==`L3_WRP03A) ||
(curr_st==`L3_WRP03B) ||
(curr_st==`L3_RDP02A) ||
(curr_st==`L3_RDP02B) ||
(sync_t2 &&
(curr_st==`L3_G_RDP02A) ||
(curr_st==`L3_G_RDP02B) ||
(curr_st==`L3_G_RDP01)) ||
(curr_st==`L3_G_WAIT1) ||
(curr_st==`L3_G_WAIT2) ||
(curr_st==`L2_CYCEND) ||
((curr_st==`L3_CBR07) && (rf_cbr == 1'b0)) );
wire mm_issue_req_p;
wire readx_p;
wire readx = (`MM_RDX);
//remove hold
// GReg1 ffh_issue_req(mm_issue_req_p, mm_issue_req, ss_clock, Gnd);
// GReg1 ffh_mm_mreq(readx_p, readx, ss_clock, Gnd);
Mflipflop_noop_1 ffh_issue_req(mm_issue_req_p, mm_issue_req, ss_clock);
Mflipflop_noop_1 ffh_mm_mreq(readx_p, readx, ss_clock);
// add graphics issue_req_p for graphics read
// wire g_issue_req;
// wire g_issue_req_p;
assign g_issue_req = (`G_ISS == 1'b1);
//remove hold
// GReg1 ffh_gissue_req(g_issue_req_p, g_issue_req, ss_clock, Gnd);
Mflipflop_noop_1 ffh_gissue_req(g_issue_req_p, g_issue_req, ss_clock);
assign cyc_hld_read = cyc_hld & ~((mm_issue_req_p | g_issue_req_p) & readx_p);
// wire g_page, g_page_p;
assign g_page = (`G_PAGE == 1'b1);
//remove hold
// GReg1 ffh_g_page(g_page_p, g_page, ss_clock, Gnd);
Mflipflop_noop_1 ffh_g_page(g_page_p, g_page, ss_clock);
/* Instanciate mcb-page, to produce 'is-page'. */
/*==================================================================*/
// rl_mcb_page ispage (is_page, mm_page, rst, ss_clock, cyc_reg);
rl_mcb_page ispage (is_page, mm_page, ras_dis, mm_lst_cyc_afx, pa25_flag, ss_clock);
// pass counter values over here.
state_count_1 rl_mcb_count(read_dec, rmw_dec, ras_dec, wr5_dec, wr6_dec, r175_dec,
cas_dec, bus_dec, cbr_dec, curr_st, cyc_reg, sp_sel, sp_sel_1, sp_sel_2,
rst, ss_clock);
// IIe note : Falcon transfer book keeping. A 3 bit counter is used to keep the of the number
// of Falcon DMA transfers. It will rise the limit flag when the number of Falcon
// cycles reach four.
afx_count falcon_limit(afx_limit, curr_st, sync_t0, rst, ss_clock);
endmodule
// This are the counters used in the state machines.
// 6 re-usable counters loaded except during inside the state itself.
//module rl_col_inc(col_inc, col_mm, ld_ct, mode_ct, inc_ct, ss_clock);
![[Up: rl_mcb_sm rl_mcb_count]](v2html-up.gif)
module state_count_1(read_dec, rmw_dec, ras_dec, wr5_dec, wr6_dec, r175_dec, cas_dec,
bus_dec, cbr_dec,
curr_st, cyc_reg, sp_sel, sp_sel_1, sp_sel_2, rst, ss_clock);
output [2:0] read_dec; // Registered o/p from GReg2.
output [2:0] rmw_dec; // Registered o/p from GReg2.
output [2:0] ras_dec; // Registered o/p from GReg2.
output [1:0] wr5_dec;
output [1:0] wr6_dec;
output r175_dec;
output [1:0] cas_dec;
output [2:0] bus_dec;
output [2:0] cbr_dec; // Registered o/p from GReg2.
input [8:0] curr_st;
input [6:0] cyc_reg;
input sp_sel;
input sp_sel_1;
input sp_sel_2;
input rst;
input ss_clock;
// read counter specific.
wire [2:0] incr_w;
wire Gnd = 0 ;
wire ld_ct, dec_ct;
assign dec_ct = ((curr_st==`L3_RDP01T) || (curr_st==`L3_RDM03T) ||
(curr_st==`L3_RDM06T) || (curr_st==`L3_RDM09T));
assign ld_ct = ~dec_ct;
//------------- incr function --------------------------------
// Is a 2 bit loadable-decrementor used for decrementing the
// column address in block type accesses (I$, D$, SBus).
//-------------------------------------------------------------
function [2:0] f_decr;
input sp_sel, sp_sel_1, sp_sel_2;
input [2:0] read_dec;
input ld_ct, dec_ct;
begin
f_decr = read_dec;
if ( ld_ct == 1'b1 ) begin /* load the input. */
case (({sp_sel_2, sp_sel_1,sp_sel})) //PARALLEL_CASE
3'b000: f_decr = 3'b000;
3'b001: f_decr = 3'b001;
3'b010: f_decr = 3'b001;
3'b011: f_decr = 3'b010;
3'b100: f_decr = 3'b011;
3'b101: f_decr = 3'b011;
3'b110: f_decr = 3'b100;
3'b111: f_decr = 3'b101;
endcase
end
else if ( dec_ct == 1'b1 ) begin /* count up.*/
f_decr = read_dec - 3'b001; // Modulo-2 counter.
end
end
endfunction
//remove hold
// GReg2 ffh_col_inc (read_dec[1:0], incr_w[1:0], ss_clock, Gnd );
Mflipflop_noop_3 ffh_col_inc (read_dec[2:0], incr_w[2:0], ss_clock );
//-------------------------------------------------------------
assign incr_w = f_decr(sp_sel,sp_sel_1,sp_sel_2,read_dec,ld_ct,dec_ct);
// end read counter
// RMWP02X, RAS01X counter specific.
wire [2:0] incr_w_rmw;
wire ld_ct_rmw, dec_ct_rmw;
assign dec_ct_rmw = ((curr_st==`L3_RMWP02X) || (curr_st==`L3_RAS01X));
assign ld_ct_rmw = ~dec_ct_rmw;
//------------- incr function --------------------------------
// Is a 3 bit loadable-decrementor used for decrementing the
// column address in block type accesses (I$, D$, SBus).
//-------------------------------------------------------------
function [2:0] f_decr_rmw;
input sp_sel, sp_sel_1, sp_sel_2;
input [2:0] rmw_dec;
input ld_ct_rmw, dec_ct_rmw;
begin
f_decr_rmw = rmw_dec;
if ( ld_ct_rmw == 1'b1 ) begin /* load the input. */
case (({sp_sel_2, sp_sel_1,sp_sel})) //PARALLEL_CASE
3'b000: f_decr_rmw = 3'b000;
3'b001: f_decr_rmw = 3'b000;
3'b010: f_decr_rmw = 3'b001;
3'b011: f_decr_rmw = 3'b010;
3'b100: f_decr_rmw = 3'b011;
3'b101: f_decr_rmw = 3'b011;
3'b110: f_decr_rmw = 3'b100;
3'b111: f_decr_rmw = 3'b101;
endcase
end
else if ( dec_ct_rmw == 1'b1 ) begin /* count up.*/
f_decr_rmw = rmw_dec - 3'b001; // Modulo-2 counter.
end
end
endfunction
//remove hold
// GReg2 ffh_col_inc_rmw (rmw_dec[2:0], incr_w_rmw[2:0], ss_clock, Gnd );
Mflipflop_noop_3 ffh_col_inc_rmw (rmw_dec[2:0], incr_w_rmw[2:0], ss_clock );
//-------------------------------------------------------------
assign incr_w_rmw = f_decr_rmw(sp_sel,sp_sel_1,sp_sel_2, rmw_dec,ld_ct_rmw,dec_ct_rmw);
// end rmw counter
// RAS04 counter specific.
wire [2:0] incr_w_ras;
wire ld_ct_ras, dec_ct_ras;
assign dec_ct_ras = (curr_st==`L3_RAS04) ;
assign ld_ct_ras = ~dec_ct_ras;
//------------- incr function --------------------------------
// Is a 3 bit loadable-decrementor used for decrementing the
// column address in block type accesses (I$, D$, SBus).
//-------------------------------------------------------------
function [2:0] f_decr_ras;
input sp_sel, sp_sel_1, sp_sel_2;
input [2:0] ras_dec;
input ld_ct_ras, dec_ct_ras;
input [6:0] cyc_reg;
begin
f_decr_ras = ras_dec;
if ( ld_ct_ras == 1'b1 ) begin /* load the input. */
case (({sp_sel_2, sp_sel_1,sp_sel})) //PARALLEL_CASE
3'b000: f_decr_ras = ( (cyc_reg==`DWR8N)|(cyc_reg==`DWR4N) ) ?
3'b000 : 3'b001;
3'b001: f_decr_ras = 3'b001;
3'b010: f_decr_ras = 3'b001;
3'b011: f_decr_ras = 3'b010;
3'b100: f_decr_ras = 3'b010;
3'b101: f_decr_ras = 3'b010;
3'b110: f_decr_ras = 3'b011;
3'b111: f_decr_ras = 3'b100;
endcase
| This page: |
Created: | Thu Aug 19 12:03:26 1999 |
| From: |
../../../sparc_v8/ssparc/memif/rtl/rl_mcb_sm.v
|