/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)rl_va_mux.v
***
****************************************************************************
****************************************************************************/
/*****************************************************************************/
/* @(#)rl_va_mux.v 1.29 4/20/93 */
/* rl_va_mux.v */
/* */
/* Description: */
/* This module describes the virtual address muxing */
/* (va_mux) model, of the input address to the MMU */
/* datapath. This is a RTL model that describes */
/* the datapath of the multiplexing required to form */
/* the virtual address the TLB tag compare, supporting */
/* virtual address translation bypass, and the loading */
/* of the SFAR register. */
/* */
/*****************************************************************************/
module rl_va_mux
(
tlb_wrt_tag, tlb_asel, tlb_io_bit, c_en,
hld_mmu_cr, hld_ctpr, hld_sfsr, rd_sfsr, hld_sfar,
hld_trcr, hld_cxr,
io_op, flush_ioall,
sel_mdat_mux, mmstben_reg, dp_asi_dcd6,
r_d_vaddr,r_d_vaddr_02,
io_tlb_nxt, tlb_tag_reload, tw_io_bit,
asi_write, asi_dcd4, asi_dcd6, tlb_asi_act,
mmstben, mmstben_aarb, mmreg_rd_asi,mmu_asi_op,
tlb_tag_we, tlb_data_we, tlb_update,
flush_iopte, mmu_en_e, tlb_flush, io_mmu_en,
ss_clock,ss_reset);
output tlb_wrt_tag
; /* Decoded TLB tag write select.*/
output tlb_asel
; /* tlb input address select*/
output tlb_io_bit
; /* tlb input IO bit */
output c_en
; /* TLB Compare data strobe input */
output hld_mmu_cr
; /* Hold enable for MMU control reg.*/
output hld_ctpr
; /* Hold enable for CTPR.*/
output hld_sfsr
; /* Hold enable for Sync. Fault Status*/
output rd_sfsr
; /* Read decode for Sync. Fault Status*/
output hld_sfar
; /* Hold enable for Sync. Fault Address*/
output hld_trcr
; /* Hold enable for TLB Replc. Cntl reg.*/
output hld_cxr
; /* Hold enable for Context register*/
output io_op
; /* indicates current cycle is a IO op.*/
output sel_mdat_mux
; /* reg'd version of asi_dcd & mmstben.*/
output mmstben_reg
; /* reg'd version of mmstben.*/
output dp_asi_dcd6
; /* special asi_dcd6 for bug#680 fix */
input [12:08] r_d_vaddr
; /* registered data virtual addr.*/
input r_d_vaddr_02
; /* registered data virtual addr.*/
input io_tlb_nxt
; /* select IO address.*/
input tw_io_bit
; /* .*/
input asi_write
; /* indicates an ASI write this cycle.*/
input asi_dcd4
; /* indicates current ASI=0x4.*/
input asi_dcd6
; /* indicates current ASI=0x6. (TLB)*/
input tlb_asi_act
;
input mmu_asi_op
;
input mmstben
; /* Strobe indicating mc_mdata bus is valid*/
input mmstben_aarb
; /* Strobe indicating mc_mdata bus is valid*/
input mmreg_rd_asi
; /* */
input tlb_tag_we
; /* MMU SM write enable for the TLB.*/
input tlb_data_we
; /* MMU SM write enable for the TLB.*/
input tlb_update
; /* TLB update from read word in progress*/
input flush_iopte
;
input flush_ioall
;
input mmu_en_e
;
input tlb_flush
;
input io_mmu_en
;
input tlb_tag_reload
;
input ss_clock
;
input ss_reset
;
wire sel_mdat_mux;
/******************************************************************************/
wire mmstben_reg;
Mflipflop_r_1 mmstben_reg_1(mmstben_reg,mmstben,~ss_reset,ss_clock) ;
wire asi_wrtstb
= (asi_write & mmstben_aarb); /* indicates write strobe*/
/***** Compare strobe enable *************************/
assign c_en = ~(tlb_asi_act | tlb_tag_we | tlb_data_we |
tlb_update | sel_mdat_mux ) &
(mmu_en_e | io_mmu_en) |
tlb_flush ;
assign sel_mdat_mux = (asi_dcd6 & mmstben_aarb ) | tlb_tag_reload |
(asi_dcd4 & mmstben_aarb);
wire io_op;
Mflipflop_r_1 io_op_1(io_op,io_tlb_nxt,~ss_reset,ss_clock) ;
assign tlb_io_bit = io_tlb_nxt | tw_io_bit |
((flush_iopte | flush_ioall) & tlb_flush) ;
/***************************************************************************/
/***** Data Virtual Address decode logic, for MMU register load enables. */
/*** IFF the ASI=0x4 and a ST is decoded, then decode the correct enable. */
/*** First reset all the HOLD selects, to retain the current reg. */
/** ASI = 0x4 and the data VA[12:08] = 0x00. select MMU Cntl Reg. ***/
wire hld_mmu_cr = ~((asi_dcd4 & asi_wrtstb) & (!r_d_vaddr[12:08]));
/** ASI = 0x4 and the data VA[12:08] = 0x01. select CTPR ***/
wire hld_ctpr = ~((asi_dcd4 & asi_wrtstb) &
(!r_d_vaddr[12:09]) & (r_d_vaddr[08]));
/** ASI = 0x4 and the data VA[12:08] = 0x02. select Context Reg. ***/
wire hld_cxr = ~((asi_dcd4 & asi_wrtstb) &
(!r_d_vaddr[12:10]) & (r_d_vaddr[09])& (~r_d_vaddr[08]));
/** ASI = 0x4 and the data VA[12:08] = 0x13. select SFSR ***/
wire hld_sfsr = ~((asi_dcd4 & asi_wrtstb) &
(r_d_vaddr[12]) & (!r_d_vaddr[11:10]) &
(r_d_vaddr[09]) & (r_d_vaddr[08]));
/** ASI = 0x4 and the data VA[12:08] = 0x03. select SFSR ***/
wire rd_sfsr = ((asi_dcd4 & mmreg_rd_asi) &
(!r_d_vaddr[12:10]) & (r_d_vaddr[09]) & (r_d_vaddr[08]));
/** ASI = 0x4 and the data VA[12:08] = 0x14. select SFAR ***/
wire hld_sfar = ~((asi_dcd4 & asi_wrtstb) &
(r_d_vaddr[12]) & (~r_d_vaddr[11]) &
(r_d_vaddr[10]) & (!r_d_vaddr[09:08]));
/** ASI = 0x4 and the data VA[12:08] = 0x10. select TLB Replc. Cntl ***/
wire hld_trcr = ~((asi_dcd4 & asi_wrtstb) &
(r_d_vaddr[12]) & (!r_d_vaddr[11:08]));
/*** ASI = 0x6 (TLB), the data VA[07:02] select which tag/PTE is read. ***/
assign dp_asi_dcd6 = asi_dcd6 & asi_write & mmstben_aarb ;
assign tlb_wrt_tag = (asi_dcd6 & asi_write & mmstben_aarb ) |
tlb_tag_we;
assign tlb_asel = ((~tlb_flush & mmu_asi_op) | tlb_asi_act | tlb_tag_we |
tlb_data_we | ~c_en);
/***************************************************************************/
endmodule /* va_mux*/
This page: |
Created: | Thu Aug 19 12:00:45 1999 |
| From: |
../../../sparc_v8/ssparc/mmu/m_mmu_cntl/rtl/rl_va_mux.v
|