.pin_go_standby		(pin_go_standby),	
			.go_standby		(go_standby),	
			.standby_dsbl_tlb	(standby_dsbl_tlb),	
			.pcic_idle		(pcic_idle),	
			.mm_lvl15_int_l		(mm_lvl15_int_l),
			.any_intrnl_int_l	(any_intrnl_int_l),
// needs to be hooked up to the bm_sel input pins when the sp_sel pins
// are removed.  Can't do this until the memif changes are installed by June.
// 
			.bm_sel			(w_bm_sel),
// Revision 2.0 adds for reset control in pcic (in interrupts)
			.input_reset_l			(input_reset_l),
			.iu_error			(iu_error),
			.pci_slave_mode			(pci_slave_mode),
			.raw_pci_rst_l			(pci_rst_pin_in_l),
			.sw_rst				(sw_rst),
			.en_sw_rst_nonwd		(en_sw_rst_nonwd),
			.en_pci_sw_rst			(en_pci_sw_rst)
                        );

/*  */
/*****************  MEMIF model  **************************************/


    rl_memif ssparc_memif(

//hooked up b_mem... instead of w_b_mem... 
            .b_memdata_out(b_memdata_out), 	// Data out to the Data Pads for DRAM.

            .b_mempar_out(memif_mempar),	// Parity out to the Parity pads for DRAM
            .mc_memaddr(memif_memaddr_out),		// Memory address to Out pads for DRAM.

// falcon address bus connects here later
                .mc_memaddr_in(pcic_ab_out[11:0]),
                .am_gnt_l(w_am_gnt_l),
		.afx_rst_page_vld (afx_rst_page_vld),
                .am_gnt_l_oen(am_gnt_l_oen),
                .cas_cyc(w_cas_cyc),
                .valid_l(w_valid_l),
                .am_cstb_l(am_cstb_l),
                .am_read(am_read),
                .am_wm(am_wm),
              //  .falcon_exists(1'b1),
                .mm_sbae_0(mm_sbae_0),
                .prom_p_reply(prom_p_reply),
 
            .mc_ras_l(w_mc_ras_l),		// 8 RASes to Out pads for DRAM.
            .mc_cas_l(w_mc_cas_l), 		// 4 CASes to Out pads for DRAM
            .mc_moe_l(w_mc_moe_l),		// The OE to Out pads for DRAM. 
            .mc_mwe_l(w_mc_mwe_l),		// The WE to Out pads for DRAM.
            .simm32_sel(w_simm32_sel),		// if 1, for double density simms 
            .dp_ben(memif_mem_oen), 		// External Tri-enable to IO-pad Control.
            .mc_mstb_l(mc_mstb_l),		// Data-ready Strobe to MMU.
            .mc_mbsy(mc_mbsy),			// Memory logic busy sig to MMU
            .mc_caddr_hld(mc_caddr_hld), 	// Hold low addr bits. To MMU
            .dp_perr(dp_perr),  		// Parity-Error condition bits to IU.
            .dp_perr_buf(dp_perr_buf),  		// Parity-Error buffered version.
            .mc_mdata0(misc[31:0]), 		// Write Lo-word to internal dat_bus
            .rl_memif_scan_out (), 

//hooked up b_mem... instead of w_b_mem... 
            .b_memdata_in(b_memdata_in),  	// Data in from Data Pads for DRAM.

            .b_mempar_in(w_b_mempar_in),   	// Parity in from the Parity pads for DRAM. 
            .mm_pa_a(mm_pa[28:12]),		// Phys-addr 27:12 from MMU
            .mm_pa_b(mm_pa[2:0]), 		// Phys-addr 02:00 from MMU.
            .mm_caddr(mm_caddr[11:03]),		// Phys-addr 11:03 (latched) from MMU.
            .mm_issue_req(mm_issue_req),	// Valid-request from MMU
            .mm_issue_req2(mm_issue_req2),	// same as mm_issue_req
            .mm_mreq(mm_mreq),			// Mem cyc-req from MMU.
            .mm_page(mm_page), 			// Page mode request from MMU.
//            .mm_page_abort(mm_page_abort),	// Page mode abort request from mmu
            .mc_mdata_en0(mc_mdata_en0),	// Tri_enable, Wr Lo_word, mmu
            .mm_rf_cntl (mm_rfr_cntl), 		//Refr-rate select from MMU.
            .mm_oddmpar(mm_oddpar), 		// Select odd/even parity. MMU.
            .mm_parity_en(mm_parity_en), 	// parity enable. From MMU.
//IIep 2.0: add pcic_afxm_db_oen input for dma read parity checking -rdv
	    .pcic_afxm_db_oen(pcic_afxm_db_oen),
            .mc_mdata_in(misc[31:0]), 		// In from internal data bus
            .rl_memif_scan_in (), 
            .ss_scan_mode (ss_scan_mode),
	    .sp_sel(w_sp_sel),
            .ss_reset(reset),
            .ss_clock(ss_clock),

	    .mc_refresh(mc_refresh), 		//to mmu ,D ram refresh on
	    .mc_cfb_data(cache_fill[63:0]),	//Bypass data to cache fill bu
	    .precharge_early_0(precharge_early_0),  // to memif, early precharge for bank0
	    .precharge_early_1(precharge_early_1),  // to memif, early precharge for bank1
	    .pdm_ready(memif_idle),
	    .rfr_clock(rfr_clock),		// from clk_cntl, refresh clock
	    .rfr_late(rfr_late),		// from clk_cntl, the anti-phase clock
	    .mm_misc2cf(mm_misc2cf),		// select to mux misc to $ fill
	    .mm_2nd_wd(mm_2nd_wd),		// pack d-word from misc to $ fill
        .mm_fb_req (mm_fb_req),                 // from mmu,FB memory request
        .mm_fb_size (mm_fb_size),               // from mmu,FB request size
        .mm_fb_page (mm_fb_page),               // from mmu,FB request pg_md
        .gclk_1st_phase (gclk_1st_phase),
        .aen (w_aen),       		        // address enable to frame buffer
        .s_reply (w_s_reply),               	// output to fb
        .p_reply (w_p_reply),               	// input from fb
	.pcic_p_reply (pcic_p_reply),		// input from pcic
        .ab (memif_ab_out),               	// input from fb
	.ab_in (pcic_ab_out[14:12]),
        .p_reply_dec (p_reply_dec),               	// input from fb
        .afx_to (mc_afx_to),               	// output to mmu
        .mm_mem_dbg (mm_mem_dbg),               	// input from fb
	    .mm_issue_req_early(mm_issue_req_early)	// mmu to hold off refresh
            );

    // Cache controller block

    rl_cc cc (
	.little_endian		(little_endian),   //from Miu
        .hold_fetch_f_l		(hold_fetch_f_l),
        .sel_last_gen		(sel_last_gen),
        .sel_recirc		(sel_recirc),
	.ld_op_d		(ld_op_d),
	.st_op_d		(st_op_d),
        .ic_force_ifill_g 	(ic_force_ifill_g),
        .mm_cache_stat 		(mm_cache_stat),
	.fp_dout_e		(fp_dout_e[63:0]),
        .iu_store_data          (iu_store_data[31:0]),
        .select_IU_DOUT       	(select_IU_DOUT),
        .select_FP_DOUT       	(select_FP_DOUT),
        .sel_ldstb_1          	(sel_ldstb_1),
	.dcc_idle		(dcc_idle),
	.misc_out		(misc[31:0]),
	.ic_ibus		(ic_ibus[63:0]),
	.it_dout_f		(it_dout_f[`it_msb:0]),
	.it_cntx_out		(it_cntx_out[7:0]),
	.it_val_f		(it_val_f),
	.mm_icdaten		(mm_icdaten),
	.mm_fs_lvl		(mm_fs_lvl[1:0]),
	.it_lvl_in		(it_lvl_in[1:0]),
	.it_lvl_out		(it_lvl_out[1:0]),
	.ic_lvl_f		(ic_lvl_f[1:0]),
	.ic_sup_only_f		(ic_sup_only_f),
	.it_acc_out		(it_acc_out),
	.dt_cntx_in		(dt_cntx_in[7:0]),
	.it_cntx_in		(it_cntx_in[7:0]),
	.cxr			(cxr[7:0]),
	.i_dva_req		(i_dva_req),
	.sgnd_ld_e		(sgnd_ld_e),
	.mm_dct_daten		(mm_dct_daten),
	.standby_req		(standby_req),
	.ic_standby_f		(ic_standby_f),
	.dc_standby_w		(dc_standby_w),
	.dt_acc_out		(dt_acc_out),
   	.dt_val_w		(dt_val_w),
	.dva_w_2		(dva_w_2),
	.invalid_wb_entry	(invalid_wb_entry),
    	.dt_dout_w		(dt_dout_w[`dt_msb:0]),
	.nforce_dva_f		(nforce_dva_f),
	.ic_hld			(ic_hld[1:0]),
	.dc_hld			(dc_hld[1:0]),
	.enbl_fetch		(enbl_fetch),
	.iu_asi_e		(iu_asi_e[5:0]),//from iu, asi fields in e stage
	.dc_dva_e		(dc_dva_e[`dc_msb:3]),//from iu, dc virtual address
	.dwait_w 		(dwait_w),	//to iu,dc request iu to wait in W stage for cache filled
	.dwait_w_for_flush 	(dwait_w_for_flush),//to iu, for flush hold only (timing fix).
	.enbl_itag_match_f	(enbl_itag_match_f),//from ic,qualify it_hit_f
	.iwait_f		(iwait_f),	//to iu,ic request iu to wait in W stage for cache filled
        .ic_miss_or_part        (ic_miss_or_part),
        .ic_miss_and_part       (ic_miss_and_part),
        .ic_miss_sustain        (ic_miss_sustain), //to mmu,asserted 1 cycle after ic_miss 
						// when mmu assert mm_istate_avail
	.imiss_in_progress      (imiss_in_progress),//to iu,asserted in the 2nd cycle of a ic miss,till the
					        // last fill write cycle( for cached filled) or the bypass
						//  cyc ( for non cached filled)
	.i_nfillp               (i_nfillp[4:3]),//to iu, address for fill write
    	.wb0_hold_lo		(wb0_hold_lo),  // to mmu, write buffer control
    	.wb1_hold_lo		(wb1_hold_lo),	// to mmu
    	.wb2_hold_lo		(wb2_hold_lo),	// to mmu
    	.wb3_hold_lo		(wb3_hold_lo),	// to mmu
    	.wb_1_sel		(wb_1_sel),	// to mmu, write buffer control
    	.wb_2_sel		(wb_2_sel),	// to mmu
    	.wb_3_sel		(wb_3_sel),	// to mmu
	.wb_valid		(wb_valid),	// to mmu, write buffer valid
	.dt_index3              (dt_index3),  	// iu_asi_e is context_flush or user flush
        .dt_index2              (dt_index2), 	// iu_asi_e is region, context or user flush
        .dt_index1              (dt_index1), 	// iu_asi_e is seg, region, cntxt, or user flush
        .dt_flush               (dt_flush),     // iu_asi_e is page, seg,region,cntxt,or user flush
        .dt_flush_user          (dt_flush_user),  //iu_asi_e is user flush
        .dt_flush_user_cntx     (dt_flush_user_cntx),  //iu_asi_e is user or context flush
        .it_index3              (it_index3), 	//iu_asi_e is context_flush or user flush
        .it_index2              (it_index2),	//iu_asi_e is region, context or user flush
        .it_index1              (it_index1),	//iu_asi_e is seg, region, cntxt, or user flush
        .it_flush               (it_flush),	//iu_asi_e is page, seg,region,cntxt,or user flush
        .it_flush_user          (it_flush_user),//iu_asi_e is user flush
        .it_flush_user_cntx     (it_flush_user_cntx),//iu_asi_e is user or context flush
   	.dt_cntx_out		(dt_cntx_out[7:0]),//lda 0xE read from cache tags
	.ic_power_down          (ic_power_down),// icache power down
	.dc_power_down          (dc_power_down),// dcache power down
	.dt_at			(dt_at[4:0]),
 	.it_acc_in		(it_acc_in),
 	.dt_acc_in		(dt_acc_in[4:0]),
	.dc_do			(dc_do[63:0]),	// to dc herbulator,D-cache data output bus
	.ld_iu			(ld_iu[31:0]),	// to iu, 32-bit data from herbulator
	.ld_fpu			(ld_fpu_w[63:0]),//to fpu, 64 bit data from herbulator
	.fpu_mem_e		(fpu_mem_e),	//from iu,ldf,stf,lddf,stdf,stfsr,&stfq in e stage
	.dt_hit			(dt_hit_w),	//from dcaches, dtag hit in w stage
	.ld_op_e		(ld_op_e),	//from iu,e stage load (exclude ldst and swap)
	.size_e			(size_e[1:0]),	//from iu, size of mem op in e stage
	.st_op_e		(st_op_e),	//from iu,e stage store
	.cache_fill		(cache_fill[63:0]),//from memif, cache fill data from dram
	.dc_di			(dc_di[63:0]),	//to dcache,(fill_write_e)?cache_fill:iu_dout
	.dc_shold (dc_shold),			// to iu, wrbuffer full
	.it_val_in (it_val_in),		// to cache
	.ic_wle   (ic_wle),			// icache write enable
	.ic_be   (ic_be[1:0]),			// icache bypass enable
	.iu_bytemarks   (iu_bytemarks[3:0]),	// from iu, iu bytemarks
	.iu_dva_e        (iu_dva_e_dc[31:0]), 	// from iu, data virtualaddress in e
	.flush_op_e 	(iu_iflush_e),		// from iu, IFlush op in e
	.iu_iva_g        (iu_iva_g[13:3]), 	// from iu, inst virtual address in g
	.icache_adr      (icache_adr[31:14]), 	// from iu, inst virtual address in g
	.dc_wle        (dc_wle),		// to dcache, write enable
	.dc_be        (dc_be[7:0]),			// to dcache, bypass enable
	.dc_dtv_din        (dc_dtv_din),	
	.dp_perr	(dp_perr[1:0]),		// from memif, data parity error for I$cntrl
	.dp_perr_buf	(dp_perr_buf[1:0]),	// from memif, data parity error for D$cntrl
	.ic_perr_f	(ic_perr_f[1:0]),
	.start_itag_inv	(start_itag_inv),
	.ic_idle	(ic_idle),
	.misc_in (misc[31:0]),			// miscellaneous bus
	.dc_wrtbuf (misc[31:0]),		// write buffer output to misc bus
	.dc_tagasi_bus (misc[31:0]),		// ld tag asi path to IU thru misc bus
	.iu_pipe_hold_ic (pipe_hold4ic),	// iu pipe hold for I$
	.iu_pipe_hold_dc (pipe_hold4dc),	// iu pipe hold for D$
	.iu_pipe_hold_dc_l (pipe_hold4dc_l[1:0]),	// iu pipe hold for D$, inverted
	.fast_hld_terms (fast_hld_terms),	// subset of iu pipe hold for D$.
	.iu_in_trap (iu_in_trap),		// from iu, trap
	.IU_in_trap4dc (IU_in_trap4dc),		// a copy special for the DC
	.mm_dabort (mm_dabort),			// from mmu,abort the d cache mem op
	.mm_dcstben (mm_dcstben),		// from mmu,assert stb_en
	.mm_dcdaten_in (mm_dcdaten_in),		// from mmu,strobe of 0 word of write buffer to misc
	.mm_wbstb (mm_wbstb),	 		// from mmu,strobe of 0 word of write buffer to misc
	.mm_wbsel1 (mm_wbsel1), 		// from mmu,strobe of 1 word of write buffer to misc
	.mm_dcache_enbl (mm_dcache_enbl),	// from mmu,enable d cache
	.mm_dstat_avail (mm_dstat_avail),	// from mmu, acknowlege to dmiss
	.enbl_dtag_match_w (enbl_dtag_match_w),	// from mmu qualify dt_hit_w,asserted in in ld_op_w/st_op_w
	.dc_miss_or_part (dc_miss_or_part),	// Part 1 of timing fix 
	.dc_miss_and_part (dc_miss_and_part),	// Part 2 of timing fix 
	.dc_miss_sustain (dc_miss_sustain),	// asserted 1 cycle after dc_miss is active. 
						// mm_dstate_avail
	.mm_icstben (mm_icstben),		//from mmu,assert stb_en for ic to do non mem xaxtion
	.mm_iabort (mm_iabort),			//from mmu, memory op abort
	.icstben_asi (icstben_asi),		//from mmu icstben for asi operation
	.dt_be		(dt_be),		//to dtag, write enable
	.dt_be_vb	(dt_be_vb),		//to dtag, write valid bit
	.it_be_vb	(it_be_vb),
	.it_be		(it_be),
	.it_hit_f	(it_hit_f),		//itag hit in f stage
	.it_hit_f_mmu	(it_hit_f_mmu),		//to mmu (moved form Mhold logic)
        .mm_istat_avail (mm_istat_avail),	//from mmu,xlation done, cache state available.ack ic miss
        .mm_icache_enbl (mm_icache_enbl),	//from mmu, enable icache
	.it_din		(it_din[31:`log2_icachesize]), // itag data in
	.dt_din		(dt_din[31:`log2_dcachesize]), // dtag data in

	.ss_scan_mode (ss_scan_mode),
	.ss_dccntl_scan_in (),
	.ss_iccntl_scan_out (),
	.ss_clock_dc_cntl (ss_clock),			// supply main ss_clock
	.ss_clock_ic_cntl (ss_clock),			// supply main ss_clock
	.ss_reset (reset)
    ) ;

/**************************************************************************/
endmodule