/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)rl_cc.v 1.105 9/15/93
// Interconnect module for cache controllers - this is a layout block.
module rl_cc
(
little_endian,
hold_fetch_f_l,
sel_last_gen,
sel_recirc,
ld_op_d,
st_op_d,
ic_force_ifill_g,
mm_cache_stat,
fp_dout_e,
iu_store_data,
select_IU_DOUT,
select_FP_DOUT,
sel_ldstb_1,
dcc_idle,
mm_icdaten,
it_val_f,
it_cntx_out,
it_dout_f,
ic_ibus,
misc_out,
ic_sup_only_f,
dt_cntx_in,
it_cntx_in,
cxr,
i_dva_req,
sgnd_ld_e,
mm_dct_daten,
standby_req,
ic_standby_f,
dc_standby_w,
dt_val_w,
dva_w_2,
invalid_wb_entry,
dt_dout_w,
nforce_dva_f,
ic_hld,
dc_hld,
enbl_fetch,
dc_dva_e,
dt_acc_in,
dt_acc_out,
it_acc_out,
dwait_w,
dwait_w_for_flush,
iu_dva_e,
iu_asi_e,
mm_dcache_enbl,
mm_dstat_avail,
enbl_dtag_match_w,
dc_miss_or_part,
dc_miss_and_part,
dc_miss_sustain ,
mm_dcdaten_in,
mm_wbstb,
mm_wbsel1,
it_din,
dt_din,
mm_icache_enbl,
it_hit_f,
it_hit_f_mmu, // MMU's copy buffered in ic_cntl
mm_istat_avail,
iwait_f,
enbl_itag_match_f,
ic_miss_or_part,
ic_miss_and_part,
ic_miss_sustain,
imiss_in_progress,
i_nfillp,
wb0_hold_lo,
wb1_hold_lo,
wb2_hold_lo,
wb3_hold_lo,
wb_1_sel,
wb_2_sel,
wb_3_sel,
wb_valid,
it_index3,
it_index2,
it_index1,
it_flush,
it_flush_user,
it_flush_user_cntx,
dt_index3,
dt_index2,
dt_index1,
dt_flush,
dt_flush_user,
dt_flush_user_cntx,
dt_cntx_out,
ic_power_down,
dc_power_down,
dt_at,
it_acc_in,
mm_fs_lvl,
it_lvl_in,
it_lvl_out,
ic_lvl_f,
dc_shold,
it_val_in,
ic_wle,
it_be,
it_be_vb,
dt_be,
dt_be_vb,
ic_be,
iu_bytemarks,
flush_op_e,
iu_iva_g,
icache_adr,
dc_wle,
dc_be,
dc_dtv_din,
dp_perr,
dp_perr_buf,
ic_perr_f,
start_itag_inv,
ic_idle,
misc_in,
iu_pipe_hold_dc_l,
iu_pipe_hold_dc,
iu_pipe_hold_ic,
fast_hld_terms,
iu_in_trap,
IU_in_trap4dc,
mm_dabort,
mm_dcstben,
mm_icstben,
mm_iabort,
dc_wrtbuf,
dc_tagasi_bus,
icstben_asi,
dt_hit,
ld_op_e,
size_e,
st_op_e,
dc_do,
ld_iu,
ld_fpu,
fpu_mem_e,
cache_fill,
dc_di,
ss_scan_mode,
ss_dccntl_scan_in,
ss_iccntl_scan_out,
ss_clock_dc_cntl,
ss_clock_ic_cntl,
ss_reset
) ;
input little_endian
; // from iu to support little endian (if = 1)
output hold_fetch_f_l
;
input sel_last_gen
;
input sel_recirc
;
output ic_force_ifill_g
;
input mm_cache_stat
;
input [63:0] fp_dout_e
;
input [31:0] iu_store_data
;
input select_IU_DOUT
;
input select_FP_DOUT
;
input sel_ldstb_1
;
output dcc_idle
;
input mm_icdaten
;
input it_val_f
;
input [7:0] it_cntx_out
;
input [`it_msb:0] it_dout_f
;
input [63:0] ic_ibus
;
output ic_sup_only_f
;
input [7:0] cxr
;
output [7:0] dt_cntx_in
;
output [7:0] it_cntx_in
;
output i_dva_req
;
input ss_dccntl_scan_in
;
output ss_iccntl_scan_out
;
input sgnd_ld_e
;
input standby_req
;
output ic_standby_f
;
output dc_standby_w
;
output dva_w_2
;
output [1:0] ic_hld
;
output [1:0] dc_hld
;
input enbl_fetch
;
output [`dc_msb:3] dc_dva_e
;
output [31:`log2_icachesize] it_din
;
output [31:`log2_dcachesize] dt_din
;
output imiss_in_progress
;
output [4:3] i_nfillp
;
input mm_icache_enbl
;
input it_hit_f
;
output it_hit_f_mmu
;
input mm_istat_avail
;
output iwait_f
;
output enbl_itag_match_f
;
output ic_miss_or_part
;
output ic_miss_and_part
;
output ic_miss_sustain
;
output wb0_hold_lo
;
output wb1_hold_lo
;
output wb2_hold_lo
;
output wb3_hold_lo
;
output wb_1_sel
;
output wb_2_sel
;
output wb_3_sel
;
input [63:0] dc_do
;
output [31:0] ld_iu
;
output [63:0] ld_fpu
;
input fpu_mem_e
;
input [1:0] size_e
;
input [5:0] iu_asi_e
;
output dwait_w
;
output dwait_w_for_flush
;
input dt_val_w
;
input [7:0] dt_cntx_out
;
output ic_power_down
;
output dc_power_down
;
input dt_hit
;
input [31:0] iu_dva_e
;
input ld_op_d
;
input st_op_d
;
input ld_op_e
;
input st_op_e
;
input [63:0] cache_fill
;
output [63:0] dc_di
;
output it_acc_in
;
input [1:0] mm_fs_lvl
;
output [1:0] it_lvl_in
;
input [1:0] it_lvl_out
;
output [1:0] ic_lvl_f
;
output [4:0] dt_acc_in
;
input [4:0] dt_acc_out
;
input it_acc_out
;
output it_index3
;
output it_index2
;
output it_index1
;
output it_flush
;
output it_flush_user
;
output it_flush_user_cntx
;
output dt_index3
;
output dt_index2
;
output dt_index1
;
output dt_flush
;
output dt_flush_user
;
output dt_flush_user_cntx
;
output [4:0] dt_at
;
input icstben_asi
;
output [31:0] dc_wrtbuf
;
output [31:0] dc_tagasi_bus
;
input mm_dct_daten
;
input iu_pipe_hold_dc
;
input [1:0] iu_pipe_hold_dc_l
;
input iu_pipe_hold_ic
;
input fast_hld_terms
;
input iu_in_trap
;
input IU_in_trap4dc
;
input mm_dabort
;
input mm_dcstben
;
input ss_scan_mode
;
input ss_clock_dc_cntl
;
input ss_clock_ic_cntl
;
input ss_reset
;
input mm_icstben
;
input mm_iabort
;
input mm_dcdaten_in
;
input mm_wbstb
;
input mm_wbsel1
;
input [31:0] misc_in
;
output [31:0] misc_out
;
input [1:0] dp_perr
;
input [1:0] dp_perr_buf
;
output [1:0] ic_perr_f
;
output start_itag_inv
;
output ic_idle
;
output dc_shold
;
output it_val_in
;
output ic_wle
;
output [1:0] ic_be
;
input [3:0] iu_bytemarks
;
input flush_op_e
;
input [13:3] iu_iva_g
;
input [31:14] icache_adr
;
output [7:0] dc_be
;
output invalid_wb_entry
;
output dc_wle
;
output dc_dtv_din
;
output it_be
;
output it_be_vb
;
output dt_be
;
output dt_be_vb
;
output [1:0] wb_valid
;
input [`dt_msb:0] dt_dout_w
;
input mm_dcache_enbl
;
input mm_dstat_avail
;
output enbl_dtag_match_w
;
output dc_miss_or_part
;
output dc_miss_and_part
;
output dc_miss_sustain
;
input nforce_dva_f
;
wire ic_miss
;
wire flush_ic_e
;
wire ss_dccntl_scan_out
;
rl_dc_cntl dc_cntl(
.little_endian (little_endian),
.dp_perr (dp_perr_buf[1:0]),
.fp_dout_e (fp_dout_e[63:0]),
.iu_store_data (iu_store_data[31:0]),
.select_IU_DOUT (select_IU_DOUT),
.select_FP_DOUT (select_FP_DOUT),
.sel_ldstb_1 (sel_ldstb_1),
.dcc_miss_idle (dcc_idle),
.dcc_nc_bypass (dcc_nc_bypass
),
.dt_cntx_in (dt_cntx_in[7:0]),
.cxr (cxr[7:0]),
.i_dva_req (i_dva_req),
.sgnd_ld_e (sgnd_ld_e),
.standby_req (standby_req),
.dc_standby_w (dc_standby_w),
.mm_dct_daten (mm_dct_daten),
.dt_val_w (dt_val_w),
.dc_hld (dc_hld[1:0]),
.invalid_wb_entry (invalid_wb_entry),
.dt_dout_w (dt_dout_w[`dt_msb:0]),
.flush_op_e (flush_op_e),
.nforce_dva_f (nforce_dva_f),
.dva_w_2 (dva_w_2),
.dwait_w (dwait_w),
.dwait_w_for_flush (dwait_w_for_flush),
.dc_dva_e (dc_dva_e),
.iu_asi_e (iu_asi_e),
.mm_dcdaten_in (mm_dcdaten_in),
.mm_wbstb (mm_wbstb),
.mm_wbsel1 (mm_wbsel1),
.mm_dcache_enbl (mm_dcache_enbl),
.mm_dstat_avail (mm_dstat_avail),
.enbl_dtag_match_w (enbl_dtag_match_w),
.dc_miss_or_part (dc_miss_or_part),
.dc_miss_and_part (dc_miss_and_part),
.ic_miss (ic_miss),
.dc_miss_sustain (dc_miss_sustain),
.dt_acc_in (dt_acc_in[4:0]),
.dt_acc_out (dt_acc_out[4:0]),
.wb0_hold_lo (wb0_hold_lo),
.wb1_hold_lo (wb1_hold_lo),
.wb2_hold_lo (wb2_hold_lo),
.wb3_hold_lo (wb3_hold_lo),
.wb_1_sel (wb_1_sel),
.wb_2_sel (wb_2_sel),
.wb_3_sel (wb_3_sel),
.wb_valid (wb_valid),
.it_index3_w (it_index3),
.it_index2_w (it_index2),
.it_index1_w (it_index1),
.it_flush_w (it_flush),
.it_flush_user_w (it_flush_user),
.it_flush_user_cntx_w (it_flush_user_cntx),
.ic_asi_load_cache_w (ic_asi_load_cache_w
),
.ic_asi_store_tag_e (ic_asi_store_tag_e
),
.ic_asi_store_cache_e (ic_asi_store_cache_e
),
.flush_ic_e (flush_ic_e),
//
.dt_index3_w (dt_index3),
.dt_index2_w (dt_index2),
.dt_index1_w (dt_index1),
.dt_flush_w_l (dt_flush),
.dt_flush_user_w (dt_flush_user),
.dt_flush_user_cntx_w (dt_flush_user_cntx),
.dt_cntx_out (dt_cntx_out),
.dc_power_down (dc_power_down),
.dt_at (dt_at[4:0]),
.dc_do (dc_do[63:0]),
.ld_iu (ld_iu[31:0]),
.ld_fpu (ld_fpu[63:0]),
.fpu_mem_e (fpu_mem_e),
.size_e (size_e[1:0]),
.dt_hit_w (dt_hit),
.iu_dva_e (iu_dva_e[31:0]),
.ld_op_d (ld_op_d),
.st_op_d (st_op_d),
.ld_op_e (ld_op_e),
.st_op_e (st_op_e),
.iu_bytemarks (iu_bytemarks[3:0]),
.fast_hld_terms (fast_hld_terms),
.fast_iu_held_l (iu_pipe_hold_dc_l[1]),
.iu_held (iu_pipe_hold_dc),
.iu_held_for_dc_be (iu_pipe_hold_dc),
.iu_held_l (iu_pipe_hold_dc_l[0]),
.iu_in_trap (IU_in_trap4dc),
.mm_dabort (mm_dabort),
.mm_dcstben (mm_dcstben),
.dc_shold (dc_shold),
.wrtbuf (dc_wrtbuf[31:0]),
.dc_tagasi_bus (dc_tagasi_bus[31:0]),
.cached (mm_cache_stat),
.misc_in (misc_in[3:1]),
.dc_be (dc_be[7:0]),
.dc_wle (dc_wle),
.dc_dtv_din (dc_dtv_din),
.dt_be (dt_be),
.dt_be_vb (dt_be_vb),
.dc_di (dc_di[63:0]),
.cache_fill (cache_fill[63:0]),
.dt_din (dt_din[31:`log2_dcachesize]),
.ss_scan_in (ss_dccntl_scan_in),
.ss_scan_out (ss_dccntl_scan_out),
.ss_scan_mode (ss_scan_mode),
.ss_clock (ss_clock_dc_cntl),
.ss_reset (ss_reset)
);
wire [1:0] ic_be ;
rl_ic_cntl ic_cntl(
.hold_fetch_f_l (hold_fetch_f_l),
.sel_last_gen (sel_last_gen),
.sel_recirc (sel_recirc),
.ic_force_ifill_g (ic_force_ifill_g),
.mm_cache_stat (mm_cache_stat),
.dcc_nc_bypass (dcc_nc_bypass),
.dp_perr (dp_perr[1:0]),
.ic_perr_f (ic_perr_f[1:0]),
.start_itag_inv (start_itag_inv),
.ic_idle (ic_idle),
.ic_sup_only_f (ic_sup_only_f),
.it_acc_out (it_acc_out),
.cxr (cxr[7:0]),
.it_cntx_in (it_cntx_in[7:0]),
.standby_req (standby_req),
.ic_standby_f (ic_standby_f),
.dva_w_2 (dva_w_2),
.iu_in_trap (iu_in_trap),
.flush_ic_e (flush_ic_e),
.ic_asi_store_tag_e (ic_asi_store_tag_e),
.ic_asi_store_cache_e (ic_asi_store_cache_e),
.nforce_dva_f (nforce_dva_f),
.ic_hld (ic_hld[1:0]),
.enbl_fetch (enbl_fetch),
.ic_power_down (ic_power_down),
.it_acc_in (it_acc_in),
.mm_fs_lvl (mm_fs_lvl[1:0]),
.it_lvl_in (it_lvl_in[1:0]),
.it_lvl_out (it_lvl_out[1:0]),
.ic_lvl_f (ic_lvl_f[1:0]),
.iu_iva_g (iu_iva_g[13:3]),
.icache_adr (icache_adr[31:14]),
.iu_held (iu_pipe_hold_ic),
.mm_icstben (mm_icstben),
.icstben_asi (icstben_asi),
.mm_iabort (mm_iabort),
.misc_in (misc_in[31:0]),
.misc_out (misc_out[31:0]),
.ic_ibus (ic_ibus[63:0]),
.it_dout_f (it_dout_f[`it_msb:0]),
.it_cntx_out (it_cntx_out[7:0]),
.it_val_f (it_val_f),
.ic_asi_load_cache_w (ic_asi_load_cache_w),
.mm_icdaten (mm_icdaten),
.ic_wle (ic_wle),
.ic_be (ic_be[1:0]),
.it_be (it_be),
.it_be_vb (it_be_vb),
.it_val_in (it_val_in),
.it_din (it_din[31:`log2_icachesize]),
.mm_icache_enbl (mm_icache_enbl),
.it_hit_f (it_hit_f),
.it_hit_f_mmu (it_hit_f_mmu),
.mm_istat_avail (mm_istat_avail),
.iwait_f (iwait_f),
.enbl_itag_match_f (enbl_itag_match_f),
.ic_miss (ic_miss),
.ic_miss_or_part (ic_miss_or_part),
.ic_miss_and_part (ic_miss_and_part),
.ic_miss_sustain (ic_miss_sustain),
.imiss_in_progress (imiss_in_progress),
.i_nfillp (i_nfillp[4:3]),
.ss_scan_in (ss_dccntl_scan_out),
.ss_scan_out (ss_iccntl_scan_out),
.ss_scan_mode (ss_scan_mode),
.ss_reset (ss_reset),
.ss_clock (ss_clock_ic_cntl)
);
// Added spare cells
spares rl_cc_spares ();
endmodule
This page: |
Created: | Thu Aug 19 12:00:27 1999 |
| From: |
../../../sparc_v8/ssparc/cc/rtl/rl_cc.v
|