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/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)tbr.v
***
****************************************************************************
****************************************************************************/
// @(#)tbr.v	1.1 4/7/92
// tbr.v
/*
	This file describes the TBR register
*/



module Mtbr (tbrm,
	trapcode, result,
	TRAP, hld_tba, hld_tt, n_hld_tt_scan,
	ss_clock, hold
	);


// OUTPUTS

output [31:4] tbrm;		// master latched tbr

// INPUTS

input [7:0] trapcode;		// encoded trap type
input [31:0] result;		// source of WRTBR data

// CONTROL

input TRAP;			// contrl to write TT
input hld_tba;			// tbr hold control
input hld_tt;			// TT hold control
input n_hld_tt_scan;		// not TT hold and not scan_mode

// SCAN

//input y_scan;			// lsb from Y register (scan_mode)
//output tbr_scan;		// msb to DPC (scan_mode)

// MISC

input ss_clock;
input hold;
// input scan_mode;


	// TBR MUXs

	wire [31:12] tbr_wr = result[31:12];

	wire [11:4] tbr_unwr;

	// hold is now a feedback type
	// mux defaults to loading from trapcode

    // Expanded macro begin.
    // cmux2d(tbr_unwr_mux, 8,  tbr_unwr,  		tbrm[11:4], 	hld_tt,  		trapcode, 	n_hld_tt_scan)
    function [8:1] tbr_unwr_mux ;
        input [8:1] in0_fn ;
        input s0_fn ;
        input [8:1] in1_fn ;
        input s1_fn ;
        reg [8:1] out_fn ;
        begin
            case ({	n_hld_tt_scan, 	hld_tt}) /* synopsys parallel_case */
                2'b01:         out_fn = in0_fn;
                2'b10: out_fn = in1_fn;
                default: out_fn = 65'hx;
            endcase
            tbr_unwr_mux = out_fn ;
        end
    endfunction
    assign  tbr_unwr = tbr_unwr_mux( 		tbrm[11:4], 	hld_tt,  		trapcode, 	n_hld_tt_scan) ;
    // synopsys translate_off
    always @ (posedge(~Mclocks.clock))
    #1 if ((	n_hld_tt_scan+	hld_tt !== 1) & `SS_SCOPE.input_reset_l &
    ~Mtask.trace.ppr & ~(	n_hld_tt_scan^	hld_tt===1'bx)) begin
    $display("### %m.tbr_unwr_mux: CMUX2D select error!\n");
    $display("	n_hld_tt_scan,	hld_tt=%0d%0d\n", 	n_hld_tt_scan,	hld_tt);
    Mclocks.warning_count = Mclocks.warning_count + 1;
end
 // synopsys translate_on
 // Expanded macro end.


	// Sorry for kludging around the next two registers.
	// I can clean it back up when I have better register macros.

	// TBA

	wire [31:12] tbam;	// writeable part of the TBR
	wire [19:0] tbam_wire;	// FF macros are stupid
	wire [19:0] tbr_wr_wire = tbr_wr[31:12];	// FF macros are stupid
	Mflipflop_20 tba_master_20( tbam_wire, tbr_wr_wire, ss_clock, 		(hold | hld_tba)) ;
	assign tbam[31:12] = tbam_wire[19:0];	// FF macros are stupid
	
	// TT

	wire [11:4] ttm;	// TT part of TBR
	wire [7:0] ttm_wire;	// FF macros are stupid
	wire [7:0] tbr_unwr_wire = tbr_unwr[11:4];	// FF macros are stupid
	Mflipflop_8 tt_master_8( ttm_wire, tbr_unwr_wire, ss_clock, 		(hold | hld_tt)) ;
	assign ttm[11:4] = ttm_wire[7:0];	// FF macros are stupid

	// TBR

	wire [31:4] tbrm = {tbam, ttm};

	// SCAN

//	wire tbr_scan = tbrm[4];

endmodule