wire [3:0] alu_cc_nextdup = {ccN, ccZ, ccV, ccC};

	wire [3:0] alu_cc = {alu_cc_nextdup[3:2], nectccV, nextccC};

	assign high_2 = big_alu_out[33:32];
	wire high_2_1 = high_2[1];
	assign alu_out = big_alu_out[31:0];




// BARREL SHIFTER

	wire [31:0] shift_out;

	bsr shifter (shift_out,
		alu_s1sm, alu_s2i_cnt, shift_left, arith_shift,
		~shift_left, arith_shift, shift_left, ~shift_left);

//	Mshift shifter (shift_out,
//		alu_s1sm, shift_cnt, shift_left, arith_shift);



// ALU / SHIFTER MUX

	wire resultm_sc_mux_sdin;
	wire [31:0] ones_32 = 32'hffffffff;	// simplify mux argument
	wire [31:0] neg_idivovf_result = 32'h80000000;
	wire [31:0] pos_idivovf_result = 32'h7fffffff;

    // Expanded macro begin.
    // cmux5d(alu_shift_mux, 32,  alu_shift, 		alu_out, 	rs_from_alu, 		shift_out, 	rs_from_sh, 		ones_32, 	rs_from_else, 		neg_idivovf_result,  force_neg, 		pos_idivovf_result,  force_pos)
    function [32:1] alu_shift_mux ;
        input [32:1] in0_fn ;
        input s0_fn ;
        input [32:1] in1_fn ;
        input s1_fn ;
        input [32:1] in2_fn ;
        input s2_fn ;
        input [32:1] in3_fn ;
        input s3_fn ;
        input [32:1] in4_fn ;
        input s4_fn ;
        reg [32:1] out_fn ;
        begin
            case ({ force_pos,  force_neg, 	rs_from_else, 	rs_from_sh, 	rs_from_alu}) /* synopsys parallel_case */
                5'b00001:       out_fn = in0_fn ;
                5'b00010: out_fn = in1_fn ;
                5'b00100:       out_fn = in2_fn ;
                5'b01000: out_fn = in3_fn ;
                5'b10000:       out_fn = in4_fn ;
                default:        out_fn = 65'hx;
            endcase
            alu_shift_mux = out_fn ;
        end
    endfunction
    assign  alu_shift = alu_shift_mux(		alu_out, 	rs_from_alu, 		shift_out, 	rs_from_sh, 		ones_32, 	rs_from_else, 		neg_idivovf_result,  force_neg, 		pos_idivovf_result,  force_pos) ;
    // synopsys translate_off
    always @ (posedge(~Mclocks.clock))
    #1 if (( force_pos+ force_neg+	rs_from_else+	rs_from_sh+	rs_from_alu !== 1) & `SS_SCOPE.input_reset_l &
    ~Mtask.trace.ppr & ~( force_pos+ force_neg+	rs_from_else+	rs_from_sh^	rs_from_alu===1'bx)) begin
    $display("### %m.alu_shift_mux: CMUX5D select error!\n");
    $display(" force_pos, force_neg,	rs_from_else,	rs_from_sh,	rs_from_alu=%0d%0d%0d%0d%0d\n",  force_pos, force_neg,	rs_from_else,	rs_from_sh,	rs_from_alu);
    Mclocks.warning_count = Mclocks.warning_count + 1;
end
        // synopsys translate_on
        // Expanded macro end.


	assign alu_shift_dc = alu_shift;


// POST ALU SHIFTER FOR IMUL AND IDIV

	wire [31:0] alu_fresult;

    // Expanded macro begin.
    // cmux2d(alu_fresult_mux, 32, alu_fresult,  		alu_shift,  sel_sll1_divalu_l,  		({W_alushift_out[30:0],idiv_shiftin_low}),  		sel_sll1_divalu)
    function [32:1] alu_fresult_mux ;
        input [32:1] in0_fn ;
        input s0_fn ;
        input [32:1] in1_fn ;
        input s1_fn ;
        reg [32:1] out_fn ;
        begin
            case ({ 		sel_sll1_divalu,  sel_sll1_divalu_l}) /* synopsys parallel_case */
                2'b01:         out_fn = in0_fn;
                2'b10: out_fn = in1_fn;
                default: out_fn = 65'hx;
            endcase
            alu_fresult_mux = out_fn ;
        end
    endfunction
    assign alu_fresult = alu_fresult_mux( 		alu_shift,  sel_sll1_divalu_l,  		({W_alushift_out[30:0],idiv_shiftin_low}),  		sel_sll1_divalu) ;
    // synopsys translate_off
    always @ (posedge(~Mclocks.clock))
    #1 if (( 		sel_sll1_divalu+ sel_sll1_divalu_l !== 1) & `SS_SCOPE.input_reset_l &
    ~Mtask.trace.ppr & ~( 		sel_sll1_divalu^ sel_sll1_divalu_l===1'bx)) begin
    $display("### %m.alu_fresult_mux: CMUX2D select error!\n");
    $display(" 		sel_sll1_divalu, sel_sll1_divalu_l=%0d%0d\n",  		sel_sll1_divalu, sel_sll1_divalu_l);
    Mclocks.warning_count = Mclocks.warning_count + 1;
end
 // synopsys translate_on
 // Expanded macro end.


// RESULT REGISTER

	// resultm used to be wire-ored with the special mux

	Mflipflop_32 result_master_32( W_alushift_out, alu_fresult, 		ss_clock, hold_Wreg_real) ;

	Mflipflop_2 result_high2_reg_2(result_high2,high_2,ss_clock,hold_Wreg_real) ;


// PC and SPECIAL REGISTER MUX

        wire [31:0] resultm;
        wire [31:0] psrm;
        wire [31:0] ym;
        wire [2:0] ym_lo3 = ym[2:0];

	// simplify mux arguments

	wire [31:0] pcspec_wim = {24'b0, wimm};
	wire [31:0] pcspec_tbrm = {tbrm, 4'b0};

    // Expanded macro begin.
    // cmux7d(pcspec_mux, 32,  resultm, 		({tpc, 2'b0}), 	rdtpcm_sm, 		({wpc, 2'b0}), 	e_jmpcallm_sm, 		psrm, 		e_rdpsrm_sm, 		pcspec_wim, 	e_rdwimm_sm, 		ym, 		e_rdym_sm, 		pcspec_tbrm, 	e_rdtbrm_sm, 		W_alushift_out, 	sel_pcspec_l_sm)
    function [32:1] pcspec_mux ;
        input [32:1] in0_fn ;
        input s0_fn ;
        input [32:1] in1_fn ;
        input s1_fn ;
        input [32:1] in2_fn ;
        input s2_fn ;
        input [32:1] in3_fn ;
        input s3_fn ;
        input [32:1] in4_fn ;
        input s4_fn ;
        input [32:1] in5_fn ;
        input s5_fn ;
        input [32:1] in6_fn ;
        input s6_fn ;
        reg [32:1] out_fn ;
        begin
            case ({	sel_pcspec_l_sm, 	e_rdtbrm_sm, 		e_rdym_sm, 	e_rdwimm_sm, 		e_rdpsrm_sm, 	e_jmpcallm_sm, 	rdtpcm_sm}) /* synopsys parallel_case */
                7'b0000001:     out_fn = in0_fn ;
                7'b0000010: out_fn = in1_fn ;
                7'b0000100:     out_fn = in2_fn ;
                7'b0001000: out_fn = in3_fn ;
                7'b0010000:     out_fn = in4_fn ;
                7'b0100000: out_fn = in5_fn ;
                7'b1000000:     out_fn = in6_fn ;
                default:        out_fn = 65'hx;
            endcase
            pcspec_mux = out_fn ;
        end
    endfunction
    assign  resultm = pcspec_mux(		({tpc, 2'b0}), 	rdtpcm_sm, 		({wpc, 2'b0}), 	e_jmpcallm_sm, 		psrm, 		e_rdpsrm_sm, 		pcspec_wim,
    e_rdwimm_sm, 		ym, 		e_rdym_sm, 		pcspec_tbrm, 	e_rdtbrm_sm, 		W_alushift_out, 	sel_pcspec_l_sm) ;
    // synopsys translate_off
    always @ (posedge(~Mclocks.clock))
    #1 if ((	sel_pcspec_l_sm+	e_rdtbrm_sm+		e_rdym_sm+	e_rdwimm_sm+		e_rdpsrm_sm+	e_jmpcallm_sm+	rdtpcm_sm !== 1) & `SS_SCOPE.input_reset_l &
    ~Mtask.trace.ppr & ~(	sel_pcspec_l_sm+	e_rdtbrm_sm+		e_rdym_sm+	e_rdwimm_sm+		e_rdpsrm_sm+	e_jmpcallm_sm^	rdtpcm_sm===1'bx)) begin
    $display("### %m.pcspec_mux: CMUX7D select error!\n");
    $display("	sel_pcspec_l_sm,	e_rdtbrm_sm,		e_rdym_sm,	e_rdwimm_sm,		e_rdpsrm_sm,	e_jmpcallm_sm,	rdtpcm_sm=%0d%0d%0d%0d%0d%0d%0d\n", 	sel_pcspec_l_sm,	e_rdtbrm_sm,		e_rdym_sm,	e_rdwimm_sm,		e_rdpsrm_sm,	e_jmpcallm_sm,	rdtpcm_sm);
    Mclocks.warning_count = Mclocks.warning_count + 1;
end
        // synopsys translate_on
        // Expanded macro end.


// RESULT SLAVe

// Mux for alu/Shift or pc/special register (in W cycle)

	assign result = resultm;


/*
 * This logic used to be in pc.v in SUNTAN.  for SUNERGY, this
 * logic is here (for load align control) since the load address
 * is computed here.
 */
//	wire [1:0] which_byte_ = ~result[1:0];

// SCAN OUT

	wire result_scan = result[0];

// Special register instantiation
//---------------------------------------------------------------------------
// PSR MODULE



        Mpsr psr_mod (psrm, cwp, cwpm_, ncwpm_,
		ecwpm_, wcwpm1, cwpp1, cwpm1, wcwp,
		ccm, cc_next3, cc_next1,
                sm, little_endian, s, psm, ps, et, ef, pil,
                result,
                alu_cc, hold_cc, load_cc, write_cc, restore_cc,
                clret_sets_sm, setet_ps2s_sm, write_etps_sm, hold_ets_sm,
                s_into_ps_sm, hold_ps_sm,
                hld_pilefec,
                w_wrpsr_sm,  TRAP_sm,
                cwp_inc_sm, cwp_dec_sm, cwp_hold_sm, ecwp_next_sm,
		cwp_recirc,
                ss_clock, hold_Mexec1
        );

//---------------------------------------------------------------------------
// WIM MODULE


        Mwim wim_mod (wimm,
                result[7:0],
                hld_wim,
                ss_clock, hold_Mexec1);
 
//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
// TBR MODULE
 
 
        Mtbr tbr_mod (tbrm,
                trapcode, result,
                TRAP, hld_tba, hld_tt, n_hld_tt_scan,
                ss_clock, hold_Mexec1
        );
 
//---------------------------------------------------------------------------
// Y MODULE
 
        My y_mod (ym,
                result,
                n_ymsb,
                wr_y, wr_mulscc,
                hld_y,
                ss_clock, hold_Mexec1
                );
 
//---------------------------------------------------------------------------
// DCACHE INTERFACE - muxes
/*
 * Moved to D$
	Mdcacheif dcacheif(iu_dout,
		src3,
		fp_dout,
		select_FP_DOUT,
		sel_ldstb_1,
		select_IU_DOUT,
		ss_clock
	);
 */


// DISPLAY TASK

/* synopsys translate_off */
task disp;
begin
	$write("alu_s1m=%x FROM ", alu_s1m);
	if(alus1_setm || alus1_setm===1'bx)	$write("sethi_datam      ");
	if(alus1_datam || alus1_datam===1'bx)	$write("ld_iu    ");
//	if(alus1_rfm || alus1_rfm===1'bx)	$write("src1m            ");
//	if(alus1_b3m || alus1_b3m===1'bx)	$write("rfwrdatam(B3) ");
	if(alus1_b2m || alus1_b2m===1'bx)	$write("wrdatam(B2)      ");
	if(alus1_b1m || alus1_b1m===1'bx)	$write("resultm(B1)      ");
	$write("	alu_s2m=%x FROM ", alu_s2m);
	if(alus2_datam || alus2_datam===1'bx)	$write("ld_iu ");
//	if(alus2_im || alus2_im===1'bx)		$write("simm13m ");
//	if(alus2_rfm || alus2_rfm===1'bx)	$write("src2m ");
//	if(alus2_b3m || alus2_b3m===1'bx)	$write("rfwrdatam(B3) ");
	if(alus2_b2m || alus2_b2m===1'bx)	$write("wrdatam(B2) ");
	if(alus2_b1m || alus2_b1m===1'bx)	$write("resultm(B1) ");
	$display;

	$write("alu_s1sm=%x ", alu_s1sm);
	if(e_mulsm || e_mulsm===1'bx)	$write("(e_mulsm)");
	else				$write("         ");
	$write("		alu_s2im=%x ", alu_s2im);
//	if(alu_invertbm || alu_invertbm===1'bx) $write("(invertbm)");
	$display;

	if(alu_ADD || alu_ADD===1'bx)	$write("alu_ADD ");
	if(alu_AND || alu_AND===1'bx)	$write("alu_AND ");
	if(alu_XNOR || alu_XNOR===1'bx)	$write("alu_XNOR ");
	$write("carry_in=%x		", carry_in);
//	if(shift_pass)					$write("shift_PASS ");
//	else begin
//		if(shift_pass===1'bx)			$write("shift_PASS ");
//		if(shift_sra || shift_sra===1'bx)	$write("shift_SRA  ");
//		if(shift_srl || shift_srl===1'bx)	$write("shift_SRL  ");
//		if(shift_sll || shift_sll===1'bx)	$write("shift_SLL  ");
//	end
//	$display;

	$write("alu_out=%x ", alu_out);
	if(alu_cc[3] || alu_cc[3]===1'bx)	$write("N");
	else					$write(" ");
	if(alu_cc[2] || alu_cc[2]===1'bx)	$write("Z");
	else					$write(" ");
	if(alu_cc[1] || alu_cc[1]===1'bx)	$write("V");
	else					$write(" ");
	if(alu_cc[0] || alu_cc[0]===1'bx)	$write("C ");
	else					$write("  ");
//	if(alu_tagged | alu_tagged===1'bx)	$write("tagged");
//	else					$write("      ");
	$write("		shift_out=%x", shift_out);
	$display;

	$write("alu_shift=%x ", alu_shift);
	if(rs_from_sh | rs_from_sh===1'bx) $write("(rs_from_sh)");
	if(rs_from_alu | rs_from_alu===1'bx) $write("(rs_from_alu)");
	if(rs_from_else | rs_from_else===1'bx) $write("(rs_from_else)");
	$display;

	$write("resultm=%x FROM ", resultm);
	
	if(rdtpcm || rdtpcm===1'bx) $write("TPCm ");
	if(e_jmpcallm || e_jmpcallm===1'bx) $write("WPCm ");
	if(e_rdpsrm || e_rdpsrm===1'bx) $write("PSRm ");
	if(e_rdwimm || e_rdwimm===1'bx) $write("WIMm ");
	if(e_rdym || e_rdym===1'bx) $write("Ym ");
	if(e_rdtbrm || e_rdtbrm===1'bx) $write("TBRm ");
//	if(~rs_frm_alshm_ || rs_frm_alshm_===1'bx) $write("ALUm ");
	
	$display;

	$display("result=%x	wrdatam=%x", result, wrdatam);

	$display("---------------------------------------------------------------------------");

	#0 Mclocks.STOP = ~Mclocks.STOP;
end
endtask
/* synopsys translate_on */

endmodule



/*
 * moved to D$

module Mdcacheif(iu_dout,
	src3,
	fp_dout,
	select_FP_DOUT,
	sel_ldstb_1,
	select_IU_DOUT,
	ss_clock
	);

output [63:0] iu_dout;

//input [31:0] alu_shift;                // ditto. 
input [31:0] src3;
input [63:0] fp_dout;

input select_FP_DOUT;                   // use to select FP data for stores
input sel_ldstb_1;
input select_IU_DOUT;                   // use to select FP data for stores
input ss_clock;
//input hold;

//input ss_scan_mode;
//input dcacheif_scan_in;
//output dcacheif_scan_out;

//Forward Dec.

// SELECT BETWEEN IU AND FPU DATA
	wire [31:0] all1s = 32'hffffffff;
        wire [31:0] DOUT_even;
        CMUX3D(dout_select_even, 32, DOUT_even, 		src3, select_IU_DOUT, 		all1s, sel_ldstb_1, 		fp_dout[63:32], select_FP_DOUT)

	wire [31:0] DOUT_odd;
        CMUX3D(dout_select_odd, 32, DOUT_odd, 		src3, select_IU_DOUT, 		all1s, sel_ldstb_1, 		fp_dout[31:0], select_FP_DOUT)

	wire [63:0] iu_dout = {DOUT_even,DOUT_odd};

endmodule

 */

/*
	the Malucc module used to be here.  it is now
	in the file alu.v
 */