/******************************************************************************/ 
/*                                                                            */ 
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
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/******************************************************************************/ 
/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)wim.v
***
***
****************************************************************************
****************************************************************************/
// @(#)wim.v	1.3 4/8/92
// wim.v
//------------------------------------------------------------------------------
/*
	module describing the WIM register
*/



module Mwim (wimm,
	result,
	hld_wim,
	ss_clock, hold);

// OUTPUTS

output [7:0] wimm;		// master latched wim

// INPUTS

input [7:0] result;		// least significant 7 bits of result reg.
// input reset;

// CONTROL

input hld_wim;			// WIM clock hold

// SCAN MODE

//input tpc_scan;			// shift_in in scan mode (from TPC)
//output wim_scan;		// shift_out in scan mode (to Y reg)

// MISC		

input ss_clock;			// main clock
input hold;
// input scan_mode;

	wire [7:0] wim_in = result[7:0];

	wire [7:0] wimm;
	Mflipflop_8 wim_master_8( wimm, wim_in, ss_clock, 		(hold | hld_wim)) ;
	
endmodule