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/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)write_data.v
***
***  Description:
***    Implements the afx write data, includes little to big endian conversion.
*** 
****************************************************************************
****************************************************************************/


module write_data(	
		pcim_big_endian,	//big endian mode
		little_endian,		// processor little endian bit
		reset,			//reset
		clock,			//fifo clock
		db,			//AFX data bus (big endian)
		afx_write,		//afx_write signal latched
		write_l,		//valid data on afx data bus, active lo

		load_data_fifo,		//load fifo to pci write data
 		afx_write_data);		//data out

//  This module captures the AFX data bus for writes and also
//  converts from big-endian to little endian in the
//  connectivity.  (write_data will be little endian.)

	parameter WIDTH = 63;

input	pcim_big_endian;
input 	little_endian;
input 	reset;
input 	clock;
input	[WIDTH:0] db;
input	afx_write;
input	write_l;

output  load_data_fifo;
output [WIDTH:0] afx_write_data;


reg 	load_data_fifo;
wire [WIDTH:0] afx_write_data;
reg	write_del_l;

wire load_en = afx_write & ~write_del_l;

wire [63:0] db_mux = pcim_big_endian ? {db[31:0],db[63:32]} : 
		{db[7:0],db[15:8],db[23:16],
                db[31:24],db[39:32],db[47:40],db[55:48],db[63:56]};

REG64 reg0(afx_write_data,clock,load_en,db_mux);

always @(posedge clock)
begin
  
  write_del_l <= #1 write_l;

  load_data_fifo <= #1 (afx_write & ~write_del_l);

end

endmodule