/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
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/* obligations, and limitations governing use of the contents of this file. */
/* */
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/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
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/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)write_data.v
***
*** Description:
*** Implements the afx write data, includes little to big endian conversion.
***
****************************************************************************
****************************************************************************/
module write_data
(
pcim_big_endian, //big endian mode
little_endian, // processor little endian bit
reset, //reset
clock, //fifo clock
db, //AFX data bus (big endian)
afx_write, //afx_write signal latched
write_l, //valid data on afx data bus, active lo
load_data_fifo, //load fifo to pci write data
afx_write_data); //data out
// This module captures the AFX data bus for writes and also
// converts from big-endian to little endian in the
// connectivity. (write_data will be little endian.)
parameter WIDTH = 63;
input pcim_big_endian
;
input little_endian
;
input reset
;
input clock
;
input [WIDTH:0] db
;
input afx_write
;
input write_l
;
output load_data_fifo
;
output [WIDTH:0] afx_write_data
;
reg load_data_fifo;
wire [WIDTH:0] afx_write_data;
reg write_del_l
;
wire load_en
= afx_write & ~write_del_l;
wire [63:0] db_mux
= pcim_big_endian ? {db[31:0],db[63:32]} :
{db[7:0],db[15:8],db[23:16],
db[31:24],db[39:32],db[47:40],db[55:48],db[63:56]};
REG64 reg0(afx_write_data,clock,load_en,db_mux);
always @(posedge clock)
begin
write_del_l <= #1 write_l;
load_data_fifo <= #1 (afx_write & ~write_del_l);
end
endmodule
This page: |
Created: | Thu Aug 19 12:01:37 1999 |
| From: |
../../../sparc_v8/ssparc/pcic/afx_slave/rtl/write_data.v
|