/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
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/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
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/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)y.v
***
****************************************************************************
****************************************************************************/
// @(#)y.v 1.1 4/7/92
// y.v
/*
Description of the Y register
*/
module My
(ym,
result,
n_ymsb,
wr_y, wr_mulscc,
hld_y,
ss_clock, hold
);
// OUTPUTS
output [31:0] ym
; // Y register master
// INPUTS
input [31:0] result
; // input to Y register for writes
input n_ymsb
; // next Y msb for Shifts
// CONTROL
input wr_y
; // write result into y.
input wr_mulscc
; // write mulscc into y
//input scan_y; // Scan into y
//input clr_y; // clear y
// input e_mulsm; // muls in execute. needed to choose nmuls_add
input hld_y
; // clock hold for Y register
// SCAN
// input wim_scan; // shift_in in scan mode (from wim)
// output y_scan; // shift_out in scan mode (to tbr)
// MISC
input ss_clock
;
input hold
;
// FORWARD DECLARATION
wire [31:0] ym;
// MUX chooses between result (for WRY) and Y[31:1] (for MULScc)
wire [31:0] next_y
;
wire ymux_sdin
;
wire [31:0] ymux_in0
= {n_ymsb, ym[31:1]}; // simplify argument
/* remove as unnecessary
wire [31:0] ymux_in1 = {ymux_sdin, ym[31:1]}; // simplify argument
#ifdef REGWIRE_IS_WIRE
// Synopsys can't eat unknowns.
wire [31:0] ymux_in2 = {32'h0}; // simplify argument
#else
wire [31:0] ymux_in2 = {32'hx}; // simplify argument
#endif
// wire [31:0] ymux_in3 = {scan_mode, shift_y}; // simplify argument
*/
// MUX4(ymux,32, next_y, result, ymux_in0, ymux_in1, ymux_in2, ymux_in3)
// Expanded macro begin.
// cmux2d(ymux, 32, next_y, result, wr_y, ymux_in0, wr_mulscc)
function [32:1] ymux ;
input [32:1] in0_fn ;
input s0_fn ;
input [32:1] in1_fn ;
input s1_fn ;
reg [32:1] out_fn ;
begin
case ({ wr_mulscc, wr_y}) /* synopsys parallel_case */
2'b01: out_fn = in0_fn;
2'b10: out_fn = in1_fn;
default: out_fn = 65'hx;
endcase
ymux = out_fn ;
end
endfunction
assign next_y = ymux( result, wr_y, ymux_in0, wr_mulscc) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( wr_mulscc+ wr_y !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( wr_mulscc^ wr_y===1'bx)) begin
$display("### %m.ymux: CMUX2D select error!\n");
$display(" wr_mulscc, wr_y=%0d%0d\n", wr_mulscc, wr_y);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
// ymux_in1, scan_y,
// ymux_in2, clr_y)
// MaSTER LATCH
Mflipflop_32 ymaster_32( ym, next_y, ss_clock, (hold | hld_y)) ;
// (hold | hld_y) & ~(scan_y | clr_y))
// (hold | hld_y) & ~scan_mode)
// SCAN OUT
// wire y_scan = ym[0];
endmodule
This page: |
Created: | Thu Aug 19 12:01:34 1999 |
| From: |
../../../sparc_v8/ssparc/iu/Mexec/rtl/y.v
|