Title |
Issue
|
How
to Save Register Content During Spartan-XL Power-Down |
Q2 '99
|
XC9500XV
High-Performance 2.5V ISP CPLD |
Q2 '99
|
The
3.3V Spartan-XL FPGA Series Invades New Territory with High Speed and Low
Cost |
Q4 '98
|
Choosing
a 3.3V CPLD? "ARM" Yourself |
Q4 '98
|
Reducing
CPLD Power Consumption |
Q4 '98
|
Spartan
Series Takes the Lead with Low Power |
Q2 '98
|
Low
Power FPGA Achieves 400 MHz Performance |
Q2 '98
|
CMOS
I/O Characteristics |
Q2 '98
|
Using
Decoupling Capacitors in 3.3 V Systems |
Q1 '98
|
Xilinx
XC4000XL Power Calculation |
Q1 '98
|
Low
Voltage Planning |
Q3 '97
|
Programmable
Logic in Mixed Voltage Applications |
Q2 '97
|
FPGAs,
Power, and Packages |
Q2 '97
|
Power,
Package, and Performance: Trading Off Among the Three P's |
Q3 '96
|