Xilinx Introduces the CoolRunner XPLA3 Family! The CoolRunnerTM XPLA3 eXtended Programmable Logic Array family of CPLDs is targeted for low power applications that include portable, handheld, and power sensitive applications. Each member of the XPLA3 family includes Fast Zero PowerTM (FZP) design technology that combines low power AND high speed. With this design technique, the XPLA3 family offers true pin-to-pin speeds of 5.0 ns, while simultaneously delivering power that is  <100µA (standby) without the need for special "power down bits" that negatively affect device performance.   Learn more about CoolRunner's Fast Zero Power feature: PPTPDF

XPLA3 Family XPLA3 Features and Benefits

XPLA3 Architecture XPLA3 Software Tools

More Information

CoolRunner XPLA3 Family

XPLA3 Features and Benefits
 

Features	Benefits
Total CMOS architecture with FZP design technology	Lowest stand-by and total current consumption of any CPLD
32 to 384 macrocell device selections	Full range of densities
Fast pin to pin timing 32 M/C - 5 ns	Perfect fit for high speed systems
3.3 Volt operation with 5 Volt tolerant I/Os	Simplifies multivoltage system design
Full 36 by 48 PLA - Full Programmable AND / Programmable OR structure	Optimizes sharing and resource utilization (all product terms available)
Bus friendly I/O	Pull-up resistor for I/O termination
Multiple clocking options	Maximum clocking resources for design flexibility
Fast input registers	Supports direct high speed interface
VFM (Variable Function Mux) and Fold-back NANDs	Superior logic optimization and device fitting
Small, surface mount packages -  .8mm and .5mm ball pitch Chip Scale BGAs	Smallest footprint and board space savings
Advanced 5 metal layer process technology	Lowest Cost
Industrial and Commercial temperature ranges	Full Industrial temperature and operating range (2.7 to 3.6 Volt)

XPLA3 Architecture The XPLA3 architecture features a direct input register path, multiple clocks, JTAG programming, 5 volt tolerant I/Os and a full PLA structure. These enhancements deliver high speed coupled with the best flexible logic allocation which results in the ability to make design changes without changing pin-outs. The XPLA3 architecture includes a pool of 48 product terms that can be allocated to any macrocell in the logic block. This combination allows logic to be allocated efficiently throughout the logic block and support as many product terms as needed per macrocell. In addition, there is no speed penalty for using a variable number of product terms per macrocell.

XPLA3 Software Tools Software support for XPLA3 devices will be provided by Xilinx WebPOWERED software products which includes WebFITTERTM and WebPACKTM beginning the week of February 7, 2000. Both tools are free.  In addition, EDIF input for all major 3rd party software flows such as Cadence, Mentor, Viewlogic, Exemplar and Synopsys are supported.

More Information
 

XPLA3 Datasheets XPLA3 Application Notes XPLA3 Architecture Overview XPLA3 Press Release CoolRunner Customer Success Stories CoolRunner FAQs

WebPOWERED Solutions CPLD Software Solutions FAQs 3rd Party Programmer Support Xilinx at Work in MP3 Player XPLA2/Enhanced Family