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CPLD Applications 

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XC9500XL

Application Notes Ver. Date Size
pdf XAPP144: Designing CPLD Multi-voltage SystemsNew 1.1 02/00 60 KB
pdf XAPP141: In-System Programming Times for XC9500XL 1.0 4/99 18 KB
pdf XAPP115: Planning for High Speed XC9500XL Designs 1.0 9/98 110 KB
pdf XAPP114: Understanding XC9500XL CPLD Power 1.1 1/99 90 KB
pdf XAPP112: Designing With XC9500XL CPLDs 1.1 1/99 160 KB
pdf XAPP111: Using the XC9500XL Timing Model 1.2 1/99 100 KB
Application Brief Ver. Date Size
pdf XBRF017: XC9500XL Versus MAX 7000A Architecture Comparison 1.1 9/98 60 KB


XC9500

Application Notes Ver. Date Size
pdf XAPP137: Configuring Virtex FPGAs from Parallel EPROMs with a CPLD 1.0 3/99 90 KB
pdf XAPP113: Faster Erase Times for XC95216 and XC95108 Devices on HP 3070 Series Testers  1.0 7/98 30 KB
pdf XAPP110: XC9500 CPLD Power Sequencing 1.0 1/98 30 KB
pdf XAPP109: Hints, Tips and Tricks for using XABEL with Xilinx M1.5 Design and Implementation Tools 2.0 10/98 80 KB
pdf XAPP105: A CPLD VHDL Introduction 1.0 1/98 60 KB
pdf XAPP104: A Quick JTAG ISP Checklist 1.1 1/99 20 KB
pdf XAPP103: The Tagalyzer - A JTAG Boundary Scan Debug Tool 1.0 1/98 130 KB
pdf XAPP102: XC9500 Remote Field Upgrade
Associated PCInternet Link and UNIXInternet Link design files
1.0 1/98 80 KB
pdf XAPP078: XC9536 ISP Demo Board
Johnson Shift Counter VHDL CodeInternet Link
Johnson Shift Counter ABEL CodeInternet Link
VHDL Design FilesInternet Link
1.0 4/97 41 KB
pdf XAPP077: Metastability Considerations 1.0 1/97 23 KB
pdf XAPP076: Embedded Instrumentation Using XC9500 CPLDs 1.0 1/97 39 KB
pdf XAPP075: Using ABEL with Xilinx CPLDs 1.0 1/97 53 KB
pdf XAPP074: Pin Preassigning with XC9500 CPLDs 1.3 6/98 50 KB
pdf XAPP073: Designing with XC9500 CPLDs 1.3 1/98 70 KB
pdf XAPP071: Using the XC9500 Timing Model 1.0 1/97 47 KB
pdf XAPP070: Using In-System Programmability in Boundary-Scan Systems 1.1 7/97 42 KB
pdf XAPP069: Using the XC9500 JTAG Boundary-Scan Interface 2.0 2/98 122 KB
pdf XAPP068: In-System Programming Times 1.2 4/98 13 KB
pdf XAPP067: Using Serial Vector Format Files to Program XC9500 Devices In-System on Automatic Test Equipment and Third Party Tools 1.1 7/97 40 KB
pdf XAPP058: Xilinx In-System Programming Using an Embedded Microcontroller
Associated files are available for PCInternet Link, SolarisInternet Link, and HPInternet Link(files updated 6/99)
2.0 6/99 300 KB
Application Brief
pdf XBRF009: XC9500 Pin-Locking Capability and Benchmarks 1.3 1/97 47 KB


CoolRunner

Application Notes Ver. Date Size
pdf XAPP334: Utilizing XPLA3 Universal Control TermsNew 1.0 1/00 60 KB
pdf XAPP333: CoolRunner XPLA3 I2C Bus Controller ImplementationNew 1.0 1/00 190 KB
pdf XAPP332: PinLocking in CoolRunner XPLA3 CPLDsNew 1.0 1/00 80 KB
pdf XAPP328: Design of a MP3 Portable Player using a CoolRunner CPLDNew 1.1 12/99 450 KB
pdf XAPP327: Fitting Designs Efficiently Into CoolRunner CPLDsNew 1.0 11/99 260 KB
pdf XAPP316: Xilinx Project Navigator XST - XPLA Professional Design  Flow for CoolRunner CPLDs 1.0 9/99 170 KB
pdf XAPP315: Implementing an I2C Bus Controller in a CoolRunnerTM CPLD
Associated VHDLInternet Link design files 
1.0 10/99 150KB
pdf XAPP313: Achieving High Performance in a CoolRunnerTM XCR3960 1.0 10/99 160KB
pdf XAPP312: Differences In ABEL and PHDL 1.0 10/99 60 KB
pdf XAPP311: Five Volt Tolerance and PCI New 1.1 2/00 70 KB
pdf XAPP310: Power Up Reset Characteristics of CoolRunner CPLDs New 1.1 2/00 30 KB
pdf XAPP307: Terminating Unused I/O Pins in Xilinx XPLA1 and XPLA2 CoolRunner CPLDs New 1.1 2/00 30 KB
pdf XAPP302: Metastability Characteristics for CoolRunner CPLDs New 1.1 2/00 40 KB
pdf XAPP300: In-System programming (ISP) 4/97 80 KB
White Paper
pdf CoolRunner XPLA3 Architecture OverviewNew 1.0 1/00 200 KB
pdf The XPLATM Architecture 120 KB
Other Links
Users Manual for XPLA Professional
Schematic Capture Library


Tutorials New

Title Size
pdf Exemplar/ModelSim Tutorial for CPLDs 300 KB
pdf Mentor Schematic Design Tutorial 1 MB
pdf OrCAD/ModelSim Tutorial for CPLDs 200 KB
pdf Synopsys Design Compiler/FPGA Compiler/ModelSim Tutorial for CPLDs 200 KB
pdf Synplify/ModelSim Tutorial for CPLDs 200 KB
pdf Workstation Flow for Xilinx CoolRunner CPLDs 50 KB
Download associated PC design files for VHDLInternet Link and VerilogInternet Link


XCELL Articles

Title Issue
pdf CPLD ChipViewer-Graphical Design Control Made Simple Q4'99 New
pdf Xilinx Introduces - New High-Speed Download Cable Q4'99 New
pdf What's New in v2.1i for XC9500 CPLDs? Q4'99 New
pdf Xilinx at Work in Digital Modems Q4'99 New
pdf Software Selection Guide Q4'99 New
pdf FPGA/CPLD Selection Guide Q4'99 New
pdf Xilinx Acquires CoolRunner Line of CPLDs Q3'99
pdf WebFITTER - Now Better Than Ever Q3'99
pdf New WebPACK - Packs a CPLD Punch Q3'99
pdf Advanced Chip Scale & BGA Packaging Q3'99
pdf FPGA/CPLD Device Selection Q3'99
pdf Software Selection Guide Q3'99