Xilinx CPLD Software Solutions Frequently Asked Questions (FAQ)

	What software is available for Xilinx CPLDs?		What is Alliance?
	What is WebFITTER?		How is schematic entry supported?
	What features are available in WebFITTER?		How is simulation supported?
	What is WebPACK?		How are workstation design flows supported?
	What features are available in WebPACK?		Is XPLA Professional supported?
	How can I obtain WebPACK?		How do I migrate designs from XPLA Professional to WebPACK?
	What is Foundation?		What software do I use to program Xilinx CPLDs?
	What features are available in Foundation?		What third party programming support is available for the Xilinx CPLDs?

What software is available for Xilinx CPLDs?

Xilinx currently offers various software tools for targeting the Xilinx CPLD product line. WebFITTER and WebPACK as well as the Foundation and Alliance software packages may be used to target XC9500 devices. WebFITTER and WebPACK can synthesis and fit the complete Xilinx CPLD product line which now includes the new CoolRunner (XCR) device series CPLDs. CoolRunner support is being integrated into all Xilinx software and should be available throughout the product line in mid CY2001.

What is WebFITTER?

The WebFITTER is a free web-based CPLD design fitting software tool. WebFITTER allows logic designers to evaluate and design Xilinx CPLDs using the latest version of Xilinx software. Fitting and device programming results can be obtained in minutes via the web. WebFITTER also allows for users to receive an immediate price quote for the device being targeted. You can register and use WebFITTER today.

What features are available in WebFITTER?

Products Supported:	5V	XC9500, XCR22V10, and XPLA1(XCR5000)
	3.3V	XC9500XL, XCR22LV10, XPLA1(XCR3000A), XPLA2 (XCR3000-SRAM Based), XPLA3 (XCR3000XL )
	2.5V	XC9500XV
Accepted Design Entry Formats:	VHDL, Verilog, ABEL, EDIF, TDO, NCR, and XNF
Constraints File (Optional):	User specified constraints are accepted.
Device Selection Options	By density, package, speed, voltage or auto select.
Output:	Timing report, fitter report, programming file (JEDEC), timing simulation model (VHDL, Verilog or EDIF)

What is WebPACK?

WebPACK is a collection of independent, download-able software modules. Currently, WebPACK consists of the following modules:

HDL design entry module for ABEL, VHDL, or Verilog designs
XC9500 fitter module
XCR fitter module
XC9500 JTAG Programmer module
XCR PC-ISP3 module for XCR JTAG programming support

The modules may be used to compile and fit designs to CoolRunner and 9500 CPLDs. These modules may be combined to form a complete HDL design synthesis environment. Individual modules are useful in augmenting a designer's existing Xilinx or third party tool set. WebPACK also has the necessary modules for programming the target CPLD through the JTAG port.

What features are available in WebPACK?

WebPACK contains the following features:

Multiple Design Entry Formats

Verilog, VHDL

3^rd party EDIF net list files

ABEL

Altera TDO file

Produces VHDL and Verilog timing models of the design.

Fitter(s) for the XC9500 & CoolRunner (XCR) families.

XC9500 JTAG Programmer and PC-ISP3 XCR Programmer.

Graphical contrainsts entry and logic placement for the XC9500 family through ChipViewer.

Software Utilities such as XCR Idd calculator and exhaustive mode fitting scripts.

How can I obtain WebPACK?

WebPACK is currently available free-of-charge by registering.

What is Foundation?

The Foundation Series software is a complete programmable logic device (PLD) design environment. The software spans the entire Xilinx PLD line from PROMs through CPLDs and into FPGAs including the Spartan and Virtex FPGA lines. Foundation also interfaces with other EDA vendor tools providing PLD design engineers with a powerful yet flexible design environment.

What features are available in Foundation?

Foundation is the main PLD software development tool produced by Xilinx. It is the basis for all other software development tools created by Xilinx. For this reason it is best to check out our Foundation Series v2.1i Software web page for a complete listing of features and configuration options.

What is Alliance?

The Alliance Series software is designed for companies who have made an investment in an EDA environment customized to suit the needs of their design engineers. The Xilinx Alliance Series plug and plays by leveraging open systems standards, interfaces and formats such as EDIF, SDF, VHDL, VITAL/Verilog and STAMP. Combining the strengths of our EDA partner tools with the advanced implementation features found in the Xilinx Alliance Series Software provides digital designers the ultimate in flexibility and design performance.

Does WebPACK support schematic entry?

Direct schematic support is not currently available in WebPACK. For designs targeting either XC9500 or CoolRunner (XCR) CPLDs, third party schematic designs are supported using WebPACK's EDIF net list entry. Foundation designs (both schematic and mixed schematic/HDL) which target the 9500 library are supported. Foundation users targeting the XC9500 should complete the implementation in Foundation. Foundation users targeting the XCR series must create an EDIF net list file in Foundation and import the EDIF net list file into WebPACK.

Future Xilinx software will provide schematic entry beginning Summer 2000.

The schematic capture package used in XPLA Professional is not recommended for new designs. It uses a discontinued release of the Xilinx ECS schematic entry package and the discontinued Philips symbol library.

How is simulation supported?

Simulation is supported in Foundation through either gate level simulation or HDL simulation depending on which package was purchased.

WebPACK outputs Verilog and/or VHDL timing simulation models for use in third party simulators. WebPACK also supports a functional simulation using BLIFSIM. ABEL test vectors need to be created in conjunction with the design. For more information on this please refer to the Test Vector and Simulation sections of WebPACK HELP.

How are workstation design flows supported?

WebPACK is not available for workstation flows. For XC9500 designs, Xilinx's Alliance software is available. For XCR designs, a command line based script is available for implementing designs using ABEL or third party CAE design tools. Please contact your local Xilinx representative for more information.

Is XPLA Professional supported?

XPLA Professional is available for devices which are not supported in WebPACK. These include the original XPLA1 series most members of the XCR3XXXAS series. In general, these devices are not recommended for new designs.

XPLA Professional supports third party design flows which use CoolRunner (XCR) libraries to generate EDIF net lists. XPLA Professional also accepts WebPACK generated EDIFs.

XPLA Professional is available from Xilinx CPLD Web Powered Software Solutions web site

How do I migrate designs from XPLA Professional to WebPACK?

If a design is done in Philips Hardware Description Language (PHDL), rename the .phd extension to .abl, and compile the design in WebPACK. In general, PHDL is a subset of ABEL, and most designs should compile without editing the source code. WebPACK's online help and context-sensitive text editor can be used if the source code doesn't compile. Schematic designs done in XPLA Professional with the discontinued Philips symbol library should not be migrated to WebPACK.

What software do I use to program Xilinx CPLDs?

The XC9500 JTAG Programmer module in WebPACK is used for programming XC9500 series devices. The PC-ISP3 module in WebPACK is used for programming XPLA1 and XPLA3 series devices with limited support of the XPLA2 series. Both the XC9500 and PC-ISP programmer modules provide the following features:

Setup of JTAG Chain.
Port/Cable Setup.
ATE Vector Generation.
Safe Programming Modes

The XPLA2 series consist of the XCR3320 and the XCR3960. Like Xilinx FPGAs, these are SRAM based devices and they are configured using the same configuration modes as Xilinx FPGAs. The XCR3320 can be configured through the JTAG port using the XCR JTAG Programmer module but the XCR3960 cannot. The XCR3960 may be configured in the slave serial mode.

What third party programming support is available for the Xilinx CPLDs?

The following Third Party Programmer vendors currently support both the CoolRunner (XCR) and XC9500 CPLD families: BP, Data I/O, Hi-Lo, Tribal, and Xilinx. Additional vendor support for Xilinx CPLD families varies depending on product line and family. For a detailed listing of device and package support, please visit our 3rd Party Programmer Support web page. Please note that this page will be updated frequently.
Note: The XPLA3 family is programmed using ISP through the JTAG port. Support by 3rd Party Programmers is in development.