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Xilinx CPLDs are easy to use. Our 5V XC9500 and new 3.3V XC9500XL families offer the complete solution for designers today, from performing the simplest of PAL integration designs to the more advanced, real-time hardware field updates. Our customer proven pin-locking capability, along with the industry's most advanced JTAG test capability, means you can now easily program, test and verify your designs. That means it's easier and faster to get your system to market using Xilinx FastFLASH™ products. The Performance Leader in 3.3 Volt Designs Our new lower cost XC9500XL family gives you the industry's best system level performance while maintaining proven flexibility and routability. You can now easily design fast synchronous DRAM controllers operating near 200 MHz, and interface to today's more demanding tightly coupled microprocessors. Besides speed, the XC9500XL family includes a host of additional enhancements including input hysteresis to dramatically increase noise immunity, 5 volt tolerant pins that accept 5 volt, 3.3 volt, and 2.5 volt, and an additional JTAG CLAMP instruction that supports sophisticated interconnect test. The second generation "ISP friendly" pin-locking architecture, highlighted by a 54-input function block, allows you to make extensive changes while keeping your pinouts fixed. It includes such flexible features such as full control of clock and output enable inversion on a per macrocell basis as well as individual product term clock enables. No other CPLD offers these unique capabilities.
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