Virtex™ Virtex Architecture Highlights System-critical Features System Timing Solution Architecture Overview Fully Digital Delay Locked Loops (DLL) System Integration Solution Vector-based Interconnect System Memory Solution Virtex Family Roadmap Virtex SelectRAM+ Memory Hierarchy System Interface Solution Leading-Edge Software Solution Summary The Virtex family redefines the future of programmable logic by giving you next-generation FPGAs that break density and performance barriers while offering unprecedented system level integration. Virtex series devices range from 50,000 to 1,000,000 system gates at clock speeds up to 200 MHz, and include many new features that address system level design challenges, all at new, industry-leading prices. Fully supported by the Alliance Series™ and Foundation Series™ software, the Virtex family is a complete solution, ready to meet the challenges of your next generation designs. Plus, our extensive library of SmartIP™ cores helps you quickly create very complex designs, with guaranteed results. Virtex Architecture Highlights Nine devices, from 50,000 to 1,000,000 system gates (1,728 to 27,648 Logic Cells) Over 500 user I/O pins Many package options, including leading-edge 1.0mm FinePitch™ ball grid arrays and 0.8mm chip scale packages Leading edge 2.5-Volt, 0.22 micron, five-layer metal CMOS process Fully 5-Volt tolerant I/Os Timing-driven place and route tools allow compile times of 200,000 gates per hour on a 400 MHz Pentium II CPU System-critical Features   Four, fully digital, Delay Locked Loops (DLLs) to aid system clock generation, synchronization, and distribution Vector-based interconnect for fast, predictable, core-friendly routing across all densities Supports 3 levels of memory hierarchy SelectI/O™ technology supports multiple voltage and signal standards, simultaneously Fully 66 MHz / 64 bit PCI and Compact PCI compliant The Virtex Series Transforms FPGAs from Glue Logic to System Component System Timing Solution The Virtex series solves clock skew issues by allowing internal and external clock synchronization. With four Delay Locked Loops, your system's clock skew will be eliminated. You can get clock-to-output delays of less than three nanoseconds and a very substantial increase in system performance. Top of page

| Product Overview Cover | Corporate Overview | Virtex-Redefining the FPGA | | CPLDs - A New Generation | FPGAs - A Heritage of Excellence | Hardwire FpgASICs | Software Solutions | | Core Solutions | High-Reliability Products | Technical Service and Support |