Zero Delay Clock Management Multiple DLLs facilitate precise generation of zero-delay clocks both inside and outside the FPGA for highest chip-to-chip speeds. Fully Digital Delay Locked Loops (DLL) Four independent DLL circuits for internal and external clock synchronization 200 MHz chip-to-chip communication Less than 3 ns clock-to-output time across all devices Clock doubling and clock division 0° degree, 90° degree, 180° degree, and 270° degree phase System Integration Solution With an available density range up to 1,000,000 gates, the Virtex series allows unprecedented system level integration, supported by a highly efficient segmented routing structure which provides abundant routing resources and assures consistent performance. Vector-based Interconnect Core friendly routing results in consistent performance regardless of size or number of cores Routing structure optimized to handle high-fanout nets Drop-in Intellectual Property with fast, predictable performance in all devices SmartIP™ Optimized Vector-Based Interconnect System Memory Solution Data intensive applications require high-bandwidth memory. The Virtex SelectRAM+ memory hierarchy provides high bandwidth for memory block sizes in bytes (distributed memory), kilobytes (block memory), and megabytes (SSTL3 interface to external DRAM and SRAM). Return to Virtex-Redefining the FPGA

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