Virtex Family Roadmap  Device XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 System Gates 57,906 108,904 164,674 236,666 322,970 468,252 661,111 888,439 1,124,022 Logic Cells 1,728 2,700 3,888 5,292 6,912 10,800 15,552 21,168 27,648 Block RAM Bits 32,768 40,960 49,152 57,344 65,536 81,920 98,304 114,688 131,072 Max Avail User I/O 180 180 260 284 316 404 512 512 512 Package Size     I/O XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 12 x 12mm          98 CS144 CS144               20 x 20mm          98 TQ144 TQ144               32 x 32mm          166 PQ240 PQ240 PQ240 PQ240 PQ240 HQ240 HQ240 HQ240   27 x 27mm          180 BG256 BG256 BG256 BG256           35 x 35mm          260     BG352 BG352 BG352         40 x 40mm          316         BG432 BG432 BG432 BG432   42.5 x 42.5mm     444           BG560 BG560 BG560 BG560 17 x 17mm          176 FG256 FG256 FG256 FG256           23 x 23mm          312     FG456 FG456 FG456         27 x 27mm          404           FG676 FG676 FG676   40 x 40mm          512             FG680 FG680 FG680 Speed Grades -4, -5, -6 -4, -5, -6 -4, -5, -6 -4, -5, -6 -4, -5, -6 -4, -5, -6 -4, -5, -6 -4, -5, -6 -4, -5, -6 Return to Virtex-Redefining the FPGA

 

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