3 Level Memory Hierarchy Enables 200MHz Bandwidth Virtex SelectRAM+ Memory Hierarchy Distributed SelectRAM+ Memory The vast array of configurable logic blocks (CLBs) are each configurable as a 16x1, 16x2, or 32x1 synchronous RAM, or as a 16x1 dual-port synchronous RAM Block SelectRAM+ Memory Dedicated blocks of on-chip 4,096 bit full dual-port synchronous RAM for critical high- bandwidth memory, configurable as 4Kx1, 2Kx2, 1Kx4, 512x8, and 256x16 Up to 200 MHz Interface For external SDRAM, ZBT, SGRAM, and SSRAM memories. System Interface Solution Virtex SelectI/O technology facilitates high-performance connectivity to leading-edge devices employing multiple voltage and signal standards: Chip to chip   LVTTL, LVCMOS Chip to Memory   SSTL2-I, SSTL2-II, SSTZL3-I, SSTL3-II, HSTL-I, HSTL-III, HSTL-IV, CTT Chip to Backplane   PCI66, PCI33-5V, PCI33-3.3V GTL, GTL+, AGP Future   SelectI/O technology allows support for future standards Fourth Generation Configurable Logic Block Leading-Edge Software Solution Software Support - The Xilinx Alliance Series and Foundation Series software provide complete support for Virtex FPGAs. The new Virtex series CLB was developed in parallel with our synthesis tools to guarantee high performance results when used with VHDL and Verilog design methodologies. Complex logic such as 32-bit arithmetic functions, pipelined multiplication, and 64-to-1 multiplexing can be easily described in a high level language and will operate above 100 MHz in any Virtex series device. The Virtex series is supported in Alliance Series and Foundation Series software, featuring state-of-the-art, push-button productivity with high performance results. Timing-driven place and route tools allow you to compile 200,000 gates per hour. Core Support - Our SmartIP™ core technology, in conjunction with our regular CLB structure and the very dense routing resources in Virtex devices, allows you to place multiple cores anywhere on the device and still achieve consistent, predictable core performance. Plus, we have a large and expanding array of cores from which to choose, available from both Xilinx and from our AllianceCORE™ partners. Summary The revolutionary Virtex family of FPGAs breaks new density and performance barriers by expanding the traditional uses for programmable logic; delivering the first platform that truly addresses system-level design challenges. Virtex is a complete family of nine devices that range in density from 50,000 to 1,000,000 system gates with 200 MHz chip-to-chip performance. The Virtex family features four, fully digital, Delay Locked Loops for internal and external clock synchronization, a hierarchy of memory access, and SelectI/O technology for simultaneous interface to multiple voltage and signal standards. Combined with Alliance Series and Foundation Series state of the art software, Virtex offers unprecedented system level integration capabilities. There has never been an easier or faster way to get your systems to market. Return to Virtex-Redefining the FPGA

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