Digital Component Models

Type	Description	Source
Logic AND	and module with variable number of input terminals	and.va
Logic NAND	nand module with variable number of input terminals	nand.va
Logic OR	or module with variable number of input terminals	or.va
Logic NOR	nor module with variable number of input terminals	nor.va
Logic XOR	xor module with variable number of input terminals	xor.va
Logic XNOR	xnor module with variable number of input terminals	xnor.va
Logic NOT	inverter module with variable number of input and output terminals	not.va
D-Flip-Flop	D-Flip Flop	d_ff.va
JK-Flip-Flop	JK-Flip-Flop	jk_ff.va
RS-Flip-Flop	RS-Flip-Flop	rs_ff.va
T-Flip-Flop	T-Flip-Flop	t_ff.va
Clock Generator	clock generator for symmetric clock	clock_generator.va
Bit Error Rate	bit error rate calculator model	biterrorrate.va

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Logic AND module

Module Name and.va	V_and
Terminals	in : terminal : input [0:size-1] voltage out : terminal : output voltage
Parameter	size : number of input bits = 2 from [2:inf) vout_high : high output voltage = 5.0 vout_low : low output voltage = 0.0 from (-inf:vout_high) vth : input threshold voltage = 1.4 tdelay : time between change on a input and output : 5n from [0:inf) trise : rising time = 1n from [0:inf) tfall : falling time = 1n from [0:inf)

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Logic NAND module

Module Name nand.va	V_nand
Terminals	in : terminal : input [0:size-1] voltage out : terminal : output voltage
Parameter	size : number of input bits = 2 from [2:inf) vout_high : high output voltage = 5.0 vout_low : low output voltage = 0.0 from (-inf:vout_high) vth : input threshold voltage = 1.4 tdelay : time between change on a input and output : 5n from [0:inf) trise : rising time = 1n from [0:inf) tfall : falling time = 1n from [0:inf)

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Logic OR module

Module Name or.va	V_or
Terminals	in : terminal : input [0:size-1] voltage out : terminal : output voltage
Parameter	size : number of input bits = 2 from [2:inf) vout_high : high output voltage = 5.0 vout_low : low output voltage = 0.0 vth : input threshold voltage = 1.4 tdelay : time between change on a input and output : 5n from [0:inf) trise : rising time = 1n from [0:inf) tfall : falling time = 1n from [0:inf)

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Logic NOR module

Module Name nor.va	V_nor
Terminals	in : terminal : input [0:size-1] voltage out : terminal : output voltage
Parameter	size : number of input bits = 2 from [2:inf) vout_high : high output voltage = 5.0 vout_low : low output voltage = 0.0 from (-inf:vout_high) vth : input threshold voltage = 1.4 tdelay : time between change on a input and output : 5n from [0:inf) trise : rising time = 1n from [0:inf) tfall : falling time = 1n from [0:inf)

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Logic XOR module

Module Name xor.va	V_xor
Terminals	in : terminal : input [0:size-1] voltage out : terminal : output voltage
Parameter	size : number of input bits = 2 from [2:inf) vout_high : high output voltage = 5.0 vout_low : low output voltage = 0.0 from (-inf:vout_high) vth : input threshold voltage = 1.4 tdelay : time between change on a input and output : 5n from [0:inf) trise : rising time = 1n from [0:inf) tfall : falling time = 1n from [0:inf)

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Logic XNOR module

Module Name xnor.va	V_xnor
Terminals	in : terminal : input [0:size-1] voltage out : terminal : output voltage
Parameter	size : number of input bits = 2 from [2:inf) vout_high : high output voltage = 5.0 vout_low : low output voltage = 0.0 from (-inf:vout_high) vth : input threshold voltage = 1.4 tdelay : time between change on a input and output : 5n from [0:inf) trise : rising time = 1n from [0:inf) tfall : falling time = 1n from [0:inf)

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Logic NOT module

Module Name not.va	V_not
Terminals	in : terminal : input [0:size-1] voltage out : terminal : output [0:size-1] voltage
Parameter	size : number of bits = 2 from [2:inf) vout_high : high output voltage = 5.0 vout_low : low output voltage = 0.0 from (-inf:vout_high) vth : input threshold voltage = 1.4 tdelay : time between change on a input and output : 5n from [0:inf) trise : rising time = 1n from [0:inf) tfall : falling time = 1n from [0:inf)

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D-Flip-Flop module

Module Name d_ff.va	V_d_ff
Terminals	q : logic output : output voltage qbar : inverse logic output : output voltage clk : clock terminal : input voltage d : data input : input voltage
Parameter	tdelay : time between change on a input and output : 5n from [0:inf) ttransit : transit time for changes at the output : 5n from [0:inf) vout_high : high output voltage = 5.0 vout_low : low output voltage = 0.0 from (-inf:vout_high) vth : input threshold voltage = 1.4

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JK-Flip-Flop module

Module Name jk_ff.va	V_jk_ff
Terminals	q : logic output : output voltage qbar : inverse logic output : output voltage clk : clock terminal : input voltage j : data input : input voltage k: data input : input voltage
Parameter	tdelay : time between change on a input and output : 5n from [0:inf) ttransit : transit time for changes at the output : 5n from [0:inf) vout_high : high output voltage = 5.0 vout_low : low output voltage = 0.0 from (-inf:vout_high) vth : input threshold voltage = 1.4

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RS-Flip-Flop module

Module Name rs_ff.va	V_rs_ff
Terminals	q : logic output : output voltage qbar : inverse logic output : output voltage set : data input : input voltage reset : data input : input voltage
Parameter	tdelay : time between change on a input and output : 5n from [0:inf) ttransit : transit time for changes at the output : 5n from [0:inf) vout_high : high output voltage = 5.0 vout_low : low output voltage = 0.0 from (-inf:vout_high) vth : input threshold voltage = 1.4

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T-Flip-Flop module

Module Name t_ff.va	V_t_ff
Terminals	q : logic output : output voltage clk : clock terminal : input voltage
Parameter	tdelay : time between change on a input and output : 5n from [0:inf) ttransit : transit time for changes at the output : 5n from [0:inf) vout_high : high output voltage = 5.0 vout_low : low output voltage = 0.0 from (-inf:vout_high) vth : input threshold voltage = 1.4 q_init : integer initial value for q = 0 from [0:1]

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Clock Generator

Module Name clock_generator.va	clock_generator
Terminals	clk : terminal : output voltage
Parameter	clk_period : clock period = 10n from (0:inf) clk_ratio : ratio between low clock time and clock period = 0.5 clk_high : high clock output = 5.0 clk_low : low clock output = 0.0 from (-inf:clk_high) trise : rising time = 1n tfall : falling time = 1n

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Bit Error Rate Calculator

Module Name biterrorrate.va	bit_error_rate
Terminals	in : input terminal : input voltage ref : reference terminal : input voltage
Parameter	period : clock period = 5n from (0:inf) vth : threshold for input bits = 2.5

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   Last updated on
   December 11, 1998