Xilinx Product Strategy  We recognize that our future growth is dependent on the development of new products. Our primary areas of focus are: to set a new standard for lower complexity CPLDs, to maintain density/performance leadership with our FPGAs, to give our customers a low-cost migration path for high-volume applications with our mask-programmed HardWire™ ASICs and to support all our product families with easy-to-use, fully automated software.  Faster design verification.  Xilinx FPGAs and CPLDs can be designed and verified much faster than traditional gate arrays. Additionally, there are no non-recurring engineering (NRE) costs, no test vectors to generate and no prototypes to wait for.  Design Changes Without Penalties  Because Xilinx devices are dynamically reconfigurable, modifications are risk-free and can be made anytime. This adds up to significant cost savings in design and production.

Shortest Time-to-Market.  With Xilinx programmable logic, your time-to-market is measured in weeks rather than the months required for traditional gate arrays. This can be a critical decision in your device selection. In fact, a study by McKinsey and Company concluded that a six-month delay in getting to market can cost a product one-third of its lifetime profit potential. With a custom gate array, design iterations can easily add these critical six months, and more, to a product schedule.  No-Risk Cost Reduction Path.  Once the programmable logic design is finalized, high-volume applications can take advantage of the Xilinx HardWire conversion for cost reduction. No simulation files or test vectors are required to complete the conversion. No additional customer engineering is required to convert the FPGA design into a fully tested, completely verified HardWire device.

Acceleration of Time to Market/Volume Chart

 
 

PROGRAMMABLE PRODUCT FAMILY OVERVIEW
Industry   Category	Product Series	Technology	Ideal Use	Series  Key Features	Product Family	Macrocells/  Logic Cells	Max.  Logic Gates	Max. I/O	Voltage
Complex PLD   (CPLDs)	XC9000	FLASH	ISP  Predictable Timing  Fast Pin-to-Pin Speeds	5V ISP, 5ns Tpd, JTAG,  Industry-leading Pin-locking,  High Endurance	XC9500	36-288	0.8K-6.4K	192	5V
Reprogrammable FPGAs	XC4000	SRAM	High Density  High Performance	Select-RAM™ Distributed RAM, Dedicated Arithmetic Logic,  PCI Compliant,   JTAG, Internal 3-State buffers	XC4000E	238-2,432	3K-25K	256	5V
					XC4000EX	2,432-3,078	28K-36K	288	5V
					XC4000XL	466-7,448	5K-85K	448	3.3V
					XC4000XV	10,982	125K	448	2.5V
	Spartan Series	SRAM	Low Cost   High Performance		Spartan XCS00	238-1,862	3K-20K	205	5V

   

| Product Overview Homepage | Corporate Overview | Advanced Programmable Logic Technology |  | Xilinx Delivers a New Generation of CPLDs | A Heritage of FPGA Excellence | Hardwire Gate Array |  | Xilinx Software Solutions | Xilinx Core Solutions | Comprehensive Technical Support |

 

© 1998 Xilinx, Inc. All rights reserved Trademarks and Patents