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Xilinx Delivers a New Generation of CPLDs

 
CPLD Product Selection Matrix 
DEVICES
KEY FEATURES
Density
Features
Macrocells
Max. I/O
ISP
Pin-to-Pin Delay (ns)
Individual OE Control
JTAG (IEEE1149.1)
X
C
9
5
0
0
XC9536 

XC9572 

XC95108 

XC95144 

XC95216 

XC95288 

5V ISP 
Best Pin-Locking 
JTAG 
High Endurance 
36  34 
72  72  7.5 
108  108  7.5 
144  133  7.5 
216  166  10 
288  192  15 
 
 
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