| Application Notes |
Ver. |
Date |
Size |
 XAPP137:
Configuring Virtex FPGAs from Parallel EPROMs with a CPLD |
1.0 |
3/99 |
90 KB |
| XAPP113:
Faster Erase Times for XC95216 and XC95108 Devices on HP 3070 Series Testers |
1.0 |
7/98 |
30 KB |
| XAPP110:
XC9500 CPLD Power Sequencing |
1.0 |
1/98 |
30 KB |
| XAPP109:
Hints, Tips and Tricks for using XABEL with Xilinx M1.5 Design and Implementation
Tools |
2.0 |
10/98 |
80 KB |
| XAPP105:
A CPLD VHDL Introduction |
1.0 |
1/98 |
60 KB |
| XAPP104:
A Quick JTAG ISP Checklist |
1.1 |
1/99 |
20 KB |
| XAPP103:
The Tagalyzer - A JTAG Boundary Scan Debug Tool |
1.0 |
1/98 |
130 KB |
XAPP102:
XC9500 Remote Field Upgrade
Associated PC
and UNIX
design files |
1.0 |
1/98 |
80 KB |
XAPP078:
XC9536 ISP Demo Board
Johnson Shift Counter VHDL
Code
Johnson Shift Counter ABEL
Code
VHDL Design
Files |
1.0 |
4/97 |
41 KB |
| XAPP077:
Metastability Considerations |
1.0 |
1/97 |
23 KB |
| XAPP076:
Embedded Instrumentation Using XC9500 CPLDs |
1.0 |
1/97 |
39 KB |
| XAPP075:
Using ABEL with Xilinx CPLDs |
1.0 |
1/97 |
53 KB |
| XAPP074:
Pin Preassigning with XC9500 CPLDs |
1.3 |
6/98 |
50 KB |
| XAPP073:
Designing with XC9500 CPLDs |
1.3 |
1/98 |
70 KB |
| XAPP071:
Using the XC9500 Timing Model |
1.0 |
1/97 |
47 KB |
| XAPP070:
Using In-System Programmability in Boundary-Scan Systems |
1.1 |
7/97 |
42 KB |
| XAPP069:
Using the XC9500 JTAG Boundary-Scan Interface |
2.0 |
2/98 |
122 KB |
| XAPP068:
In-System Programming Times |
1.2 |
4/98 |
13 KB |
| XAPP067:
Using Serial Vector Format Files to Program XC9500 Devices In-System on
Automatic Test Equipment and Third Party Tools |
1.1 |
7/97 |
40 KB |
XAPP058:
Xilinx In-System Programming Using an Embedded Microcontroller
Associated files are available for PC,
Solaris,
and HP(files
updated 6/99) |
2.0 |
6/99 |
300 KB |
| Application Brief |
|
|
|
| XBRF009:
XC9500 Pin-Locking Capability and Benchmarks |
1.3 |
1/97 |
47 KB |
XC9500XL
to view the 
PDF files below.
