/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
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/******************************************************************************/
/****************************************************************************
* @(#)abort_write_sm.v 1.11 2/22/96
* aw_sm.v
*
* Description:
* This is a state machine that detects when a write burst
* needs to be terminated because of late-arriving data
* that hasn't been properly packed.
* When the trcv fifos are read out and only a single 32-bit word
* is available, it is presumed that the trcv fifos have run
* out of data and are down to this last single word.
* However, if late-coming data get written into the trcv's
* after this "last single" is detected, the burst must be
* terminated because the address generation may no longer be
* in sync with the data packing.
*
*
* This module is instantiated by the afxmaster.v module.
*
*
*
****************************************************************************/
`define AW_IDLE 3'b000
`define WAIT4VAL 3'b001
`define LAST_DATA 3'b011
`define DELAYED_ABORT 3'b010
`define WRITE_ABORTED 3'b110
`define QUICK_ABORT 3'b101 //2.0: new state
`timescale 1ns/1ns
module abort_write_sm
(pend_abort_write, abort_write, write_aborted,
delayed_abort_write,
gclk, reset_l, last_single, no_rcv_read,
valid_l, trcv2_only, data_cyc, cas_cyc,
radr_cyc, cadr_cyc, hold_cyc, idle_cyc, req_cyc,
trcv2_read, new_cmd_start);
output pend_abort_write
;
output abort_write
;
output write_aborted
;
output delayed_abort_write
; //2.0: new output
input gclk
;
input reset_l
;
input last_single
;
input no_rcv_read
;
input valid_l
;
input trcv2_only
;
input data_cyc
;
input cas_cyc
;
input radr_cyc
;
input cadr_cyc
;
input hold_cyc
;
input idle_cyc
;
input req_cyc
;
input trcv2_read
;
input new_cmd_start
;
wire [2:0] aw_state
; // curr state of sm
function [2:0] aw_sm;
input [2:0] aw_state;
input reset_l;
input last_single;
input no_rcv_read;
input valid_l;
input trcv2_only;
input data_cyc;
input cas_cyc;
input radr_cyc;
input cadr_cyc;
input hold_cyc;
input idle_cyc;
input req_cyc;
input trcv2_read;
input new_cmd_start;
reg [2:0] aw_ns; // next_state
begin
if (~reset_l) begin
aw_ns = `AW_IDLE;
end
else begin
aw_ns = aw_state;
case (aw_state)
`AW_IDLE: begin
//2.0 add no_rcv_read case
if (no_rcv_read)
aw_ns = `QUICK_ABORT;
else if (last_single & radr_cyc)
aw_ns = `LAST_DATA;
else if (last_single & data_cyc & ~valid_l)
aw_ns = `LAST_DATA;
else if (last_single & data_cyc & valid_l)
aw_ns = `WAIT4VAL;
end
`WAIT4VAL: begin
if (~valid_l)
aw_ns = `LAST_DATA;
else
aw_ns = `WAIT4VAL;
end
`LAST_DATA: begin
if (trcv2_only & (radr_cyc | cadr_cyc |
data_cyc | hold_cyc |
(idle_cyc & ~new_cmd_start)))
aw_ns = `DELAYED_ABORT;
else
if (~trcv2_only & (radr_cyc | cadr_cyc |
data_cyc | hold_cyc |
(idle_cyc & ~new_cmd_start)))
aw_ns = `LAST_DATA;
else
aw_ns = `AW_IDLE;
end
`DELAYED_ABORT: begin
if (radr_cyc | cadr_cyc |
data_cyc | hold_cyc)
aw_ns = `DELAYED_ABORT;
else
aw_ns = `WRITE_ABORTED;
end
`WRITE_ABORTED: begin
if (trcv2_read)
aw_ns = `AW_IDLE;
else
aw_ns = `WRITE_ABORTED;
end
`QUICK_ABORT: begin
if (req_cyc)
aw_ns = `AW_IDLE;
else
aw_ns = `QUICK_ABORT;
end
default: begin
aw_ns = `AW_IDLE;
//synopsys translate_off
if (reset_l) $display("aw_sm: Error!");
//synopsys translate_on
end
endcase
end
aw_sm = aw_ns;
end
endfunction
reg [2:0] sm_output
;
always @(posedge gclk) begin
sm_output <= #1 aw_sm(aw_state, reset_l, last_single, no_rcv_read,
valid_l, trcv2_only,
data_cyc, cas_cyc, radr_cyc, cadr_cyc,
hold_cyc, idle_cyc, req_cyc, trcv2_read, new_cmd_start);
end
assign aw_state = sm_output;
wire pend_abort_write = (aw_state==`LAST_DATA);
wire abort_write = ((aw_state==`LAST_DATA) & trcv2_only) |
(aw_state==`DELAYED_ABORT) |
(aw_state==`QUICK_ABORT);
wire write_aborted = (aw_state==`WRITE_ABORTED);
//2.0: bring out new wire
wire delayed_abort_write = (aw_state==`DELAYED_ABORT);
endmodule
This page: |
Created: | Thu Aug 19 12:00:53 1999 |
| From: |
../../../sparc_v8/ssparc/pcic/afxmaster/rtl/abort_write_sm.v
|