/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)aregloadctl.v 1.1 4/7/92
//
module AregLoadCtl
(ROM,
LoadOprs,
notAbortWB,
PreventSwap,
FracAregLC, FracAregLoadEn,
LoadFromMult, // Export to Breg
SelInitRemBits);
input [`end_frac_areg_field:`start_frac_areg_field] ROM
;
input LoadOprs
,
notAbortWB
,
PreventSwap
;
output [2:0] FracAregLC
;
output FracAregLoadEn
,
LoadFromMult
,
SelInitRemBits
;
ME_TIEOFF toff (vdd
, gnd
);
ME_INVA iopl (LoadOprs, notLoadOprs
);
ME_AND2 alcn1 (ROM[`u_FracAregFromFunc2], notLoadOprs,
FracAregLC[2]);
ME_AND2 alcn2 (ROM[`u_FracAregFromFunc1], notLoadOprs,
FracAregLC[1]);
ME_AND2 alcn3 (ROM[`u_FracAregFromFunc0], notLoadOprs,
FracAregLC[0]);
ME_OR4 alcne (ROM[`u_FracAregFromFunc0],
ROM[`u_FracAregFromFunc1],
ROM[`u_FracAregFromFunc2],
LoadOprs,
LoadEn
);
//ME_AND3 alcni (LoadEn, notAbortWB, notPreventSwap, FracAregLoadEn);
ME_AND2 alcni (LoadEn, notAbortWB, FracAregLoadEn_p
);
ME_NMUX2B_B alcn0 (FracAregLoadEn_p, vdd, PreventSwap, FracAregLoadEn);
ME_AND3 alcnf (ROM[`u_FracAregFromFunc0],
ROM[`u_FracAregFromFunc1],
ROM[`u_FracAregFromFunc2],
LoadFromMult); // 1 1 1
ME_INVA alcn7 (ROM[`u_FracAregFromFunc0], notFunc0
);
ME_INVA alcn8 (ROM[`u_FracAregFromFunc2], notFunc2
);
ME_AND3_B alcnh (notFunc0,
ROM[`u_FracAregFromFunc1],
notFunc2,
SelInitRemBits); // 0 1 0 ie FracAregFromFracBreg
endmodule
This page: |
Created: | Thu Aug 19 12:02:59 1999 |
| From: |
../../../sparc_v8/ssparc/fpu/fp_ctl/rtl/aregloadctl.v
|