/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
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/* */
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/******************************************************************************/
// @(#)dp.v 1.1 4/7/92
//
module fp_exp
( ss_clock, SNnotDB, OprSNnotDB,
RS2_exp, RS1_exp,
FracAregForInt,
notSLFromNorm,
ShiftBy8,
ExpAregLoadEn, ExpAregLC0, ExpAregLC1,
ExpBregLoadEn, ExpBregLC0, ExpBregLC1,
ExpXCtl0, ExpXCtl1,
ExpYCtl0, ExpYCtl1,
Sub, CarryIn,
Constantb, Constantc, Constantd, Constante,
Constantf, Constantg, Constanth,
// output start here
AregMasterBufOut,
ExpResultBuf, notExpShiftResult,
ExpZero, ExpResult_12,
SLControl,
notAInfNaN, notAZeroDenorm,
notBInfNaN, notBZeroDenorm,
notUnderflow, notOverflow, notExpException,
ss_scan_mode, fp_exp_scan_in, fp_exp_scan_out);
input ss_clock
, SNnotDB
, OprSNnotDB
;
input [10:0] RS2_exp
, RS1_exp
;
input [7:0] FracAregForInt
;
input ExpAregLoadEn
, ExpAregLC0
, ExpAregLC1
;
input ExpBregLoadEn
, ExpBregLC0
, ExpBregLC1
;
input ExpXCtl0
, ExpXCtl1
;
input ExpYCtl0
, ExpYCtl1
;
input Sub
, CarryIn
;
input Constantb
, Constantc
, Constantd
, Constante
,
Constantf
, Constantg
, Constanth
;
input [3:0] notSLFromNorm
;
input ShiftBy8
;
input ss_scan_mode
, fp_exp_scan_in
;
output [3:0] SLControl
;
output [7:0] AregMasterBufOut
;
output [10:0] ExpResultBuf
;
output [12:0] notExpShiftResult
;
output ExpZero
;
output ExpResult_12
;
output notAInfNaN
, notAZeroDenorm
;
output notBInfNaN
, notBZeroDenorm
;
output notUnderflow
, notOverflow
, notExpException
;
output fp_exp_scan_out
;
ME_TIEOFF toff (vdd
, gnd
);
assign fp_exp_scan_out = 1'bx ;
wire [12:0] int_ExpResultBuf
;
assign ExpResultBuf = int_ExpResultBuf[10:0] ;
wire [12:0] AregMaster
, AregMasterBuf
, BregMaster
, BregMasterBuf
,
ExpXbus
, ExpYbus
, ExpResult
;
wire [3:0] ExpYbusS
;
assign ExpResult_12 = ExpResult[12] ;
// extended internal format operands
wire [12:0] OprA
, OprB
;
wire [10:0] ExpOpA
, ExpOpB
;
// Operand select (single/double) muxes
ME_MUX_2B_11 opifaxe (OprSNnotDB,
RS2_exp[10:0],
{gnd, gnd, gnd, RS2_exp[10:3]},
ExpOpA[10:0]);
assign OprA = {gnd, gnd, ExpOpA};
ME_MUX_2B_11 opifbxe (OprSNnotDB,
RS1_exp[10:0],
{gnd, gnd, gnd, RS1_exp[10:3]},
ExpOpB[10:0]);
assign OprB = {gnd, gnd, ExpOpB};
NormCalLog nmcl (notSLFromNorm,
ShiftBy8,
ExpYCtl0, ExpYCtl1,
ExpYbus[3:0],
ExpYbusS[3:0],
SLControl);
//wire [7:0] AregMasterBufOut = AregMasterBuf[7:0];
con1 g0 (AregMasterBuf[0], AregMasterBufOut[0]);
con1 g1 (AregMasterBuf[1], AregMasterBufOut[1]);
con1 g2 (AregMasterBuf[2], AregMasterBufOut[2]);
con1 g3 (AregMasterBuf[3], AregMasterBufOut[3]);
con1 g4 (AregMasterBuf[4], AregMasterBufOut[4]);
con1 g5 (AregMasterBuf[5], AregMasterBufOut[5]);
con1 g6 (AregMasterBuf[6], AregMasterBufOut[6]);
con1 g7 (AregMasterBuf[7], AregMasterBufOut[7]);
ME_FREGA_S_4_13 Areg ( ss_clock,
ExpAregLoadEn, ExpAregLC0, ExpAregLC1,
OprA,
{gnd, gnd, gnd, gnd, gnd, FracAregForInt[7:0]}, // AIntVal
int_ExpResultBuf, BregMasterBuf,
AregMaster, AregMasterBuf);
Exception ae ( AregMasterBuf, SNnotDB, notAInfNaN, notAZeroDenorm);
ME_MUX_4B_13 Ymux (ExpYCtl0, ExpYCtl1,
{gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}, // Zero
{gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, vdd, gnd, gnd, gnd}, // Normaliser value of 8
AregMasterBuf,
{gnd, gnd, gnd, Constantb, Constantb, Constantb, Constantc,
Constantc, Constantd, Constante, Constantf, Constantg, Constanth}, // Constant
ExpYbus );
ME_FREGA_S_4_13 Breg (ss_clock,
ExpBregLoadEn, ExpBregLC0, ExpBregLC1,
OprB,
{int_ExpResultBuf[12], int_ExpResultBuf[12:1]}, // ExpResultSR1
int_ExpResultBuf, AregMasterBuf,
BregMaster, BregMasterBuf);
Exception be (BregMasterBuf, SNnotDB, notBInfNaN, notBZeroDenorm);
ME_MUX_4B_13 Xmux (ExpXCtl0, ExpXCtl1,
{gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}, // Zero
{gnd, gnd, gnd, Constantb, Constantb, Constantb, Constantc,
Constantc, Constantd, Constante, Constantf, Constantg, Constanth}, // Constant
AregMasterBuf, BregMasterBuf,
ExpXbus );
ME_ADD_13 add ( Sub, CarryIn, ExpXbus, {ExpYbus[12:4], ExpYbusS[3:0]}, ExpResult, int_ExpResultBuf, ExpZero);
// original Meiko code (changed 11/7/90 -- dhn):
// shiftsub adds ( BregMaster, AregMaster, notExpShiftResult);
//
//ME_ADD_13 adds ( 1'b1, 1'b0, AregMaster, BregMaster, notExpShiftResult,,);
// just use the subtractor, don't need the condition codes, etc.
ME_SUB_13 subtract13 ( 1'b1, 1'b0, AregMaster, BregMaster, notExpShiftResult );
ResultException re (ExpResult, SNnotDB, ExpZero, notUnderflow, notOverflow, notExpException);
endmodule
This page: |
Created: | Thu Aug 19 12:00:20 1999 |
| From: |
../../../sparc_v8/ssparc/fpu/fp_exp/rtl/dp.v
|