ME_NMUX2B g25 ( notp0to2, Cin, g0to2, notCin3 ) ;
ME_AND4_B g26 ( p0, p1, p2, p3, p ) ;
endmodule
![[Up: acell10 bit0]](v2html-up.gif)
module acell4a
( x, y, notsub, notCin, z, zbuf, p, g ) ;
input [3:0] x, y ;
input notsub, notCin ;
output [3:0] zbuf, z ;
output p, g;
acell1 bit0 ( x[0], y[0], notsub, Cin0, z[0], zbuf[0], p0, notp0, pbuf0 ) ;
acell1 bit1 ( x[1], y[1], notsub, Cin1, z[1], zbuf[1], p1, notp1, pbuf1 ) ;
acell1 bit2 ( x[2], y[2], notsub, Cin2, z[2], zbuf[2], p2, notp2, pbuf2 ) ;
acell1 bit3 ( x[3], y[3], notsub, Cin3, z[3], zbuf[3], p3, notp3, pbuf3 ) ;
ME_NAND2 g10 ( pbuf0, pbuf1, notplo ) ;
ME_NAND2 g11 ( p2, p3, notphi ) ;
ME_NMUX2B_B g12 ( p1, x[1], x[0], notglo ) ;
ME_NMUX2B_B g13 ( p3, x[3], x[2], notghi ) ;
ME_NMUX2B_B g14 ( notphi, notglo, notghi, g ) ;
ME_INV_A g15 ( notCin, Cin0 );
ME_INV_A g16 ( x[0], notg0 );
ME_NMUX2B g17 ( p0, notg0, notCin, Cin1 ) ;
ME_INV_A g18 ( notglo, glo );
ME_INV_A g19 ( glo, notglobuf );
ME_NMUX2B g20 ( notplo, notCin, notglobuf, Cin2 ) ;
ME_NAND3 g21 ( pbuf0, pbuf1, pbuf2, notp0to2 ) ;
ME_INV_A g22 ( x[2], notg2 );
ME_INV_A g23 ( notg2, g2 );
ME_NMUX2B g24 ( notp2, glo, g2, notg0to2 ) ;
ME_NMUX2B g25 ( notp0to2, notCin, notg0to2, Cin3 ) ;
ME_AND4_B g26 ( p0, p1, p2, p3, p ) ;
endmodule
module acell1 ( x, y, sub, Cin, z, zbuf, p, notp, pbuf ) ;
input x, y ;
input sub, Cin ;
output z, zbuf ;
output p, notp, pbuf;
// g is x for first bit
// bit 0
ME_XOR3_B g1 ( y, x, sub, p);
// ME_XOR2_B g1 ( sub, x, q);
// ME_XOR2_B g2 ( y, q, p);
ME_INV_A g3 ( p, notp );
ME_INV_A g5 ( notp, pbuf );
ME_NMUX2B_B g4 ( Cin, notp, pbuf, z) ;
ME_BUF_B g6 ( z, zbuf) ;
endmodule
module acell1a ( x, y, sub, notCin, z, zbuf, p, notp, pbuf ) ;
input x, y ;
input sub, notCin ;
output zbuf, z ;
output p, notp, pbuf;
// g is x for first bit
// bit 0
ME_XOR3_B g1 ( y, x, sub, p );
// ME_XOR2_B g1 ( sub, x, q);
// ME_XOR2_B g2 ( y, q, p);
ME_INV_A g3 ( p, notp );
ME_INV_A g5 ( notp, pbuf );
ME_NMUX2B_B g4 ( notCin, pbuf, notp, z) ;
ME_BUF_B g6 ( z, zbuf) ;
endmodule
// Meiko multiplier cells
//
module CS_bit ( SI, CI, Mul, notSiMulSR, notShift, Neg, notZero,
notSiMul, SA, CA );
input SI, CI, Mul, notSiMulSR, notShift, Neg, notZero ;
output notSiMul, SA, CA ;
ME_XNOR2_B g10 ( .a(Neg), .b(Mul), .z(notSiMul)) ;
ME_NMUX2B g11 ( .s(notShift), .a(notSiMulSR), .b(notSiMul), .z(notSiMulSh)) ;
ME_AND2_B g12 ( .a(notZero), .b(notSiMulSh), .z(Mulbit)) ;
ME_ADD3_B g13 ( .ci(SI), .a(CI), .b(Mulbit), .s(SA), .co(CA)) ;
endmodule
module CS_byte ( SI, CI, Mul, notSiMulSR, notShift, Neg, notZero,
notSiMul, SA, CA );
input [7:0] SI, CI, Mul, notSiMulSR;
input notShift, Neg, notZero ;
output [7:0] notSiMul, SA, CA ;
wire [7:0] notSiMulSh, Mulbit;
ME_XNOR2_B g00 ( .a(Neg), .b(Mul[0]), .z(notSiMul[0])) ;
ME_NMUX2B g01 ( .s(notShift), .a(notSiMulSR[0]), .b(notSiMul[0]), .z(notSiMulSh[0])) ;
ME_AND2_B g02 ( .a(notZero), .b(notSiMulSh[0]), .z(Mulbit[0])) ;
ME_ADD3_B g03 ( .ci(SI[0]), .a(CI[0]), .b(Mulbit[0]), .s(SA[0]), .co(CA[0])) ;
ME_XNOR2_B g10 ( .a(Neg), .b(Mul[1]), .z(notSiMul[1])) ;
ME_NMUX2B g11 ( .s(notShift), .a(notSiMulSR[1]), .b(notSiMul[1]), .z(notSiMulSh[1])) ;
ME_AND2_B g12 ( .a(notZero), .b(notSiMulSh[1]), .z(Mulbit[1])) ;
ME_ADD3_B g13 ( .ci(SI[1]), .a(CI[1]), .b(Mulbit[1]), .s(SA[1]), .co(CA[1])) ;
ME_XNOR2_B g20 ( .a(Neg), .b(Mul[2]), .z(notSiMul[2])) ;
ME_NMUX2B g21 ( .s(notShift), .a(notSiMulSR[2]), .b(notSiMul[2]), .z(notSiMulSh[2])) ;
ME_AND2_B g22 ( .a(notZero), .b(notSiMulSh[2]), .z(Mulbit[2])) ;
ME_ADD3_B g23 ( .ci(SI[2]), .a(CI[2]), .b(Mulbit[2]), .s(SA[2]), .co(CA[2])) ;
ME_XNOR2_B g30 ( .a(Neg), .b(Mul[3]), .z(notSiMul[3])) ;
ME_NMUX2B g31 ( .s(notShift), .a(notSiMulSR[3]), .b(notSiMul[3]), .z(notSiMulSh[3])) ;
ME_AND2_B g32 ( .a(notZero), .b(notSiMulSh[3]), .z(Mulbit[3])) ;
ME_ADD3_B g33 ( .ci(SI[3]), .a(CI[3]), .b(Mulbit[3]), .s(SA[3]), .co(CA[3])) ;
ME_XNOR2_B g40 ( .a(Neg), .b(Mul[4]), .z(notSiMul[4])) ;
ME_NMUX2B g41 ( .s(notShift), .a(notSiMulSR[4]), .b(notSiMul[4]), .z(notSiMulSh[4])) ;
ME_AND2_B g42 ( .a(notZero), .b(notSiMulSh[4]), .z(Mulbit[4])) ;
ME_ADD3_B g43 ( .ci(SI[4]), .a(CI[4]), .b(Mulbit[4]), .s(SA[4]), .co(CA[4])) ;
ME_XNOR2_B g50 ( .a(Neg), .b(Mul[5]), .z(notSiMul[5])) ;
ME_NMUX2B g51 ( .s(notShift), .a(notSiMulSR[5]), .b(notSiMul[5]), .z(notSiMulSh[5])) ;
ME_AND2_B g52 ( .a(notZero), .b(notSiMulSh[5]), .z(Mulbit[5])) ;
ME_ADD3_B g53 ( .ci(SI[5]), .a(CI[5]), .b(Mulbit[5]), .s(SA[5]), .co(CA[5])) ;
ME_XNOR2_B g60 ( .a(Neg), .b(Mul[6]), .z(notSiMul[6])) ;
ME_NMUX2B g61 ( .s(notShift), .a(notSiMulSR[6]), .b(notSiMul[6]), .z(notSiMulSh[6])) ;
ME_AND2_B g62 ( .a(notZero), .b(notSiMulSh[6]), .z(Mulbit[6])) ;
ME_ADD3_B g63 ( .ci(SI[6]), .a(CI[6]), .b(Mulbit[6]), .s(SA[6]), .co(CA[6])) ;
ME_XNOR2_B g70 ( .a(Neg), .b(Mul[7]), .z(notSiMul[7])) ;
ME_NMUX2B g71 ( .s(notShift), .a(notSiMulSR[7]), .b(notSiMul[7]), .z(notSiMulSh[7])) ;
ME_AND2_B g72 ( .a(notZero), .b(notSiMulSh[7]), .z(Mulbit[7])) ;
ME_ADD3_B g73 ( .ci(SI[7]), .a(CI[7]), .b(Mulbit[7]), .s(SA[7]), .co(CA[7])) ;
endmodule
module CS_STAGE_57 (SI, CI, D, Shift, Pos, Zero, SA, CA);
input[56:0] SI, CI, D;
input Shift, Pos, Zero;
output[56:0] SA;
output[56:0] CA;
ME_INV_C ls0 (.a(Shift), .x(_Sh));
ME_INV_B lz1 (.a(Zero), .x(_Ze));
ME_INV_C bs2 (.a(Shift), .x(B_notSh1));
ME_INV_C bs3 (.a(Shift), .x(B_notSh2) ) ;
ME_INV_B lb0 (.a(Pos), .x(Neg));
ME_INV_C g11 (.a(Pos), .x(B_Neg) ) ;
ME_INV_C g12 (.a(Zero), .x(B_nZ) ) ;
wire [56:0] notSiMul;
// Buffer first byte seperately
CS_byte c0 (SI[7:0], CI[7:0], D[7:0], notSiMul[8:1], _Sh, Neg, _Ze, notSiMul[7:0], SA[7:0], CA[7:0] );
CS_byte c1 (SI[15:8], CI[15:8], D[15:8], notSiMul[16:9], B_notSh1, B_Neg, B_nZ, notSiMul[15:8], SA[15:8], CA[15:8] );
CS_byte c2 (SI[23:16],CI[23:16], D[23:16], notSiMul[24:17], B_notSh1, B_Neg, B_nZ, notSiMul[23:16], SA[23:16], CA[23:16] );
CS_byte c3 (SI[31:24],CI[31:24], D[31:24], notSiMul[32:25], B_notSh1, B_Neg, B_nZ, notSiMul[31:24], SA[31:24], CA[31:24] );
CS_byte c4 (SI[39:32],CI[39:32], D[39:32], notSiMul[40:33], B_notSh2, B_Neg, B_nZ, notSiMul[39:32], SA[39:32], CA[39:32] );
CS_byte c5 (SI[47:40],CI[47:40], D[47:40], notSiMul[48:41], B_notSh2, B_Neg, B_nZ, notSiMul[47:40], SA[47:40], CA[47:40] );
CS_byte c6 (SI[55:48],CI[55:48], D[55:48], notSiMul[56:49], B_notSh2, B_Neg, B_nZ, notSiMul[55:48], SA[55:48], CA[55:48] );
ME_INV_C g15 (B_Neg, notSiMulMSB ) ;
CS_bit c7 (SI[56], CI[56], D[56], notSiMulMSB, B_notSh2, B_Neg, B_nZ, notSiMul[56], SA[56], CA[56] );
endmodule
// Meiko register macros
//
/* flip flop register library */
/* components followed by instances */
/* instances should be kept up to date with functional instances */
/* provided block of 1 2 4 8 32 cells to build registers from */
/* registers should also contain buffers to drive datapath lines */
module FDREG_1Bit ( clk, D, Q ) ; // free-running reg
input clk, D ;
output Q ;
ME_FD1 f0 ( .cp(clk), .d(D), .q(Q) ) ;
endmodule
module FDREG_1Byte ( clk, D, Q ) ;
input clk ;
input [7:0] D ;
output [7:0] Q ;
ME_FD1 f0 ( .cp(clk), .d(D[0]), .q(Q[0]) ) ;
ME_FD1 f1 ( .cp(clk), .d(D[1]), .q(Q[1]) ) ;
ME_FD1 f2 ( .cp(clk), .d(D[2]), .q(Q[2]) ) ;
ME_FD1 f3 ( .cp(clk), .d(D[3]), .q(Q[3]) ) ;
ME_FD1 f4 ( .cp(clk), .d(D[4]), .q(Q[4]) ) ;
ME_FD1 f5 ( .cp(clk), .d(D[5]), .q(Q[5]) ) ;
ME_FD1 f6 ( .cp(clk), .d(D[6]), .q(Q[6]) ) ;
ME_FD1 f7 ( .cp(clk), .d(D[7]), .q(Q[7]) ) ;
endmodule
... (truncated)
module FREG_1Bit ( clk, E, D, Q ) ; // load-enable reg
input clk, D, E ;
output Q ;
ME_FD1E f0 ( .cp(clk), .te(E), .d(D), .q(Q) ) ;
endmodule
... (truncated)
module FREG_1Byte ( clk, E, D, Q ) ;
input clk, E ;
input [7:0] D ;
output [7:0] Q ;
ME_FD1E f0 ( .cp(clk), .te(E), .d(D[0]), .q(Q[0]) ) ;
ME_FD1E f1 ( .cp(clk), .te(E), .d(D[1]), .q(Q[1]) ) ;
ME_FD1E f2 ( .cp(clk), .te(E), .d(D[2]), .q(Q[2]) ) ;
ME_FD1E f3 ( .cp(clk), .te(E), .d(D[3]), .q(Q[3]) ) ;
ME_FD1E f4 ( .cp(clk), .te(E), .d(D[4]), .q(Q[4]) ) ;
ME_FD1E f5 ( .cp(clk), .te(E), .d(D[5]), .q(Q[5]) ) ;
ME_FD1E f6 ( .cp(clk), .te(E), .d(D[6]), .q(Q[6]) ) ;
ME_FD1E f7 ( .cp(clk), .te(E), .d(D[7]), .q(Q[7]) ) ;
endmodule
/* real instances start here */
module ME_FDREG_1_57 ( clk, D, Q ) ; // free-running reg
input clk ;
input [56:0] D;
output [56:0] Q;
FDREG_1Byte m0 ( clk, D[7:0], Q[7:0] ) ;
FDREG_1Byte m1 ( clk, D[15:8], Q[15:8] ) ;
FDREG_1Byte m2 ( clk, D[23:16], Q[23:16] ) ;
FDREG_1Byte m3 ( clk, D[31:24], Q[31:24] ) ;
FDREG_1Byte m4 ( clk, D[39:32], Q[39:32] ) ;
FDREG_1Byte m5 ( clk, D[47:40], Q[47:40] ) ;
FDREG_1Byte m6 ( clk, D[55:48], Q[55:48] ) ;
FDREG_1Bit m70 ( clk, D[56], Q[56] ) ;
endmodule
module ME_FREGA_1_52 ( clk, enable, D, Q ) ;
input clk, enable ;
input [51:0] D;
output [51:0] Q;
ME_INV_B m20 ( enable, _E ) ;
ME_INV_C m21 ( _E, E1 ) ;
ME_INV_C m22 ( _E, E2 ) ;
FREG_1Byte m0 ( clk, E1, D[7:0], Q[7:0] ) ;
FREG_1Byte m1 ( clk, E1, D[15:8], Q[15:8] ) ;
FREG_1Byte m2 ( clk, E1, D[23:16], Q[23:16] ) ;
FREG_1Byte m3 ( clk, E1, D[31:24], Q[31:24] ) ;
FREG_1Byte m4 ( clk, E2, D[39:32], Q[39:32] ) ;
FREG_1Byte m5 ( clk, E2, D[47:40], Q[47:40] ) ;
FREG_1Bit m60 ( clk, E2, D[48], Q[48] ) ;
FREG_1Bit m61 ( clk, E2, D[49], Q[49] ) ;
FREG_1Bit m62 ( clk, E2, D[50], Q[50] ) ;
FREG_1Bit m63 ( clk, E2, D[51], Q[51] ) ;
endmodule
module ME_FREGA_1_54 ( clk, enable, D, Q ) ;
input clk, enable ;
input [53:0] D;
output [53:0] Q;
ME_INV_B m20 ( enable, _E ) ;
ME_INV_C m21 ( _E, E1 ) ;
ME_INV_C m22 ( _E, E2 ) ;
FREG_1Byte m0 ( clk, E1, D[7:0], Q[7:0] ) ;
FREG_1Byte m1 ( clk, E1, D[15:8], Q[15:8] ) ;
FREG_1Byte m2 ( clk, E1, D[23:16], Q[23:16] ) ;
FREG_1Byte m3 ( clk, E1, D[31:24], Q[31:24] ) ;
FREG_1Byte m4 ( clk, E2, D[39:32], Q[39:32] ) ;
FREG_1Byte m5 ( clk, E2, D[47:40], Q[47:40] ) ;
FREG_1Bit m60 ( clk, E2, D[48], Q[48] ) ;
FREG_1Bit m61 ( clk, E2, D[49], Q[49] ) ;
FREG_1Bit m62 ( clk, E2, D[50], Q[50] ) ;
FREG_1Bit m63 ( clk, E2, D[51], Q[51] ) ;
FREG_1Bit m64 ( clk, E2, D[52], Q[52] ) ;
FREG_1Bit m65 ( clk, E2, D[53], Q[53] ) ;
endmodule
module ME_FREGA_1_58 ( clk, enable, D, Q ) ;
input clk, enable ;
input [57:0] D;
output [57:0] Q;
ME_INV_B m20 ( enable, _E ) ;
ME_INV_C m21 ( _E, E1 ) ;
ME_INV_C m22 ( _E, E2 ) ;
FREG_1Byte m0 ( clk, E1, D[7:0], Q[7:0] ) ;
FREG_1Byte m1 ( clk, E1, D[15:8], Q[15:8] ) ;
FREG_1Byte m2 ( clk, E1, D[23:16], Q[23:16] ) ;
FREG_1Byte m3 ( clk, E1, D[31:24], Q[31:24] ) ;
FREG_1Byte m12 ( clk, E2, D[39:32], Q[39:32] ) ;
FREG_1Byte m13 ( clk, E2, D[47:40], Q[47:40] ) ;
FREG_1Byte m14 ( clk, E2, D[55:48], Q[55:48] ) ;
FREG_1Bit m15 ( clk, E2, D[56], Q[56] ) ;
FREG_1Bit m16 ( clk, E2, D[57], Q[57] ) ;
endmodule
module ME_FREGA_1_2 ( clk, enable, D, Q ) ;
input clk, enable ;
input [1:0] D;
output [1:0] Q;
FREG_1Bit m0 ( clk, enable, D[0], Q[0] ) ;
FREG_1Bit m1 ( clk, enable, D[1], Q[1] ) ;
endmodule
module ME_FREGA_1_3 ( clk, enable, D, Q ) ;
input clk, enable ;
input [2:0] D;
output [2:0] Q;
FREG_1Bit m0 ( clk, enable, D[0], Q[0] ) ;
FREG_1Bit m1 ( clk, enable, D[1], Q[1] ) ;
FREG_1Bit m2 ( clk, enable, D[2], Q[2] ) ;
endmodule
module ME_FREGA_1_8 ( clk, enable, D, Q ) ;
input clk, enable ;
input [7:0] D;
output [7:0] Q;
FREG_1Byte m0 ( clk, enable, D[7:0], Q[7:0] ) ;
endmodule
module ME_FREGA_1_9 ( clk, enable, D, Q ) ;
input clk, enable ;
input [8:0] D;
output [8:0] Q;
FREG_1Byte m0 ( clk, enable, D[7:0], Q[7:0] ) ;
FREG_1Bit m1 ( clk, enable, D[8], Q[8] ) ;
endmodule
module ME_FREGA_1_11 ( clk, enable, D, Q ) ;
input clk, enable ;
input [10:0] D;
output [10:0] Q;
ME_BUF_B m20 ( enable, E ) ;
FREG_1Byte m0 ( clk, E, D[7:0], Q[7:0] ) ;
FREG_1Bit m1 ( clk, E, D[8], Q[8] ) ;
FREG_1Bit m2 ( clk, E, D[9], Q[9] ) ;
FREG_1Bit m3 ( clk, E, D[10], Q[10] ) ;
endmodule
module ME_FREGA_1_13 ( clk, enable, D, Q ) ;
input clk, enable ;
input [12:0] D;
output [12:0] Q;
ME_BUF_B m20 ( enable, E ) ;
FREG_1Byte m0 ( clk, E, D[7:0], Q[7:0] ) ;
FREG_1Bit m1 ( clk, E, D[8], Q[8] ) ;
FREG_1Bit m2 ( clk, E, D[9], Q[9] ) ;
FREG_1Bit m3 ( clk, E, D[10], Q[10] ) ;
FREG_1Bit m4 ( clk, E, D[11], Q[11] ) ;
FREG_1Bit m5 ( clk, E, D[12], Q[12] ) ;
endmodule
module ME_FREGA_1_25 ( clk, enable, D, Q ) ;
input clk, enable ;
input [24:0] D;
output [24:0] Q;
ME_BUF_C m20 ( enable, E ) ;
FREG_1Byte m0 ( clk, E, D[7:0], Q[7:0] ) ;
FREG_1Byte m1 ( clk, E, D[15:8], Q[15:8] ) ;
FREG_1Byte m2 ( clk, E, D[23:16], Q[23:16] ) ;
FREG_1Bit m3 ( clk, E, D[24], Q[24] ) ;
endmodule
module ME_FREGA_1_26 ( clk, enable, D, Q ) ;
input clk, enable ;
input [25:0] D;
output [25:0] Q;
ME_BUF_C m20 ( enable, E ) ;
FREG_1Byte m0 ( clk, E, D[7:0], Q[7:0] ) ;
FREG_1Byte m1 ( clk, E, D[15:8], Q[15:8] ) ;
FREG_1Byte m2 ( clk, E, D[23:16], Q[23:16] ) ;
FREG_1Bit m3 ( clk, E, D[24], Q[24] ) ;
FREG_1Bit m4 ( clk, E, D[25], Q[25] ) ;
endmodule
module ME_FREGA_1_28 ( clk, enable, D, Q ) ;
input clk, enable ;
input [27:0] D;
output [27:0] Q;
ME_BUF_C m20 ( enable, E ) ;
FREG_1Byte m0 ( clk, E, D[7:0], Q[7:0] ) ;
FREG_1Byte m1 ( clk, E, D[15:8], Q[15:8] ) ;
FREG_1Byte m2 ( clk, E, D[23:16], Q[23:16] ) ;
FREG_1Bit m3 ( clk, E, D[24], Q[24] ) ;
FREG_1Bit m4 ( clk, E, D[25], Q[25] ) ;
FREG_1Bit m5 ( clk, E, D[26], Q[26] ) ;
FREG_1Bit m6 ( clk, E, D[27], Q[27] ) ;
endmodule
module ME_FREGA_1_30 ( clk, enable, D, Q ) ;
input clk, enable ;
input [29:0] D;
output [29:0] Q;
ME_BUF_C m20 ( enable, E ) ;
FREG_1Byte m0 ( clk, E, D[7:0], Q[7:0] ) ;
FREG_1Byte m1 ( clk, E, D[15:8], Q[15:8] ) ;
FREG_1Byte m2 ( clk, E, D[23:16], Q[23:16] ) ;
FREG_1Bit m3 ( clk, E, D[24], Q[24] ) ;
FREG_1Bit m4 ( clk, E, D[25], Q[25] ) ;
FREG_1Bit m5 ( clk, E, D[26], Q[26] ) ;
FREG_1Bit m6 ( clk, E, D[27], Q[27] ) ;
FREG_1Bit m7 ( clk, E, D[28], Q[28] ) ;
FREG_1Bit m8 ( clk, E, D[29], Q[29] ) ;
endmodule
module ME_FREGA_1_32 ( clk, enable, D, Q ) ;
input clk, enable ;
input [31:0] D;
output [31:0] Q;
ME_BUF_C m20 ( enable, E ) ;
FREG_1Byte m0 ( clk, E, D[7:0], Q[7:0] ) ;
FREG_1Byte m1 ( clk, E, D[15:8], Q[15:8] ) ;
FREG_1Byte m2 ( clk, E, D[23:16], Q[23:16] ) ;
FREG_1Byte m3 ( clk, E, D[31:24], Q[31:24] ) ;
endmodule
module ME_FREG_H_32 ( clk, H, D, Q ) ;
input clk;
input [3:0] H;
input [31:0] D;
output [31:0] Q;
// rlee: note HOLD is active low
// N1Z000 gnd(GND);
// ASFFHA f00 ( .Q( Q[ 0] ), .D( D[ 0] ), .SM(GND), .SI(GND), .H( H[ 0] ),
// .CK( clk )) ;
// ASFFHA f01 ( .Q( Q[ 1] ), .D( D[ 1] ), .SM(GND), .SI(GND), .H( H[ 0] ),
// .CK( clk )) ;
// ASFFHA f02 ( .Q( Q[ 2] ), .D( D[ 2] ), .SM(GND), .SI(GND), .H( H[ 0] ),
// .CK( clk )) ;
// ASFFHA f03 ( .Q( Q[ 3] ), .D( D[ 3] ), .SM(GND), .SI(GND), .H( H[ 0] ),
// .CK( clk )) ;
// ASFFHA f04 ( .Q( Q[ 4] ), .D( D[ 4] ), .SM(GND), .SI(GND), .H( H[ 0] ),
// .CK( clk )) ;
// ASFFHA f05 ( .Q( Q[ 5] ), .D( D[ 5] ), .SM(GND), .SI(GND), .H( H[ 0] ),
// .CK( clk )) ;
// ASFFHA f06 ( .Q( Q[ 6] ), .D( D[ 6] ), .SM(GND), .SI(GND), .H( H[ 0] ),
// .CK( clk )) ;
// ASFFHA f07 ( .Q( Q[ 7] ), .D( D[ 7] ), .SM(GND), .SI(GND), .H( H[ 0] ),
// .CK( clk )) ;
// ASFFHA f08 ( .Q( Q[ 8] ), .D( D[ 8] ), .SM(GND), .SI(GND), .H( H[ 1] ),
// .CK( clk )) ;
// ASFFHA f09 ( .Q( Q[ 9] ), .D( D[ 9] ), .SM(GND), .SI(GND), .H( H[ 1] ),
// .CK( clk )) ;
// ASFFHA f10 ( .Q( Q[10] ), .D( D[10] ), .SM(GND), .SI(GND), .H( H[ 1] ),
// .CK( clk )) ;
// ASFFHA f11 ( .Q( Q[11] ), .D( D[11] ), .SM(GND), .SI(GND), .H( H[ 1] ),
// .CK( clk )) ;
// ASFFHA f12 ( .Q( Q[12] ), .D( D[12] ), .SM(GND), .SI(GND), .H( H[ 1] ),
// .CK( clk )) ;
// ASFFHA f13 ( .Q( Q[13] ), .D( D[13] ), .SM(GND), .SI(GND), .H( H[ 1] ),
// .CK( clk )) ;
// ASFFHA f14 ( .Q( Q[14] ), .D( D[14] ), .SM(GND), .SI(GND), .H( H[ 1] ),
// .CK( clk )) ;
// ASFFHA f15 ( .Q( Q[15] ), .D( D[15] ), .SM(GND), .SI(GND), .H( H[ 1] ),
// .CK( clk )) ;
// ASFFHA f16 ( .Q( Q[16] ), .D( D[16] ), .SM(GND), .SI(GND), .H( H[ 2] ),
// .CK( clk )) ;
// ASFFHA f17 ( .Q( Q[17] ), .D( D[17] ), .SM(GND), .SI(GND), .H( H[ 2] ),
// .CK( clk )) ;
// ASFFHA f18 ( .Q( Q[18] ), .D( D[18] ), .SM(GND), .SI(GND), .H( H[ 2] ),
// .CK( clk )) ;
// ASFFHA f19 ( .Q( Q[19] ), .D( D[19] ), .SM(GND), .SI(GND), .H( H[ 2] ),
// .CK( clk )) ;
// ASFFHA f20 ( .Q( Q[20] ), .D( D[20] ), .SM(GND), .SI(GND), .H( H[ 2] ),
// .CK( clk )) ;
// ASFFHA f21 ( .Q( Q[21] ), .D( D[21] ), .SM(GND), .SI(GND), .H( H[ 2] ),
// .CK( clk )) ;
// ASFFHA f22 ( .Q( Q[22] ), .D( D[22] ), .SM(GND), .SI(GND), .H( H[ 2] ),
// .CK( clk )) ;
// ASFFHA f23 ( .Q( Q[23] ), .D( D[23] ), .SM(GND), .SI(GND), .H( H[ 2] ),
// .CK( clk )) ;
// ASFFHA f24 ( .Q( Q[24] ), .D( D[24] ), .SM(GND), .SI(GND), .H( H[ 3] ),
// .CK( clk )) ;
// ASFFHA f25 ( .Q( Q[25] ), .D( D[25] ), .SM(GND), .SI(GND), .H( H[ 3] ),
// .CK( clk )) ;
// ASFFHA f26 ( .Q( Q[26] ), .D( D[26] ), .SM(GND), .SI(GND), .H( H[ 3] ),
// .CK( clk )) ;
// ASFFHA f27 ( .Q( Q[27] ), .D( D[27] ), .SM(GND), .SI(GND), .H( H[ 3] ),
// .CK( clk )) ;
// ASFFHA f28 ( .Q( Q[28] ), .D( D[28] ), .SM(GND), .SI(GND), .H( H[ 3] ),
// .CK( clk )) ;
// ASFFHA f29 ( .Q( Q[29] ), .D( D[29] ), .SM(GND), .SI(GND), .H( H[ 3] ),
// .CK( clk )) ;
// ASFFHA f30 ( .Q( Q[30] ), .D( D[30] ), .SM(GND), .SI(GND), .H( H[ 3] ),
// .CK( clk )) ;
// ASFFHA f31 ( .Q( Q[31] ), .D( D[31] ), .SM(GND), .SI(GND), .H( H[ 3] ),
// .CK( clk )) ;
Mflipflop f00 ( .out(Q[0]), .in(D[0]), .clock(clk), .enable_l(H[0]) );
Mflipflop f01 ( .out(Q[1]), .in(D[1]), .clock(clk), .enable_l(H[0]) );
Mflipflop f02 ( .out(Q[2]), .in(D[2]), .clock(clk), .enable_l(H[0]) );
Mflipflop f03 ( .out(Q[3]), .in(D[3]), .clock(clk), .enable_l(H[0]) );
Mflipflop f04 ( .out(Q[4]), .in(D[4]), .clock(clk), .enable_l(H[0]) );
Mflipflop f05 ( .out(Q[5]), .in(D[5]), .clock(clk), .enable_l(H[0]) );
Mflipflop f06 ( .out(Q[6]), .in(D[6]), .clock(clk), .enable_l(H[0]) );
Mflipflop f07 ( .out(Q[7]), .in(D[7]), .clock(clk), .enable_l(H[0]) );
Mflipflop f08 ( .out(Q[8]), .in(D[8]), .clock(clk), .enable_l(H[1]) );
Mflipflop f09 ( .out(Q[9]), .in(D[9]), .clock(clk), .enable_l(H[1]) );
Mflipflop f10 ( .out(Q[10]), .in(D[10]), .clock(clk), .enable_l(H[1]) );
Mflipflop f11 ( .out(Q[11]), .in(D[11]), .clock(clk), .enable_l(H[1]) );
Mflipflop f12 ( .out(Q[12]), .in(D[12]), .clock(clk), .enable_l(H[1]) );
Mflipflop f13 ( .out(Q[13]), .in(D[13]), .clock(clk), .enable_l(H[1]) );
Mflipflop f14 ( .out(Q[14]), .in(D[14]), .clock(clk), .enable_l(H[1]) );
Mflipflop f15 ( .out(Q[15]), .in(D[15]), .clock(clk), .enable_l(H[1]) );
Mflipflop f16 ( .out(Q[16]), .in(D[16]), .clock(clk), .enable_l(H[2]) );
Mflipflop f17 ( .out(Q[17]), .in(D[17]), .clock(clk), .enable_l(H[2]) );
Mflipflop f18 ( .out(Q[18]), .in(D[18]), .clock(clk), .enable_l(H[2]) );
Mflipflop f19 ( .out(Q[19]), .in(D[19]), .clock(clk), .enable_l(H[2]) );
Mflipflop f20 ( .out(Q[20]), .in(D[20]), .clock(clk), .enable_l(H[2]) );
Mflipflop f21 ( .out(Q[21]), .in(D[21]), .clock(clk), .enable_l(H[2]) );
Mflipflop f22 ( .out(Q[22]), .in(D[22]), .clock(clk), .enable_l(H[2]) );
Mflipflop f23 ( .out(Q[23]), .in(D[23]), .clock(clk), .enable_l(H[2]) );
Mflipflop f24 ( .out(Q[24]), .in(D[24]), .clock(clk), .enable_l(H[3]) );
Mflipflop f25 ( .out(Q[25]), .in(D[25]), .clock(clk), .enable_l(H[3]) );
Mflipflop f26 ( .out(Q[26]), .in(D[26]), .clock(clk), .enable_l(H[3]) );
Mflipflop f27 ( .out(Q[27]), .in(D[27]), .clock(clk), .enable_l(H[3]) );
Mflipflop f28 ( .out(Q[28]), .in(D[28]), .clock(clk), .enable_l(H[3]) );
Mflipflop f29 ( .out(Q[29]), .in(D[29]), .clock(clk), .enable_l(H[3]) );
Mflipflop f30 ( .out(Q[30]), .in(D[30]), .clock(clk), .enable_l(H[3]) );
Mflipflop f31 ( .out(Q[31]), .in(D[31]), .clock(clk), .enable_l(H[3]) );
endmodule
module ME_FREGA_1_64 ( clk, enable, D, Q ) ;
input clk, enable ;
input [63:0] D;
output [63:0] Q;
ME_INV_B m20 ( enable, _E ) ;
ME_INV_C m21 ( _E, E1 ) ;
ME_INV_C m22 ( _E, E2 ) ;
FREG_1Byte m0 ( clk, E1, D[7:0], Q[7:0] ) ;
FREG_1Byte m1 ( clk, E1, D[15:8], Q[15:8] ) ;
FREG_1Byte m2 ( clk, E1, D[23:16], Q[23:16] ) ;
FREG_1Byte m3 ( clk, E1, D[31:24], Q[31:24] ) ;
FREG_1Byte m4 ( clk, E2, D[39:32], Q[39:32] ) ;
FREG_1Byte m5 ( clk, E2, D[47:40], Q[47:40] ) ;
FREG_1Byte m6 ( clk, E2, D[55:48], Q[55:48] ) ;
FREG_1Byte m7 ( clk, E2, D[63:56], Q[63:56] ) ;
endmodule
// Meiko register macros
//
/* 2 input flip flop register library */
/* components followed by instances */
/* instances should be kept up to date with functional instances */
/* provided block of 1 2 4 8 32 cells to build registers from */
/* registers should also contain buffers to drive datapath lines */
module FREG_2bit ( clk, E, notA, A, d0, d1, Q ) ;
input clk, notA, A, d0, d1, E ;
output Q ;
wire x;
ME_NMUX2BA n0 ( .nota(notA), .a(A), .d0(d0), .d1(d1), .notX(x));
ME_FD1E f0 (.cp(clk), .te(E), .d(x), .qn(Q)) ;
endmodule
/* real instances start here */
// 4-bit reg with 2:1 mux built in
module ME_FREGA_2_4 ( clk, hold, S, d0, d1, Q ) ;
input clk, hold, S;
input [3:0] d0, d1;
output [3:0] Q;
// N1Z000 gnd (GND);
// AMUXFFA ff ( .DA0(d0[0]), .DA1(d0[1]), .DA2(d0[2]), .DA3(d0[3]),
// .DB0(d1[0]), .DB1(d1[1]), .DB2(d1[2]), .DB3(d1[3]),
// .CK(clk), .HLD(hold), .SM(GND), .SI(GND), .S(S),
// .DO0(Q[0]), .DO1(Q[1]), .DO2(Q[2]), .DO3(Q[3]) );
reg [3:0] mux_output;
wire enable_low;
always @ (S or d0 or d1)
case (S) // synopsys parallel_case full_case
0: mux_output = d0;
1: mux_output = d1;
default mux_output = 'bx;
endcase
assign enable_low = ~hold;
Mflipflop_4 f0 (.out(Q[3:0]), .din(mux_output[3:0]), .clock(clk), .enable_l(enable_low) );
endmodule
module ME_FREGA_2_32 ( clk, hold, S, d0, d1, Q ) ;
input clk, hold, S;
input [31:0] d0, d1;
output [31:0] Q;
// N1Z000 gnd (GND);
// AMUXFFA f0 ( .DA0(d0[0]), .DA1(d0[1]), .DA2(d0[2]), .DA3(d0[3]),
// .DB0(d1[0]), .DB1(d1[1]), .DB2(d1[2]), .DB3(d1[3]),
// .CK(clk), .HLD(hold), .SM(GND), .SI(GND), .S(S),
// .DO0(Q[0]), .DO1(Q[1]), .DO2(Q[2]), .DO3(Q[3]) );
//
// AMUXFFA f1 ( .DA0(d0[4]), .DA1(d0[5]), .DA2(d0[6]), .DA3(d0[7]),
// .DB0(d1[4]), .DB1(d1[5]), .DB2(d1[6]), .DB3(d1[7]),
// .CK(clk), .HLD(hold), .SM(GND), .SI(GND), .S(S),
// .DO0(Q[4]), .DO1(Q[5]), .DO2(Q[6]), .DO3(Q[7]) );
//
// AMUXFFA f2 ( .DA0(d0[8]), .DA1(d0[9]), .DA2(d0[10]), .DA3(d0[11]),
// .DB0(d1[8]), .DB1(d1[9]), .DB2(d1[10]), .DB3(d1[11]),
// .CK(clk), .HLD(hold), .SM(GND), .SI(GND), .S(S),
// .DO0(Q[8]), .DO1(Q[9]), .DO2(Q[10]), .DO3(Q[11]) );
//
// AMUXFFA f3 ( .DA0(d0[12]), .DA1(d0[13]), .DA2(d0[14]), .DA3(d0[15]),
// .DB0(d1[12]), .DB1(d1[13]), .DB2(d1[14]), .DB3(d1[15]),
// .CK(clk), .HLD(hold), .SM(GND), .SI(GND), .S(S),
// .DO0(Q[12]), .DO1(Q[13]), .DO2(Q[14]), .DO3(Q[15]) );
//
// AMUXFFA f4 ( .DA0(d0[16]), .DA1(d0[17]), .DA2(d0[18]), .DA3(d0[19]),
// .DB0(d1[16]), .DB1(d1[17]), .DB2(d1[18]), .DB3(d1[19]),
// .CK(clk), .HLD(hold), .SM(GND), .SI(GND), .S(S),
// .DO0(Q[16]), .DO1(Q[17]), .DO2(Q[18]), .DO3(Q[19]) );
//
// AMUXFFA f5 ( .DA0(d0[20]), .DA1(d0[21]), .DA2(d0[22]), .DA3(d0[23]),
// .DB0(d1[20]), .DB1(d1[21]), .DB2(d1[22]), .DB3(d1[23]),
// .CK(clk), .HLD(hold), .SM(GND), .SI(GND), .S(S),
// .DO0(Q[20]), .DO1(Q[21]), .DO2(Q[22]), .DO3(Q[23]) );
//
// AMUXFFA f6 ( .DA0(d0[24]), .DA1(d0[25]), .DA2(d0[26]), .DA3(d0[27]),
// .DB0(d1[24]), .DB1(d1[25]), .DB2(d1[26]), .DB3(d1[27]),
// .CK(clk), .HLD(hold), .SM(GND), .SI(GND), .S(S),
// .DO0(Q[24]), .DO1(Q[25]), .DO2(Q[26]), .DO3(Q[27]) );
//
// AMUXFFA f7 ( .DA0(d0[28]), .DA1(d0[29]), .DA2(d0[30]), .DA3(d0[31]),
// .DB0(d1[28]), .DB1(d1[29]), .DB2(d1[30]), .DB3(d1[31]),
// .CK(clk), .HLD(hold), .SM(GND), .SI(GND), .S(S),
// .DO0(Q[28]), .DO1(Q[29]), .DO2(Q[30]), .DO3(Q[31]) );
reg [31:0] mux_output;
wire enable_low;
always @ (S or d0 or d1)
case (S) // synopsys parallel_case full_case
0: mux_output[31:0] = d0[31:0];
1: mux_output[31:0] = d1[31:0];
default mux_output = 'bx;
endcase
assign enable_low = ~hold;
Mflipflop_32 f0 (.out(Q[31:0]), .din(mux_output[31:0]), .clock(clk), .enable_l(enable_low) );
endmodule
module ME_FREGA_2_58 ( clk, enable, A, d0, d1, Q ) ;
input clk, enable, A ;
input [57:0] d0, d1 ;
output [57:0] Q ;
ME_INV_C ia0 ( A, notA ) ;
ME_INV_B ia1 ( A, _A ) ;
ME_INV_C ba1 ( _A, Abuf1 ) ;
ME_INV_C ba2 ( _A, Abuf2 ) ;
ME_INV_B ie0 ( enable, _E ) ;
ME_INV_C ie1 ( _E, E1 ) ;
ME_INV_C ie2 ( _E, E2 ) ;
FREG_2byte f00 ( clk, E1, notA, Abuf1, d0[7:0], d1[7:0], Q[7:0] ) ;
FREG_2byte f01 ( clk, E1, notA, Abuf1, d0[15:8], d1[15:8], Q[15:8] ) ;
FREG_2byte f02 ( clk, E1, notA, Abuf1, d0[23:16], d1[23:16], Q[23:16] ) ;
FREG_2byte f03 ( clk, E1, notA, Abuf1, d0[31:24], d1[31:24], Q[31:24] ) ;
FREG_2byte m12 ( clk, E2, notA, Abuf2, d0[39:32], d1[39:32], Q[39:32] ) ;
FREG_2byte m13 ( clk, E2, notA, Abuf2, d0[47:40], d1[47:40], Q[47:40] ) ;
FREG_2byte m14 ( clk, E2, notA, Abuf2, d0[55:48], d1[55:48], Q[55:48] ) ;
FREG_2bit m15 ( clk, E2, notA, Abuf2, d0[56], d1[56], Q[56] ) ;
FREG_2bit m16 ( clk, E2, notA, Abuf2, d0[57], d1[57], Q[57] ) ;
endmodule
// Meiko register macros
//
/* 4 input flip flop register library */
/* components followed by instances */
/* instances should be kept up to date with functional instances */
/* components */
/* provided block of 1 8 cells to build registers from */
/* registers should also contain buffers to drive datapath lines */
module FREG_S_4Bit ( clk, E, A, B, d0, d1, d2, d3, Q, Qbuf ) ;
input clk, E, A, B, d0, d1, d2, d3 ;
output Q, Qbuf ;
ME_MUX4B n0 ( .a(A), .b(B), .d0(d0), .d1(d1), .d2(d2), .d3(d3), .z(x) );
ME_FD1E f0 ( .cp(clk), .te(E), .d(x), .q(Q), .qn(QN));
ME_INV_B b0 ( .a(QN), .x(Qbuf));
endmodule
module FREG_4Bit ( clk, E, A, B, d0, d1, d2, d3, Q ) ;
input clk, E, A, B, d0, d1, d2, d3 ;
output Q ;
ME_MUX4B n0 ( .a(A), .b(B), .d0(d0), .d1(d1), .d2(d2), .d3(d3), .z(x) );
ME_FD1E f0 ( .cp(clk), .te(E), .d(x), .q(Q));
endmodule
module FREG_4Byte ( clk, E, A, B, d0, d1, d2, d3, Q ) ;
input clk, E, A, B;
input [7:0] d0, d1, d2, d3 ;
output [7:0] Q ;
FREG_4Bit f0 ( clk, E, A, B, d0[0], d1[0], d2[0], d3[0], Q[0] ) ;
FREG_4Bit f1 ( clk, E, A, B, d0[1], d1[1], d2[1], d3[1], Q[1] ) ;
FREG_4Bit f2 ( clk, E, A, B, d0[2], d1[2], d2[2], d3[2], Q[2] ) ;
FREG_4Bit f3 ( clk, E, A, B, d0[3], d1[3], d2[3], d3[3], Q[3] ) ;
FREG_4Bit f4 ( clk, E, A, B, d0[4], d1[4], d2[4], d3[4], Q[4] ) ;
FREG_4Bit f5 ( clk, E, A, B, d0[5], d1[5], d2[5], d3[5], Q[5] ) ;
FREG_4Bit f6 ( clk, E, A, B, d0[6], d1[6], d2[6], d3[6], Q[6] ) ;
FREG_4Bit f7 ( clk, E, A, B, d0[7], d1[7], d2[7], d3[7], Q[7] ) ;
endmodule
/* real instances start here */
module ME_FREGA_4_13 ( clk, enable, A, B, d0, d1, d2, d3, Q ) ;
input clk, enable, A, B ;
input [12:0] d0, d1, d2, d3 ;
output [12:0] Q ;
ME_BUF_C m20 ( enable, E ) ;
ME_BUF_C m21 ( A, Abuf ) ;
ME_BUF_C m22 ( B, Bbuf ) ;
FREG_4Byte f1 ( clk, E, Abuf, Bbuf,
d0[7:0], d1[7:0], d2[7:0], d3[7:0], Q[7:0] ) ;
FREG_4Bit f3 ( clk, E, Abuf, Bbuf, d0[8], d1[8], d2[8], d3[8], Q[8] ) ;
FREG_4Bit f4 ( clk, E, Abuf, Bbuf, d0[9], d1[9], d2[9], d3[9], Q[9] ) ;
FREG_4Bit f5 ( clk, E, Abuf, Bbuf, d0[10], d1[10], d2[10], d3[10], Q[10] ) ;
FREG_4Bit f6 ( clk, E, Abuf, Bbuf, d0[11], d1[11], d2[11], d3[11], Q[11] ) ;
FREG_4Bit f7 ( clk, E, Abuf, Bbuf, d0[12], d1[12], d2[12], d3[12], Q[12] ) ;
endmodule
module ME_FREGA_S_4_13 ( clk, enable, A, B, d0, d1, d2, d3, Q, Qbuf) ;
input clk, enable, A, B ;
input [12:0] d0, d1, d2, d3 ;
output [12:0] Q, Qbuf;
ME_BUF_C m20 ( enable, E ) ;
ME_BUF_C m21 ( A, Abuf ) ;
ME_BUF_C m22 ( B, Bbuf ) ;
FREG_S_4Bit f0 ( clk, E, Abuf, Bbuf, d0[ 0], d1[ 0], d2[ 0], d3[ 0], Q[ 0], Qbuf[ 0] ) ;
FREG_S_4Bit f1 ( clk, E, Abuf, Bbuf, d0[ 1], d1[ 1], d2[ 1], d3[ 1], Q[ 1], Qbuf[ 1] ) ;
FREG_S_4Bit f2 ( clk, E, Abuf, Bbuf, d0[ 2], d1[ 2], d2[ 2], d3[ 2], Q[ 2], Qbuf[ 2] ) ;
FREG_S_4Bit f3 ( clk, E, Abuf, Bbuf, d0[ 3], d1[ 3], d2[ 3], d3[ 3], Q[ 3], Qbuf[ 3] ) ;
FREG_S_4Bit f4 ( clk, E, Abuf, Bbuf, d0[ 4], d1[ 4], d2[ 4], d3[ 4], Q[ 4], Qbuf[ 4] ) ;
FREG_S_4Bit f5 ( clk, E, Abuf, Bbuf, d0[ 5], d1[ 5], d2[ 5], d3[ 5], Q[ 5], Qbuf[ 5] ) ;
FREG_S_4Bit f6 ( clk, E, Abuf, Bbuf, d0[ 6], d1[ 6], d2[ 6], d3[ 6], Q[ 6], Qbuf[ 6] ) ;
FREG_S_4Bit f7 ( clk, E, Abuf, Bbuf, d0[ 7], d1[ 7], d2[ 7], d3[ 7], Q[ 7], Qbuf[ 7] ) ;
FREG_S_4Bit f8 ( clk, E, Abuf, Bbuf, d0[ 8], d1[ 8], d2[ 8], d3[ 8], Q[ 8], Qbuf[ 8] ) ;
FREG_S_4Bit f9 ( clk, E, Abuf, Bbuf, d0[ 9], d1[ 9], d2[ 9], d3[ 9], Q[ 9], Qbuf[ 9] ) ;
FREG_S_4Bit fa ( clk, E, Abuf, Bbuf, d0[10], d1[10], d2[10], d3[10], Q[10], Qbuf[10] ) ;
FREG_S_4Bit fb ( clk, E, Abuf, Bbuf, d0[11], d1[11], d2[11], d3[11], Q[11], Qbuf[11] ) ;
FREG_S_4Bit fc ( clk, E, Abuf, Bbuf, d0[12], d1[12], d2[12], d3[12], Q[12], Qbuf[12] ) ;
endmodule
// Meiko register macros
//
/* 5 input flip flop register library */
/* components followed by instances */
/* instances should be kept up to date with functional instances */
/* components */
/* provided block of 1 8 cells to build registers from */
/* registers should also contain buffers to drive datapath lines */
module FREG_S_5bit ( clk, E, A, B, C, d0, d1, d2, d3, d4, Q, Qbuf, QN) ;
input clk, E, A, B, C, d0, d1, d2, d3, d4 ;
output Q, Qbuf, QN ;
//ME_TIEOFF toff (vdd,);
ME_MUX4B m0 (.a(A), .b(B), .d0(d0), .d1(d1), .d2(d2), .d3(d3), .z(T0));
ME_NMUX2B n0 (.s(C), .a(T0), .b(d4), .z(x)) ;
ME_FD1E f0 (.cp(clk), .te(E), .d(x), .q(QN), .qn(Q));
ME_INV_B b0 (.a(QN), .x(Qbuf));
endmodule
module FREG_5bit ( clk, E, A, B, C, d0, d1, d2, d3, d4, Q, Qbuf) ;
input clk, E, A, B, C, d0, d1, d2, d3, d4 ;
output Q, Qbuf ;
ME_MUX4B m0 (.a(A), .b(B), .d0(d0), .d1(d1), .d2(d2), .d3(d3), .z(T0));
ME_NMUX2B n0 (.s(C), .a(T0), .b(d4), .z(x)) ;
ME_FD1E f0 (.cp(clk), .te(E), .d(x), .q(QN), .qn(Q));
ME_INV_B b0 (.a(QN), .x(Qbuf));
endmodule
module FREG_5byte ( clk, E, A, B, C, d0, d1, d2, d3, d4, Q, Qbuf) ;
input clk, E, A, B, C;
input [7:0] d0, d1, d2, d3, d4 ;
output [7:0] Q, Qbuf;
FREG_5bit f0 ( clk, E, A, B, C, d0[0], d1[0], d2[0], d3[0], d4[0], Q[0], Qbuf[0]) ;
FREG_5bit f1 ( clk, E, A, B, C, d0[1], d1[1], d2[1], d3[1], d4[1], Q[1], Qbuf[1]) ;
FREG_5bit f2 ( clk, E, A, B, C, d0[2], d1[2], d2[2], d3[2], d4[2], Q[2], Qbuf[2]) ;
FREG_5bit f3 ( clk, E, A, B, C, d0[3], d1[3], d2[3], d3[3], d4[3], Q[3], Qbuf[3]) ;
FREG_5bit f4 ( clk, E, A, B, C, d0[4], d1[4], d2[4], d3[4], d4[4], Q[4], Qbuf[4]) ;
FREG_5bit f5 ( clk, E, A, B, C, d0[5], d1[5], d2[5], d3[5], d4[5], Q[5], Qbuf[5]) ;
FREG_5bit f6 ( clk, E, A, B, C, d0[6], d1[6], d2[6], d3[6], d4[6], Q[6], Qbuf[6]) ;
FREG_5bit f7 ( clk, E, A, B, C, d0[7], d1[7], d2[7], d3[7], d4[7], Q[7], Qbuf[7]) ;
endmodule
/* real instances start here */
module ME_FREGA_5_58 ( clk, enable, A, B, C, d0, d1, d2, d3, d4, Q, Qbuf, notBSign) ;
input clk, enable, A, B, C ;
input [57:0] d0, d1, d2, d3, d4 ;
output [57:0] Q, Qbuf;
output notBSign;
ME_INV_B ie1 ( enable, _E1 ) ;
ME_INV_C ie2 ( _E1, E1 ) ;
ME_INV_C ie3 ( _E1, E2 ) ;
ME_INV_B ia0 ( A, _A ) ;
ME_INV_C ia1 ( _A, A1 ) ;
ME_INV_C ia2 ( _A, A2 ) ;
ME_INV_C ia3 ( _A, A3 ) ;
ME_INV_B ib0 ( B, _B ) ;
ME_INV_C ib1 ( _B, B1 ) ;
ME_INV_C ib2 ( _B, B2 ) ;
ME_INV_B ic0 ( C, _C ) ;
ME_INV_C ic1 ( _C, C1 ) ;
ME_INV_C ic2 ( _C, C2 ) ;
FREG_5byte f0 (clk, E1, A1, B1, C1,
d0[7:0], d1[7:0], d2[7:0], d3[7:0], d4[7:0], Q[7:0] ,Qbuf[7:0] );
FREG_5byte f1 (clk, E1, A1, B1, C1,
d0[15:8], d1[15:8], d2[15:8], d3[15:8], d4[15:8], Q[15:8] ,Qbuf[15:8] );
FREG_5byte f2 (clk, E1, A1, B1, C1,
d0[23:16],d1[23:16],d2[23:16],d3[23:16],d4[23:16],Q[23:16],Qbuf[23:16]);
FREG_5byte f3 (clk, E1, A2, B1, C1,
d0[31:24],d1[31:24],d2[31:24],d3[31:24],d4[31:24],Q[31:24],Qbuf[31:24]);
FREG_5byte f4 (clk, E2, A2, B2, C2,
d0[39:32],d1[39:32],d2[39:32],d3[39:32],d4[39:32],Q[39:32],Qbuf[39:32]);
FREG_5byte f5 (clk, E2, A2, B2, C2,
d0[47:40],d1[47:40],d2[47:40],d3[47:40],d4[47:40],Q[47:40],Qbuf[47:40]);
FREG_5byte f6 (clk, E2, A3, B2, C2,
d0[55:48],d1[55:48],d2[55:48],d3[55:48],d4[55:48],Q[55:48],Qbuf[55:48]);
FREG_5bit f7 (clk, E2, A3, B2, C2,
d0[56], d1[56], d2[56], d3[56], d4[56], Q[56] ,Qbuf[56]) ;
FREG_S_5bit f8 (clk, E2, A3, B2, C2,
d0[57], d1[57], d2[57], d3[57], d4[57], Q[57] ,Qbuf[57], notBSign) ;
endmodule
// Meiko register macros
//
/* 8 input flip flop register library */
/* components followed by instances */
/* instances should be kept up to date with functional instances */
/* components */
/* provided block of 1 8 cells to build registers from */
/* registers should also contain buffers to drive datapath lines */
module FREG_8bit ( clk, E, _A, _B, C, d0, d1, d2, d3, d4, d5, d6, d7, Q, Qbuf ) ;
input clk, E, _A, _B, C, d0, d1, d2, d3, d4, d5, d6, d7 ;
output Q, Qbuf ;
ME_INV_A i0 ( .a(_A), .x(A));
ME_INV_A i1 ( .a(_B), .x(B));
ME_MUX8B_B n0 (.a(A), .b(B), .c(C),
.d0(d0), .d1(d1), .d2(d2), .d3(d3),
.d4(d4), .d5(d5), .d6(d6), .d7(d7), .f(x));
ME_FD1E f0 (.cp(clk), .te(E), .d(x), .q(Q), .qn(QN));
ME_INV_B b0 (.a(QN), .x(Qbuf));
endmodule
module FREG_8bit_s ( clk, E, _A, _B, C, d0, d1, d2, d3, d4, d5, d6, d7, Q, Qbuf, QTs, Qs) ;
input clk, E, _A, _B, C, d0, d1, d2, d3, d4, d5, d6, d7 ;
output Q, Qbuf, QTs, Qs;
// Bit 56 is critical and so contains two extra latches which
// drive the rounding select value
ME_INV_A i0 ( _A, A);
ME_INV_A i1 ( _B, B);
ME_MUX8B_B n0 ( A, B, C, d0, d1, d2, d3, d4, d5, d6, d7, x );
ME_FD1E_B f0 ( clk, E, x, Q, QN);
ME_INV_B b0 ( QN, Qbuf);
ME_NMUX2B_B sm0 ( E, QNs, x, Ds );
ME_FD1_B sf0 ( clk, Ds, Qs, QNs);
ME_FD1E_B f1 ( clk, E, x, QTs, );
endmodule
module FREG_8byte ( clk, E, A, B, C, d0, d1, d2, d3, d4, d5, d6, d7, Q, Qbuf ) ;
input clk, E, A, B, C;
input [7:0] d0, d1, d2, d3, d4, d5, d6, d7 ;
output [7:0] Q, Qbuf ;
FREG_8bit f0 ( clk, E, A, B, C, d0[0], d1[0], d2[0], d3[0],
d4[0], d5[0], d6[0], d7[0], Q[0], Qbuf[0] ) ;
FREG_8bit f1 ( clk, E, A, B, C, d0[1], d1[1], d2[1], d3[1],
d4[1], d5[1], d6[1], d7[1], Q[1], Qbuf[1]) ;
FREG_8bit f2 ( clk, E, A, B, C, d0[2], d1[2], d2[2], d3[2],
d4[2], d5[2], d6[2], d7[2], Q[2], Qbuf[2]) ;
FREG_8bit f3 ( clk, E, A, B, C, d0[3], d1[3], d2[3], d3[3],
d4[3], d5[3], d6[3], d7[3], Q[3], Qbuf[3]) ;
FREG_8bit f4 ( clk, E, A, B, C, d0[4], d1[4], d2[4], d3[4],
d4[4], d5[4], d6[4], d7[4], Q[4], Qbuf[4]) ;
FREG_8bit f5 ( clk, E, A, B, C, d0[5], d1[5], d2[5], d3[5],
d4[5], d5[5], d6[5], d7[5], Q[5], Qbuf[5]) ;
FREG_8bit f6 ( clk, E, A, B, C, d0[6], d1[6], d2[6], d3[6],
d4[6], d5[6], d6[6], d7[6], Q[6], Qbuf[6]) ;
FREG_8bit f7 ( clk, E, A, B, C, d0[7], d1[7], d2[7], d3[7],
d4[7], d5[7], d6[7], d7[7], Q[7], Qbuf[7]) ;
endmodule
/* real instances start here */
module ME_FREGA_8_58 ( clk, enable, A, B, C, d0, d1, d2, d3, d4, d5, d6, d7, Q, Qbuf, QTs, Qs) ;
input clk, enable, A, B, C ;
input [57:0] d0, d1, d2, d3, d4, d5, d6, d7 ;
output [57:0] Q, Qbuf;
output QTs, Qs ;
ME_INV_C ie0 ( enable, _E ) ;
ME_INV_C ie1 ( _E, E1 ) ;
ME_INV_C ie2 ( _E, E2 ) ;
ME_INV_C ie3 ( _E, E3 ) ;
ME_INV_C ie4 ( _E, E4 ) ;
ME_INV_C m21 ( A, Abuf ) ;
ME_INV_C m22 ( B, Bbuf ) ;
ME_INV_B ic0 ( C, _C ) ;
ME_INV_C ic1 ( _C, C1 ) ;
ME_INV_C ic2 ( _C, C2 ) ;
FREG_8byte f00 (clk, E1, Abuf, Bbuf, C1,
d0[7:0], d1[7:0], d2[7:0], d3[7:0],
d4[7:0], d5[7:0], d6[7:0], d7[7:0], Q[7:0], Qbuf[7:0]) ;
FREG_8byte f01 (clk, E1, Abuf, Bbuf, C1,
d0[15:8], d1[15:8], d2[15:8], d3[15:8],
d4[15:8], d5[15:8], d6[15:8], d7[15:8], Q[15:8], Qbuf[15:8]);
FREG_8byte f02 (clk, E2, Abuf, Bbuf, C1,
d0[23:16], d1[23:16], d2[23:16], d3[23:16],
d4[23:16], d5[23:16], d6[23:16], d7[23:16],
Q[23:16], Qbuf[23:16]);
FREG_8byte f03 (clk, E2, Abuf, Bbuf, C1,
d0[31:24], d1[31:24], d2[31:24], d3[31:24],
d4[31:24], d5[31:24], d6[31:24], d7[31:24],
Q[31:24], Qbuf[31:24]);
FREG_8byte m12 (clk, E3, Abuf, Bbuf, C2,
d0[39:32], d1[39:32], d2[39:32], d3[39:32],
d4[39:32], d5[39:32], d6[39:32], d7[39:32],
Q[39:32], Qbuf[39:32]);
FREG_8byte m13 (clk, E3, Abuf, Bbuf, C2,
d0[47:40], d1[47:40], d2[47:40], d3[47:40],
d4[47:40], d5[47:40], d6[47:40], d7[47:40],
Q[47:40], Qbuf[47:40]);
FREG_8byte m14 (clk, E4, Abuf, Bbuf, C2,
d0[55:48], d1[55:48], d2[55:48], d3[55:48],
d4[55:48], d5[55:48], d6[55:48], d7[55:48],
Q[55:48], Qbuf[55:48]);
/* This is the special round bit */
FREG_8bit_s m15 (clk, E4, Abuf, Bbuf, C2,
d0[56], d1[56], d2[56], d3[56],
d4[56], d5[56], d6[56], d7[56], Q[56], Qbuf[56], QTs, Qs);
FREG_8bit m16 (clk, E4, Abuf, Bbuf, C2,
d0[57], d1[57], d2[57], d3[57],
d4[57], d5[57], d6[57], d7[57], Q[57], Qbuf[57]);
endmodule
// Meiko ymuxslice macros
//
... (truncated)
module ME_Ymux_Bit (S1, S2, S3, D1, D2, D3, Z);
input S1, S2, S3;
input D1, D2, D3;
output Z;
ME_NAND2 d0 (.a(S1), .b(D1), .z(t0));
ME_NAND2 d1 (.a(S2), .b(D2), .z(t1));
ME_NAND2 d2 (.a(S3), .b(D3), .z(t2));
ME_NAND3 d3 (.a(t0), .b(t1), .c(t2), .z(Z));
endmodule
module ME_YmuxSlice (notS1, notS2, notS3,
/* dhn--01/10/91 notS1A, notS2A, notS3A, */
D1, D2, D3,
Z);
input notS1, notS2, notS3;
/* dhn--01/10/91 input notS1A, notS2A, notS3A; */
input [55:0] D1, D2, D3;
output [55:0] Z;
ME_INV_D b1 (.a(notS1), .x(S1));
ME_INV_D b2 (.a(notS2), .x(S2));
| This page: |
Created: | Thu Aug 19 12:01:02 1999 |
| From: |
../../../sparc_v8/lib/rtl/me_cells.v
|