wire [31:00] cspace_mux
; // Control space read mux
// Expanded macro begin.
// cmux2(cspace_mux, 32, cspace_mux, afar_out, /* default */ brkpt_mux, sel_brkpt_mux)
function [32:1] fn_cspace_mux ;
input [32:1] in0_fn ;
input [32:1] in1_fn ;
input select_fn ;
reg [32:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
fn_cspace_mux = out_fn ;
end
endfunction
assign cspace_mux = fn_cspace_mux( afar_out, /* default */ brkpt_mux, sel_brkpt_mux) ;
// Expanded macro end.
// Expanded macro begin.
// cmux5d(pa_mux_rd, 32, pa_mux_rd, cache_stat, pamux_rd_sel[0], tlb_rd_out, pamux_rd_sel[1], tlb_rd_data_byp, pamux_rd_sel[2], cspace_mux, pamux_rd_sel[3], /* was afar */ dp_mux1_out, pamux_rd_sel[4])
function [32:1] fn_pa_mux_rd ;
input [32:1] in0_fn ;
input s0_fn ;
input [32:1] in1_fn ;
input s1_fn ;
input [32:1] in2_fn ;
input s2_fn ;
input [32:1] in3_fn ;
input s3_fn ;
input [32:1] in4_fn ;
input s4_fn ;
reg [32:1] out_fn ;
begin
case ({ pamux_rd_sel[4], pamux_rd_sel[3], pamux_rd_sel[2], pamux_rd_sel[1], pamux_rd_sel[0]}) /* synopsys parallel_case */
5'b00001: out_fn = in0_fn ;
5'b00010: out_fn = in1_fn ;
5'b00100: out_fn = in2_fn ;
5'b01000: out_fn = in3_fn ;
5'b10000: out_fn = in4_fn ;
default: out_fn = 65'hx;
endcase
fn_pa_mux_rd = out_fn ;
end
endfunction
assign pa_mux_rd = fn_pa_mux_rd( cache_stat, pamux_rd_sel[0], tlb_rd_out, pamux_rd_sel[1], tlb_rd_data_byp, pamux_rd_sel[2], cspace_mux, pamux_rd_sel[3], /* was afar */ dp_mux1_out, pamux_rd_sel[4]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( pamux_rd_sel[4]+ pamux_rd_sel[3]+ pamux_rd_sel[2]+ pamux_rd_sel[1]+ pamux_rd_sel[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( pamux_rd_sel[4]+ pamux_rd_sel[3]+ pamux_rd_sel[2]+ pamux_rd_sel[1]^ pamux_rd_sel[0]===1'bx)) begin
$display("### %m.pa_mux_rd: CMUX5D select error!\n");
$display(" pamux_rd_sel[4], pamux_rd_sel[3], pamux_rd_sel[2], pamux_rd_sel[1], pamux_rd_sel[0]=%0d%0d%0d%0d%0d\n", pamux_rd_sel[4], pamux_rd_sel[3], pamux_rd_sel[2], pamux_rd_sel[1], pamux_rd_sel[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/**************************************************************************/
/*** Performance Counters A & B ******************************************/
/*** ***/
/*** Both 32-bit counters have a silent roll-over. This incrementer ***/
/*** is controlled by the trigger for each counter (trig_a, trig_b). ***/
wire [31:00] pcntr_a_in
;
wire [31:00] pcntr_a_rslt
;
wire pcntr_a_hld
= iva_wp_sel & pipe_hold4mmu_dp ;
// Expanded macro begin.
// cmux2(pcntr_a_mux, 32, pcntr_a_in, pcntr_a_rslt, misc_in, ld_pcntr_a)
function [32:1] pcntr_a_mux ;
input [32:1] in0_fn ;
input [32:1] in1_fn ;
input select_fn ;
reg [32:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
pcntr_a_mux = out_fn ;
end
endfunction
assign pcntr_a_in = pcntr_a_mux( pcntr_a_rslt, misc_in, ld_pcntr_a) ;
// Expanded macro end.
wire [31:00] perf_cntr_a
;
MflipflopR_32 perf_cntr_a_32(perf_cntr_a,pcntr_a_in,ss_clock,pcntr_a_hld,ss_reset) ;
assign pcntr_a_rslt = perf_cntr_a + trig_a ;
/*** Performance Counter A carry out. implement as real carry out. ********/
assign pcntr_a_co = trig_a & (perf_cntr_a == 32'hffffffff) ;
wire [31:00] pcntr_b_in
;
wire [31:00] pcntr_b_rslt
;
// Expanded macro begin.
// cmux2(pcntr_b_mux, 32, pcntr_b_in, pcntr_b_rslt, misc_in, ld_pcntr_b)
function [32:1] pcntr_b_mux ;
input [32:1] in0_fn ;
input [32:1] in1_fn ;
input select_fn ;
reg [32:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
pcntr_b_mux = out_fn ;
end
endfunction
assign pcntr_b_in = pcntr_b_mux( pcntr_b_rslt, misc_in, ld_pcntr_b) ;
// Expanded macro end.
wire [31:00] perf_cntr_b
;
MflipflopR_32 perf_cntr_b_32(perf_cntr_b,pcntr_b_in,ss_clock,1'b0,ss_reset) ;
assign pcntr_b_rslt = perf_cntr_b + trig_b ;
/*** Performance Counter B carry out. implement as real carry out. ********/
assign pcntr_b_co = trig_b & (perf_cntr_b == 32'hffffffff) ;
/************************************************************************/
/*** Perf Cntr B load monitor (displays when loaded - for debug) ***/
// synopsys translate_off
always @(posedge ss_clock) begin
perf_a_display;
perf_b_display;
end
task perf_a_display;
if (trig_a) begin
$display("\n!!! Perf Cntr A loaded with : %0h\n",pcntr_a_rslt);
end
endtask
task perf_b_display;
if (trig_b) begin
$display("\n!!! Perf Cntr B loaded with : %0h\n",pcntr_b_rslt);
end
endtask
// synopsys translate_on
/**************************************************************************/
/*** Breakpoint address compare logic and register. ***********************/
/*** These registers are ONLY loaded by scan. ***********************/
/*****************************************************************************/
/* VA mask register definition PA = 0x1000.3018 */
/* +----------------+-----------+------------------------------------------+ */
/* | Mask.Rev # | reserved | Virtual Address Mask (see below) | */
/* +----------------+-----------+------------------------------------------+ */
/* 31 24 23 17 16 00 */
/*****************************************************************************/
/**********************************************************************************/
/***** Virtual Address field enable decode ***************************************/
/*** ***/
/*** 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ***/
/*** +-----+-----+-----+---+---+---+---+---+---+---+---+---+---+---+---+---+---+***/
/*** | T | S | R | N | M | L | K | J | I | H | G | F | E | D | C | B | A |***/
/*** |31:24|23:18|17:14| 13| 12| 11| 10| 09| 08| 07| 06| 05| 04| 03| 02| 01| 00|***/
/*** +-----+-----+-----+---+---+---+---+---+---+---+---+---+---+---+---+---+---+***/
/*** ***/
/*** The "not" bit (N-bit) is bit [17]. ***/
/*** ***/
/*** Enables A-I enable their respective fields for comparison. The N bit ***/
/*** is used to decode the 'compare not' function. The N bit affects ***/
/*** the range of VA[31:12]. ***/
/*** ***/
/*** When the N=0, normal comparisons are made. When N=1, the compare ***/
/*** result is inverted - so a 'hit' occurs when the addresses mismatch. ***/
/*** ***/
/*** Note: the enable for VA matching is in the control logic file. ***/
/**********************************************************************************/
wire [17:00] va_field_en
;
MflipflopR_18 va_field_en_ff_18(va_field_en,misc_in[17:0],ss_clock,vaf_en_hld,ss_reset) ;
wire [31:00] brk_pt_reg
;
MflipflopR_32 brk_pt_ff_32(brk_pt_reg,misc_in,ss_clock,va_bp_hld,ss_reset) ;
/*** VA breakpoint mux - Selects address for breakpoint compare *************/
/*** 00 - Physical Address ***/
/*** 01 - Virtual Instruction Address ***/
/*** 10 - Virtual Data Cache Address ***/
/*** 11 - I/O Address ***/
wire [31:00] va_brkpt_mux
;
wire [31:00] pa_brktpt
= {1'b0, pa_out[30:00]} ;
// Expanded macro begin.
// cmux4(vabrkpt_mux, 32, va_brkpt_mux, r_i_vaddr[31:00], r_d_vaddr[31:00], io_addr[31:00], pa_brktpt[31:00], va_src_sel[1:0])
function [32:1] vabrkpt_mux ;
input [32:1] in0_fn ;
input [32:1] in1_fn ;
input [32:1] in2_fn ;
input [32:1] in3_fn ;
input [1:0] select_fn ;
reg [32:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
2'b00: out_fn = in0_fn ;
2'b01: out_fn = in1_fn ;
2'b10: out_fn = in2_fn ;
2'b11: out_fn = in3_fn ;
default: out_fn = 65'hx;
endcase
vabrkpt_mux = out_fn ;
end
endfunction
assign va_brkpt_mux = vabrkpt_mux( r_i_vaddr[31:00], r_d_vaddr[31:00], io_addr[31:00], pa_brktpt[31:00], va_src_sel[1:0]) ;
// Expanded macro end.
/*** Virtual Address Breakpoint hit decode ***************************************/
wire va_hit_t
= ((brk_pt_reg[31:24] == va_brkpt_mux[31:24]) | ~va_field_en[16])
^ va_field_en[17] ;
wire va_hit_s
= ((brk_pt_reg[23:18] == va_brkpt_mux[23:18]) | ~va_field_en[15])
^ va_field_en[17] ;
wire va_hit_r
= ((brk_pt_reg[17:14] == va_brkpt_mux[17:14]) | ~va_field_en[14])
^ va_field_en[17] ;
wire va_hit_n
= ((brk_pt_reg[13] == va_brkpt_mux[13]) | ~va_field_en[13])
^ va_field_en[17] ;
wire va_hit_m
= ((brk_pt_reg[12] == va_brkpt_mux[12]) | ~va_field_en[12])
^ va_field_en[17] ;
wire va_hit_l
= (brk_pt_reg[11] == va_brkpt_mux[11]) | ~va_field_en[11];
wire va_hit_k
= (brk_pt_reg[10] == va_brkpt_mux[10]) | ~va_field_en[10];
wire va_hit_j
= (brk_pt_reg[09] == va_brkpt_mux[09]) | ~va_field_en[09];
wire va_hit_i
= (brk_pt_reg[08] == va_brkpt_mux[08]) | ~va_field_en[08];
wire va_hit_h
= (brk_pt_reg[07] == va_brkpt_mux[07]) | ~va_field_en[07];
wire va_hit_g
= (brk_pt_reg[06] == va_brkpt_mux[06]) | ~va_field_en[06];
wire va_hit_f
= (brk_pt_reg[05] == va_brkpt_mux[05]) | ~va_field_en[05];
wire va_hit_e
= (brk_pt_reg[04] == va_brkpt_mux[04]) | ~va_field_en[04];
wire va_hit_d
= (brk_pt_reg[03] == va_brkpt_mux[03]) | ~va_field_en[03];
wire va_hit_c
= (brk_pt_reg[02] == va_brkpt_mux[02]) | ~va_field_en[02];
wire va_hit_b
= (brk_pt_reg[01] == va_brkpt_mux[01]) | ~va_field_en[01];
wire va_hit_a
= (brk_pt_reg[00] == va_brkpt_mux[00]) | ~va_field_en[00];
assign brk_pt_hit = va_hit_t & va_hit_s & va_hit_r &
va_hit_n & va_hit_m & va_hit_l & va_hit_k &
va_hit_j & va_hit_i & va_hit_h & va_hit_g & va_hit_f &
va_hit_e & va_hit_d & va_hit_c & va_hit_b & va_hit_a ;
/**************************************************************************/
/*** Mux for reading performance counters and breakpoint regs ************/
/**************************************************************************/
/* The va_fld_pad HIGH order byte reflects the MASK and REVISION number */
/* The High order byte is 0x0 for the first tapeout version of */
/* */
/* va_fld_pad[31:24] version */
/* ----------------- ------------- */
/* 0x0 1.0 - First tapeout */
/* 0x11 1.1 - First tapeout 2nd version */
/* 0x20 2.0 - Second Tapeout */
/* 0x24 2.4 - Second Tapeout 5th version */
/* 0x25 2.5 - Second Tapeout 6th version */
/* 0x26 2.6 - Second Tapeout 7th version */
/* 0x30 3.0 - Third Tapeout */
/* 0x31 3.1 - Third Tapeout 2nd version */
/* 0x32 3.2 - Third Tapeout 3rd version */
/* 0x34 1.0 - Eagle Tapeout */
/* 0x35 1.1 - Eagle Tapeout (Metal only) */
/* reverted back to 0x34 id for 2.0 tapeout instead of 0x36 */
/* 0x34 2.0 - Eagle Tapeout */
/* 0x36 2.1 - Eagle Tapeout (Fix ram access) */
/* */
/**************************************************************************/
wire [31:00] va_fld_pad
= { 8'h36,6'b0, va_field_en } ;
// Expanded macro begin.
// cmux4(brkpt_mux, 32, brkpt_mux, perf_cntr_a, /* pa = 0x1000 3010 */ perf_cntr_b, /* pa = 0x1000 3014 */ va_fld_pad, /* pa = 0x1000 3018 */ brk_pt_reg, /* pa = 0x1000 301c */ pa_out[3:2])
function [32:1] fn_brkpt_mux ;
input [32:1] in0_fn ;
input [32:1] in1_fn ;
input [32:1] in2_fn ;
input [32:1] in3_fn ;
input [1:0] select_fn ;
reg [32:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
2'b00: out_fn = in0_fn ;
2'b01: out_fn = in1_fn ;
2'b10: out_fn = in2_fn ;
2'b11: out_fn = in3_fn ;
default: out_fn = 65'hx;
endcase
fn_brkpt_mux = out_fn ;
end
endfunction
assign brkpt_mux = fn_brkpt_mux( perf_cntr_a, /* pa = 0x1000 3010 */ perf_cntr_b, /* pa = 0x1000 3014 */ va_fld_pad, /* pa = 0x1000 3018 */ brk_pt_reg, /* pa = 0x1000 301c */ pa_out[3:2]) ;
// Expanded macro end.
/**************************************************************************/
/* scan out terminal */
// synopsys translate_off
wire dp_mmu_scan_out;
assign dp_mmu_scan_out = 1'bx;
// synopsys translate_on
endmodule
This page: |
Created: | Thu Aug 19 11:59:32 1999 |
| From: |
../../../sparc_v8/ssparc/mmu/dp_mmu/rtl/dp_mmu.v
|