1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
tlb_bits_mux = out_fn ;
end
endfunction
assign tlb_ptp_out = tlb_bits_mux( mmu_ptp_in, asi_ptp_in, sel_mdat_mux) ;
// Expanded macro end.
/***** Bits [40,31,24] of the TLB TAG input ****************************/
// Expanded macro begin.
// cmux2(asi_lvl_mux, 3, asi_lvl_in, misc_in[02:00], tlb_cam_reg[12:10], not_hld_cam_h)
function [3:1] asi_lvl_mux ;
input [3:1] in0_fn ;
input [3:1] in1_fn ;
input select_fn ;
reg [3:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
asi_lvl_mux = out_fn ;
end
endfunction
assign asi_lvl_in = asi_lvl_mux( misc_in[02:00], tlb_cam_reg[12:10], not_hld_cam_h) ;
// Expanded macro end.
// Expanded macro begin.
// cmux2(tlb_lvl_mux, 3, tlb_lvl_out[2:0], tlb_cam_lvl, /* Level input from tw sm.*/ asi_lvl_in, sel_mdat_mux)
function [ 3:1] tlb_lvl_mux ;
input [ 3:1] in0_fn ;
input [ 3:1] in1_fn ;
input select_fn ;
reg [ 3:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
tlb_lvl_mux = out_fn ;
end
endfunction
assign tlb_lvl_out[2:0] = tlb_lvl_mux( tlb_cam_lvl, /* Level input from tw sm.*/ asi_lvl_in, sel_mdat_mux) ;
// Expanded macro end.
/****** BIT [24:5] of TLB DATA INPUT ***********/
// remenber misc1_in will be concated into tlb_data_in
// Expanded macro begin.
// cmux2(asi_data_misc1_mux, 20, misc1_in, misc_in[26:07], tlb_data_reg[24:5], not_hld_ram)
function [20:1] asi_data_misc1_mux ;
input [20:1] in0_fn ;
input [20:1] in1_fn ;
input select_fn ;
reg [20:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
asi_data_misc1_mux = out_fn ;
end
endfunction
assign misc1_in = asi_data_misc1_mux( misc_in[26:07], tlb_data_reg[24:5], not_hld_ram) ;
// Expanded macro end.
/****** BIT [2:0] of TLB DATA INPUT *******/
// Expanded macro begin.
// cmux2(asi_data_misc2_mux, 3, misc2_in, misc_in[04:02], tlb_data_reg[2:0], not_hld_ram)
function [3:1] asi_data_misc2_mux ;
input [3:1] in0_fn ;
input [3:1] in1_fn ;
input select_fn ;
reg [3:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
asi_data_misc2_mux = out_fn ;
end
endfunction
assign misc2_in = asi_data_misc2_mux( misc_in[04:02], tlb_data_reg[2:0], not_hld_ram) ;
// Expanded macro end.
/***** Bits [27,26,25] of the TLB DATA input *****************/
// Expanded macro begin.
// cmux2(asi_data_lvl_mux, 3, asi_data_lvl_in, misc_in[31:29], tlb_data_reg[27:25], not_hld_ram)
function [3:1] asi_data_lvl_mux ;
input [3:1] in0_fn ;
input [3:1] in1_fn ;
input select_fn ;
reg [3:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
asi_data_lvl_mux = out_fn ;
end
endfunction
assign asi_data_lvl_in = asi_data_lvl_mux( misc_in[31:29], tlb_data_reg[27:25], not_hld_ram) ;
// Expanded macro end.
// Expanded macro begin.
// cmux2(tlb_sram_lvl_mux, 3, tlb_lvl_sram_out[2:0], tlb_ram_lvl, /* Level input from tw sm.*/ asi_data_lvl_in, sel_mdat_mux)
function [ 3:1] tlb_sram_lvl_mux ;
input [ 3:1] in0_fn ;
input [ 3:1] in1_fn ;
input select_fn ;
reg [ 3:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
tlb_sram_lvl_mux = out_fn ;
end
endfunction
assign tlb_lvl_sram_out[2:0] = tlb_sram_lvl_mux( tlb_ram_lvl, /* Level input from tw sm.*/ asi_data_lvl_in, sel_mdat_mux) ;
// Expanded macro end.
/* In swift context change to 8 bit */
/* Context mux (3:1) selecting either CXR, PA[9:2] or misc_in[11:4] */
/***** Bits [10:03] of the TLB TAG input ****************************/
wire [7:0] dpa_7to2
= { data_pa[7:2], 2'b0 };
// Expanded macro begin.
// cmux2(asi_cntx_mux, 8, asi_cntx_in, misc_in[11:4], tlb_cam_reg[21:14], /* Use Software bit alignment */ not_hld_cam_h)
function [8:1] asi_cntx_mux ;
input [8:1] in0_fn ;
input [8:1] in1_fn ;
input select_fn ;
reg [8:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
asi_cntx_mux = out_fn ;
end
endfunction
assign asi_cntx_in = asi_cntx_mux( misc_in[11:4], tlb_cam_reg[21:14], /* Use Software bit alignment */ not_hld_cam_h) ;
// Expanded macro end.
// Expanded macro begin.
// cmux3d(tlb_cntxt_mux, 8, tlb_cntxt_out, cxr[7:0], cxr_mux_sel[2], dpa_7to2, cxr_mux_sel[1], asi_cntx_in, cxr_mux_sel[0])
function [ 8:1] tlb_cntxt_mux ;
input [ 8:1] in0_fn ;
input s0_fn ;
input [ 8:1] in1_fn ;
input s1_fn ;
input [ 8:1] in2_fn ;
input s2_fn ;
reg [ 8:1] out_fn ;
begin
case ({ cxr_mux_sel[0], cxr_mux_sel[1], cxr_mux_sel[2]}) /* synopsys parallel_case */
3'b001: out_fn = in0_fn;
3'b010: out_fn = in1_fn;
3'b100: out_fn = in2_fn;
default: out_fn = 65'hx;
endcase
tlb_cntxt_mux = out_fn ;
end
endfunction
assign tlb_cntxt_out = tlb_cntxt_mux( cxr[7:0], cxr_mux_sel[2], dpa_7to2, cxr_mux_sel[1], asi_cntx_in, cxr_mux_sel[0]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( cxr_mux_sel[0]+ cxr_mux_sel[1]+ cxr_mux_sel[2] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( cxr_mux_sel[0]+ cxr_mux_sel[1]^ cxr_mux_sel[2]===1'bx)) begin
$display("### %m.tlb_cntxt_mux: CMUX3D select error!\n");
$display(" cxr_mux_sel[0], cxr_mux_sel[1], cxr_mux_sel[2]=%0d%0d%0d\n", cxr_mux_sel[0], cxr_mux_sel[1], cxr_mux_sel[2]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/***** Bits [39:32], [30:25], [23:18] of the TLB TAG input ***********/
/** LAYOUT NOTE: The bit ordering given above relates to the CAM *
** inputs. The datapath can either be layed-out *
** according to the CAM inputs, or the way the data is *
** input. The difference is in where the 2 level bits *
** are input, thereby Shifting the fields. */
/* TLB tag mux, selects between the different VA tags,
* and the output of the "tlb_pa_mux" (PA or mdata). */
/***** Bits [31:12] of the TLB TAG input ****************************/
/* split the 9 input mux to two mux ( 6 and 4 input ) */
/* vl_sel_in[4] is to selet uuper(mux_4) 5 input mux */
/* that is , if va_sel_in[5] == 1 , either upper */
/* of the CMUX6D have to be one */
wire [19:0] va_mux_adr_out;
// Expanded macro begin.
// cmux2(asi_va_mux, 20, asi_va_in, misc_in[31:12], tlb_cam_reg[41:22], not_hld_cam_h)
function [20:1] asi_va_mux ;
input [20:1] in0_fn ;
input [20:1] in1_fn ;
input select_fn ;
reg [20:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
asi_va_mux = out_fn ;
end
endfunction
assign asi_va_in = asi_va_mux( misc_in[31:12], tlb_cam_reg[41:22], not_hld_cam_h) ;
// Expanded macro end.
// Expanded macro begin.
// cmux4d(va_tag_mux_3, 20, va_mux_adr_out, r_i_vaddr[31:12], va_mux0_sel[0], r_d_vaddr[31:12], va_mux0_sel[1], asi_va_in, va_mux0_sel[2], wr_buf_3_out[31:12], va_mux0_sel[3])
function [ 20:1] va_tag_mux_3 ;
input [ 20:1] in0_fn ;
input s0_fn ;
input [ 20:1] in1_fn ;
input s1_fn ;
input [ 20:1] in2_fn ;
input s2_fn ;
input [ 20:1] in3_fn ;
input s3_fn ;
reg [ 20:1] out_fn ;
begin
case ({va_mux0_sel[3], va_mux0_sel[2], va_mux0_sel[1], va_mux0_sel[0]}) /* synopsys parallel_case */
4'b0001: out_fn = in0_fn;
4'b0010: out_fn = in1_fn;
4'b0100: out_fn = in2_fn;
4'b1000: out_fn = in3_fn;
default: out_fn = 65'hx;
endcase
va_tag_mux_3 = out_fn ;
end
endfunction
assign va_mux_adr_out = va_tag_mux_3( r_i_vaddr[31:12], va_mux0_sel[0], r_d_vaddr[31:12], va_mux0_sel[1], asi_va_in, va_mux0_sel[2], wr_buf_3_out[31:12], va_mux0_sel[3]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if ((va_mux0_sel[3]+ va_mux0_sel[2]+ va_mux0_sel[1]+ va_mux0_sel[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~(va_mux0_sel[3]+ va_mux0_sel[2]+ va_mux0_sel[1]^ va_mux0_sel[0]===1'bx)) begin
$display("### %m.va_tag_mux_3: CMUX4D select error!\n");
$display("va_mux0_sel[3], va_mux0_sel[2], va_mux0_sel[1], va_mux0_sel[0]=%0d%0d%0d%0d\n", va_mux0_sel[3], va_mux0_sel[2], va_mux0_sel[1], va_mux0_sel[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
// Expanded macro begin.
// cmux5d(va_tag_mux_4, 20, va_tag_mux_out, va_mux_adr_out, va_mux1_sel[0], data_pa[27:08], va_mux1_sel[1], i_vaddr[31:12], va_mux1_sel[2], d_vaddr[31:12], va_mux1_sel[3], io_addr[31:12], va_mux1_sel[4])
function [20:1] va_tag_mux_4 ;
input [20:1] in0_fn ;
input s0_fn ;
input [20:1] in1_fn ;
input s1_fn ;
input [20:1] in2_fn ;
input s2_fn ;
input [20:1] in3_fn ;
input s3_fn ;
input [20:1] in4_fn ;
input s4_fn ;
reg [20:1] out_fn ;
begin
case ({va_mux1_sel[4], va_mux1_sel[3], va_mux1_sel[2], va_mux1_sel[1], va_mux1_sel[0]}) /* synopsys parallel_case */
5'b00001: out_fn = in0_fn ;
5'b00010: out_fn = in1_fn ;
5'b00100: out_fn = in2_fn ;
5'b01000: out_fn = in3_fn ;
5'b10000: out_fn = in4_fn ;
default: out_fn = 65'hx;
endcase
va_tag_mux_4 = out_fn ;
end
endfunction
assign va_tag_mux_out = va_tag_mux_4( va_mux_adr_out, va_mux1_sel[0], data_pa[27:08], va_mux1_sel[1], i_vaddr[31:12], va_mux1_sel[2], d_vaddr[31:12], va_mux1_sel[3], io_addr[31:12], va_mux1_sel[4]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if ((va_mux1_sel[4]+va_mux1_sel[3]+va_mux1_sel[2]+va_mux1_sel[1]+va_mux1_sel[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~(va_mux1_sel[4]+va_mux1_sel[3]+va_mux1_sel[2]+va_mux1_sel[1]^va_mux1_sel[0]===1'bx)) begin
$display("### %m.va_tag_mux_4: CMUX5D select error!\n");
$display("va_mux1_sel[4],va_mux1_sel[3],va_mux1_sel[2],va_mux1_sel[1],va_mux1_sel[0]=%0d%0d%0d%0d%0d\n", va_mux1_sel[4],va_mux1_sel[3],va_mux1_sel[2],va_mux1_sel[1],va_mux1_sel[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/*** Added the I/D_PAR mux for selecting address when I/D_PAR is valid ***/
wire [30:00] par_mux1;
// Expanded macro begin.
// cmux2(par_mux1, 31, par_mux1, ipar, dpar, par_sel[0])
function [31:1] fn_par_mux1 ;
input [31:1] in0_fn ;
input [31:1] in1_fn ;
input select_fn ;
reg [31:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
fn_par_mux1 = out_fn ;
end
endfunction
assign par_mux1 = fn_par_mux1( ipar, dpar, par_sel[0]) ;
// Expanded macro end.
// switch 3 input mux to 2 input mux for layout
// Expanded macro begin.
// cmux2(par_mux2, 31, hack_par, bp_paddr1, /***** output from bp mux ******/ par_mux1, par_sel[1])
function [31:1] par_mux2 ;
input [31:1] in0_fn ;
input [31:1] in1_fn ;
input select_fn ;
reg [31:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
par_mux2 = out_fn ;
end
endfunction
assign hack_par = par_mux2( bp_paddr1, /***** output from bp mux ******/ par_mux1, par_sel[1]) ;
// Expanded macro end.
/**** generate par_mux 32 bit by adding msb to 0 ****/
/**** par_mux is used as a input of va_indx_mux *****/
wire [31:00] par_mux = { 1'b0, par_mux1 };
/* The "va_indx_mux" selects between the 3 different VA sources *****/
/* for the bits [31:12] that are used as indices during table walks.*/
/* -----Originally wanted to overlap this function -------------*****/
// Expanded macro begin.
// cmux4d(va_indx_mux, 32, va_mux, r_i_vaddr[31:00], va_mux_sel[0], r_d_vaddr[31:00], va_mux_sel[1], io_addr[31:00], va_mux_sel[2], wr_buf_3_out[31:00], va_mux_sel[3])
function [32:1] va_indx_mux ;
input [32:1] in0_fn ;
input s0_fn ;
input [32:1] in1_fn ;
input s1_fn ;
input [32:1] in2_fn ;
input s2_fn ;
input [32:1] in3_fn ;
input s3_fn ;
reg [32:1] out_fn ;
begin
case ({ va_mux_sel[3], va_mux_sel[2], va_mux_sel[1], va_mux_sel[0]}) /* synopsys parallel_case */
4'b0001: out_fn = in0_fn;
4'b0010: out_fn = in1_fn;
4'b0100: out_fn = in2_fn;
4'b1000: out_fn = in3_fn;
default: out_fn = 65'hx;
endcase
va_indx_mux = out_fn ;
end
endfunction
assign va_mux = va_indx_mux( r_i_vaddr[31:00], va_mux_sel[0], r_d_vaddr[31:00], va_mux_sel[1], io_addr[31:00], va_mux_sel[2], wr_buf_3_out[31:00], va_mux_sel[3]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( va_mux_sel[3]+ va_mux_sel[2]+ va_mux_sel[1]+ va_mux_sel[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( va_mux_sel[3]+ va_mux_sel[2]+ va_mux_sel[1]^ va_mux_sel[0]===1'bx)) begin
$display("### %m.va_indx_mux: CMUX4D select error!\n");
$display(" va_mux_sel[3], va_mux_sel[2], va_mux_sel[1], va_mux_sel[0]=%0d%0d%0d%0d\n", va_mux_sel[3], va_mux_sel[2], va_mux_sel[1], va_mux_sel[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/** LAYOUT NOTE: The tag_out is ordered to align with the CAM inputs. **/
/** This corresponds to the HARDWARE TAG representation. *************/
/* in swift va_tag_out is 42 bits */
assign va_tag_out = {tlb_vbit_out, tlb_lvl_out[2], va_tag_mux_out[19:12],
tlb_lvl_out[01],
va_tag_mux_out[11:06],
tlb_lvl_out[0],
va_tag_mux_out[05:0],
tlb_cntxt_out,
tlb_pro_bits,
tlb_sbit_out, tlb_io_bit_out, tlb_ptp_out,
tlb_cam_mbit};
/***************************************************************************/
/***************************************************************************/
/***** Context Register ** *****/
wire [7:0] cxr;
MflipflopR_8 tlb_cxr_8(cxr,misc_in[7:0],ss_clock,hld_cxr,ss_reset) ;
/*************************************************************************/
/* SFAR - Synchronous Fault Address Register. */
wire sfar_reset = ss_reset | (sfar_read & ~ss_scan_mode);
wire [31:0] sfar_in;
// Expanded macro begin.
// cmux2(sfar_mux, 32, sfar_in, r_d_vaddr, misc_in, sfar_write)
function [32:1] sfar_mux ;
input [32:1] in0_fn ;
input [32:1] in1_fn ;
input select_fn ;
reg [32:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
sfar_mux = out_fn ;
end
endfunction
assign sfar_in = sfar_mux(r_d_vaddr, misc_in, sfar_write) ;
// Expanded macro end.
wire [31:00] sfar;
MflipflopR_32 sfar_32( sfar, sfar_in, /* load SFAR from eitherDVA or MDATA*/ ss_clock,hld_sfar, /* load enable for SFAR*/ sfar_reset) ;
/***************************************************************************/
/**^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^**/
/***************************************************************************/
/***** End of DP_VA_CMUX.V logic in first part **/
/***************************************************************************/
/**+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++**/
/* */
/**+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++**/
/***************************************************************************/
/***** DP_PA_CMUX.V logic in this part **/
/***************************************************************************/
/**vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv**/
// tlb sram for asi read op
// wire [31:00] tlb_rd_data = {2'b0,tb_out,~tlb_rd_tag[1],tlb_rd_tag[1]};
// add this mux , if asi access to sram we return lvl bits of sram
// otherwise , we return pte portion only .....
// added
// asi_dcd6 --> will select tb_out[27:25] otherwise will be zero
wire [2:0] lvl_out = { (tb_out[27] & asi_dcd6),
(tb_out[26] & asi_dcd6),
(tb_out[25] & asi_dcd6) } ;
wire [31:00] tlb_rd_data = {2'b0,lvl_out,tb_out[24:0],~tlb_rd_tag[1],tlb_rd_tag[1]};
/*************************************************************************/
/* Register definitions */
/* CTPR - context table pointer register (17 bits) mdata[22:06] */
wire [17:0] ctpr_in = misc_in[23:06]; /* rename inputs */
wire [17:00] ctpr_out;
MflipflopR_18 ctpr_18( ctpr_out, ctpr_in, /* data loaded from the MDATA bus*/ ss_clock,hld_ctpr, /* load enable for CTPR*/ ss_reset) ;
wire [31:00] ctpr = {8'b0,ctpr_out,6'b0};
/* IBAR - I/O base address register (17 bits) mdata[26:10] */
wire [16:0] ibar_in = misc_in[26:10]; /* rename inputs */
wire [16:00] ibar_out;
MflipflopR_17 ibar_17( ibar_out, ibar_in, /* data loaded from the MDATA bus*/ ss_clock,hld_ibar, /* load enable for IBAR*/ ss_reset) ;
wire [31:00] ibar = {5'b0,ibar_out,10'b0};
/*************************************************************************/
/* AFAR - Asynchronous Fault Address Register. */
wire [30:0] afar_in;
// Expanded macro begin.
// cmux2(afar_mux, 31, afar_in, pa_out, misc_in[30:00], (afar_write | mfar_write))
function [31:1] afar_mux ;
input [31:1] in0_fn ;
input [31:1] in1_fn ;
input select_fn ;
reg [31:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
afar_mux = out_fn ;
end
endfunction
assign afar_in = afar_mux(pa_out, misc_in[30:00], (afar_write | mfar_write)) ;
// Expanded macro end.
wire [30:00] afar;
MflipflopR_31 afar_31( afar, afar_in, /* load AFAR from either PA or MDATA*/ ss_clock,hld_afar, /* load enable for AFAR*/ ss_reset) ;
/****************************-*-*-*-*-************************************/
/*************************************************************************/
/* MFAR - Msynchronous Fault Address Register. */
wire [30:00] mfar;
MflipflopR_31 mfar_reg_31( mfar, afar_in, /* load MFAR from either PA or MDATA*/ ss_clock,hld_mfar, /* load enable for MFAR*/ ss_reset) ;
assign odd_wd = mfar[2] ;
/****************************-*-*-*-*-************************************/
/************** this step to assign par to pa_out ****************/
assign pa_out = par; /* assign pa_out equal to par out */
/*** Mux select definitions - concatenations *****************************/
wire[3:0] bp_sel_30d = {bp_sel_30[1],io_walk,cpu_walk,bp_sel_30[0]};
wire[3:0] bp_sel_28d = {bp_sel_28[1],io_walk,cpu_walk,bp_sel_28[0]};
wire[2:0] bp_sel_21d = {io_walk,cpu_walk,bp_sel_21};
wire[3:0] bp_sel_20d = {bp_sel_20,ctpr_sel,bp_mux_sel0}; /* 4:1 selects */
wire[3:0] bp_sel_19d = {bp_sel_19,ctpr_sel,bp_mux_sel0}; /* 4:1 selects */
wire[3:0] bp_sel_18d = {bp_sel_18,ctpr_sel,bp_mux_sel0}; /* 4:1 selects */
wire[3:0] bp_sel_17d = {bp_sel_17,ctpr_sel,bp_mux_sel0}; /* 4:1 selects */
wire[3:0] bp_sel_16d = {bp_sel_16,ctpr_sel,bp_mux_sel0}; /* 4:1 selects */
wire[3:0] bp_sel_15d = {bp_sel_15,ctpr_sel,bp_mux_sel0}; /* 4:1 selects */
wire[3:0] bp_sel_14d = {bp_sel_14,ctpr_sel,bp_mux_sel0}; /* 4:1 selects */
wire[2:0] bp_sel_10d = {io_walk, ctpr_sel, bp_mux_sel0};
/* */
/***** PA[30] definition. ************************************************/
/* BYPASS_30 mux (4:1) provides addresses that bypass the TLB. */
// Expanded macro begin.
// cmux4d(bypass_30, 1, bp_paddr[30], va_mux[30], bp_sel_30d[0], /* combination of all V addr.*/ 1'b0, bp_sel_30d[1], /* table_walk selection.*/ ibar[26], bp_sel_30d[2], /* IO Base Address Reg output.*/ (boot_out_30 & bm_sel[1] ), bp_sel_30d[3])
function [ 1:1] bypass_30 ;
input [ 1:1] in0_fn ;
input s0_fn ;
input [ 1:1] in1_fn ;
input s1_fn ;
input [ 1:1] in2_fn ;
input s2_fn ;
input [ 1:1] in3_fn ;
input s3_fn ;
reg [ 1:1] out_fn ;
begin
case ({ bp_sel_30d[3], bp_sel_30d[2], bp_sel_30d[1], bp_sel_30d[0]}) /* synopsys parallel_case */
4'b0001: out_fn = in0_fn;
4'b0010: out_fn = in1_fn;
4'b0100: out_fn = in2_fn;
4'b1000: out_fn = in3_fn;
default: out_fn = 65'hx;
endcase
bypass_30 = out_fn ;
end
endfunction
assign bp_paddr[30] = bypass_30( va_mux[30], bp_sel_30d[0], /* combination of all V addr.*/ 1'b0, bp_sel_30d[1], /* table_walk selection.*/ ibar[26], bp_sel_30d[2], /* IO Base Address Reg output.*/ (boot_out_30 & bm_sel[1] ), bp_sel_30d[3]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( bp_sel_30d[3]+ bp_sel_30d[2]+ bp_sel_30d[1]+ bp_sel_30d[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( bp_sel_30d[3]+ bp_sel_30d[2]+ bp_sel_30d[1]^ bp_sel_30d[0]===1'bx)) begin
$display("### %m.bypass_30: CMUX4D select error!\n");
$display(" bp_sel_30d[3], bp_sel_30d[2], bp_sel_30d[1], bp_sel_30d[0]=%0d%0d%0d%0d\n", bp_sel_30d[3], bp_sel_30d[2], bp_sel_30d[1], bp_sel_30d[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/* select BOOT mode mux.*/
/* DPA_30 mux (2:1) selects between Bypass addr. and TLB addr. */
// Expanded macro begin.
// cmux2(dpa_30, 1, data_pa[30], tb_out[24], /* TLB data output (PTP or PTE)*/ hack_par[30], /* Bypass address*/ dpa_sel_b)
function [ 1:1] dpa_30 ;
input [ 1:1] in0_fn ;
input [ 1:1] in1_fn ;
input select_fn ;
reg [ 1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
dpa_30 = out_fn ;
end
endfunction
assign data_pa[30] = dpa_30( tb_out[24], /* TLB data output (PTP or PTE)*/ hack_par[30], /* Bypass address*/ dpa_sel_b) ;
// Expanded macro end.
/* DPA mux select (0 = tb_out).*/
/* */
/***** PA[29:28] definition. *********************************************/
/* BYPASS_28 mux (4:1) provides addresses that bypass the TLB. */
// ARAY
wire [1:0] bootAddr = {1'b1,bm_sel[1]} ;
// Expanded macro begin.
// cmux4d(bypass_28, 2, bp_paddr[29:28], va_mux[29:28], bp_sel_28d[0], /* combo of all Virtual addr.*/ 2'b0, bp_sel_28d[1], /* IO MMU Bypass bit selects "00".*/ ibar[25:24], bp_sel_28d[2], /* IO Base Address Reg output.*/ bootAddr[1:0], bp_sel_28d[3])
function [ 2:1] bypass_28 ;
input [ 2:1] in0_fn ;
input s0_fn ;
input [ 2:1] in1_fn ;
input s1_fn ;
input [ 2:1] in2_fn ;
input s2_fn ;
input [ 2:1] in3_fn ;
input s3_fn ;
reg [ 2:1] out_fn ;
begin
case ({ bp_sel_28d[3], bp_sel_28d[2], bp_sel_28d[1], bp_sel_28d[0]}) /* synopsys parallel_case */
4'b0001: out_fn = in0_fn;
4'b0010: out_fn = in1_fn;
4'b0100: out_fn = in2_fn;
4'b1000: out_fn = in3_fn;
default: out_fn = 65'hx;
endcase
bypass_28 = out_fn ;
end
endfunction
assign bp_paddr[29:28] = bypass_28( va_mux[29:28], bp_sel_28d[0], /* combo of all Virtual addr.*/ 2'b0, bp_sel_28d[1], /* IO MMU Bypass bit selects "00".*/ ibar[25:24], bp_sel_28d[2], /* IO Base Address Reg output.*/ bootAddr[1:0], bp_sel_28d[3]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( bp_sel_28d[3]+ bp_sel_28d[2]+ bp_sel_28d[1]+ bp_sel_28d[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( bp_sel_28d[3]+ bp_sel_28d[2]+ bp_sel_28d[1]^ bp_sel_28d[0]===1'bx)) begin
$display("### %m.bypass_28: CMUX4D select error!\n");
$display(" bp_sel_28d[3], bp_sel_28d[2], bp_sel_28d[1], bp_sel_28d[0]=%0d%0d%0d%0d\n", bp_sel_28d[3], bp_sel_28d[2], bp_sel_28d[1], bp_sel_28d[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/* force "11" if in BOOT MODE*/
/* DPA_28 mux (2:1) selects between Bypass addr. and TLB addr. */
// Expanded macro begin.
// cmux2(dpa_28, 2, data_pa[29:28], tb_out[23:22], /* TLB data output (PTP or PTE)*/ hack_par[29:28], /* Bypass address*/ dpa_sel_b)
function [ 2:1] dpa_28 ;
input [ 2:1] in0_fn ;
input [ 2:1] in1_fn ;
input select_fn ;
reg [ 2:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
dpa_28 = out_fn ;
end
endfunction
assign data_pa[29:28] = dpa_28( tb_out[23:22], /* TLB data output (PTP or PTE)*/ hack_par[29:28], /* Bypass address*/ dpa_sel_b) ;
// Expanded macro end.
/* DPA mux select (0 = tb_out).*/
/* */
/***** PA[27] definition. ************************************************/
/* BYPASS_27 mux (3:1) provides addresses that bypass the TLB. */
// Expanded macro begin.
// cmux3d(bypass_27, 1, bp_paddr[27], va_mux[27], /* combination of all Virtual addr.*/ bp_sel_21d[0], /* Bypass Mux selects (decoded above).*/ ctpr[23], /* Context Table Pointer Reg.*/ bp_sel_21d[1], /* Bypass Mux selects (decoded above).*/ ibar[23], /* IO Base Address Register output.*/ bp_sel_21d[2])
function [ 1:1] bypass_27 ;
input [ 1:1] in0_fn ;
input s0_fn ;
input [ 1:1] in1_fn ;
input s1_fn ;
input [ 1:1] in2_fn ;
input s2_fn ;
reg [ 1:1] out_fn ;
begin
case ({ /* IO Base Address Register output.*/ bp_sel_21d[2], /* Context Table Pointer Reg.*/ bp_sel_21d[1], /* combination of all Virtual addr.*/ bp_sel_21d[0]}) /* synopsys parallel_case */
3'b001: out_fn = in0_fn;
3'b010: out_fn = in1_fn;
3'b100: out_fn = in2_fn;
default: out_fn = 65'hx;
endcase
bypass_27 = out_fn ;
end
endfunction
assign bp_paddr[27] = bypass_27( va_mux[27], /* combination of all Virtual addr.*/ bp_sel_21d[0], /* Bypass Mux selects (decoded above).*/ ctpr[23], /* Context Table Pointer Reg.*/ bp_sel_21d[1], /* Bypass Mux selects (decoded above).*/ ibar[23], /* IO Base Address Register output.*/ bp_sel_21d[2]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( /* IO Base Address Register output.*/ bp_sel_21d[2]+ /* Context Table Pointer Reg.*/ bp_sel_21d[1]+ /* combination of all Virtual addr.*/ bp_sel_21d[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( /* IO Base Address Register output.*/ bp_sel_21d[2]+ /* Context Table Pointer Reg.*/ bp_sel_21d[1]^ /* combination of all Virtual addr.*/ bp_sel_21d[0]===1'bx)) begin
$display("### %m.bypass_27: CMUX3D select error!\n");
$display(" /* IO Base Address Register output.*/ bp_sel_21d[2], /* Context Table Pointer Reg.*/ bp_sel_21d[1], /* combination of all Virtual addr.*/ bp_sel_21d[0]=%0d%0d%0d\n", /* IO Base Address Register output.*/ bp_sel_21d[2], /* Context Table Pointer Reg.*/ bp_sel_21d[1], /* combination of all Virtual addr.*/ bp_sel_21d[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/* Bypass Mux selects (decoded above).*/
/* DPA_27 mux (2:1) selects between Bypass addr. and TLB addr. */
// Expanded macro begin.
// cmux2(dpa_27, 1, data_pa[27], tb_out[21], /* TLB data output (PTP or PTE)*/ hack_par[27], /* Bypass address*/ dpa_sel_b)
function [ 1:1] dpa_27 ;
input [ 1:1] in0_fn ;
input [ 1:1] in1_fn ;
input select_fn ;
reg [ 1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
dpa_27 = out_fn ;
end
endfunction
assign data_pa[27] = dpa_27( tb_out[21], /* TLB data output (PTP or PTE)*/ hack_par[27], /* Bypass address*/ dpa_sel_b) ;
// Expanded macro end.
/* DPA mux select (0 = tb_out).*/
/* */
/***** PA[26:24] definition. *********************************************/
/* BYPASS_24 mux (3:1) provides addresses that bypass the TLB. */
// Expanded macro begin.
// cmux3d(bypass_24, 3, bp_paddr[26:24], va_mux[26:24], /* combination of all Virtual addr.*/ bp_sel_21d[0], /* Bypass Mux selects (decoded above).*/ ctpr[22:20], /* Context Table Pointer Reg.*/ bp_sel_21d[1], /* Bypass Mux selects (decoded above).*/ ibar[22:20], /* IO Base Address Register output.*/ bp_sel_21d[2])
function [ 3:1] bypass_24 ;
input [ 3:1] in0_fn ;
input s0_fn ;
input [ 3:1] in1_fn ;
input s1_fn ;
input [ 3:1] in2_fn ;
input s2_fn ;
reg [ 3:1] out_fn ;
begin
case ({ /* IO Base Address Register output.*/ bp_sel_21d[2], /* Context Table Pointer Reg.*/ bp_sel_21d[1], /* combination of all Virtual addr.*/ bp_sel_21d[0]}) /* synopsys parallel_case */
3'b001: out_fn = in0_fn;
3'b010: out_fn = in1_fn;
3'b100: out_fn = in2_fn;
default: out_fn = 65'hx;
endcase
bypass_24 = out_fn ;
end
endfunction
assign bp_paddr[26:24] = bypass_24( va_mux[26:24], /* combination of all Virtual addr.*/ bp_sel_21d[0], /* Bypass Mux selects (decoded above).*/ ctpr[22:20], /* Context Table Pointer Reg.*/ bp_sel_21d[1], /* Bypass Mux selects (decoded above).*/ ibar[22:20], /* IO Base Address Register output.*/ bp_sel_21d[2]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( /* IO Base Address Register output.*/ bp_sel_21d[2]+ /* Context Table Pointer Reg.*/ bp_sel_21d[1]+ /* combination of all Virtual addr.*/ bp_sel_21d[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( /* IO Base Address Register output.*/ bp_sel_21d[2]+ /* Context Table Pointer Reg.*/ bp_sel_21d[1]^ /* combination of all Virtual addr.*/ bp_sel_21d[0]===1'bx)) begin
$display("### %m.bypass_24: CMUX3D select error!\n");
$display(" /* IO Base Address Register output.*/ bp_sel_21d[2], /* Context Table Pointer Reg.*/ bp_sel_21d[1], /* combination of all Virtual addr.*/ bp_sel_21d[0]=%0d%0d%0d\n", /* IO Base Address Register output.*/ bp_sel_21d[2], /* Context Table Pointer Reg.*/ bp_sel_21d[1], /* combination of all Virtual addr.*/ bp_sel_21d[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/* Bypass Mux selects (decoded above).*/
/* DPA_24 mux (2:1) selects between Bypass addr. and TLB addr. */
// Expanded macro begin.
// cmux2(dpa_24, 3, data_pa[26:24], tb_out[20:18], /* TLB data output (PTP or PTE)*/ hack_par[26:24], /* Bypass address*/ dpa_sel_b)
function [ 3:1] dpa_24 ;
input [ 3:1] in0_fn ;
input [ 3:1] in1_fn ;
input select_fn ;
reg [ 3:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
dpa_24 = out_fn ;
end
endfunction
assign data_pa[26:24] = dpa_24( tb_out[20:18], /* TLB data output (PTP or PTE)*/ hack_par[26:24], /* Bypass address*/ dpa_sel_b) ;
// Expanded macro end.
/* DPA mux select (0 = tb_out).*/
/* */
/***** PA[23:21] definition. *********************************************/
/* BYPASS_21 mux (3:1) provides addresses that bypass the TLB. */
// Expanded macro begin.
// cmux3d(bypass_21, 3, bp_paddr[23:21], va_mux[23:21], /* combination of all Virtual addr.*/ bp_sel_21d[0], /* Bypass Mux selects (decoded above).*/ ctpr[19:17], /* Context Table Pointer Reg.*/ bp_sel_21d[1], /* Bypass Mux selects (decoded above).*/ ibar[19:17], /* IO Base Address Register output.*/ bp_sel_21d[2])
function [ 3:1] bypass_21 ;
input [ 3:1] in0_fn ;
input s0_fn ;
input [ 3:1] in1_fn ;
input s1_fn ;
input [ 3:1] in2_fn ;
input s2_fn ;
reg [ 3:1] out_fn ;
begin
case ({ /* IO Base Address Register output.*/ bp_sel_21d[2], /* Context Table Pointer Reg.*/ bp_sel_21d[1], /* combination of all Virtual addr.*/ bp_sel_21d[0]}) /* synopsys parallel_case */
3'b001: out_fn = in0_fn;
3'b010: out_fn = in1_fn;
3'b100: out_fn = in2_fn;
default: out_fn = 65'hx;
endcase
bypass_21 = out_fn ;
end
endfunction
assign bp_paddr[23:21] = bypass_21( va_mux[23:21], /* combination of all Virtual addr.*/ bp_sel_21d[0], /* Bypass Mux selects (decoded above).*/ ctpr[19:17], /* Context Table Pointer Reg.*/ bp_sel_21d[1], /* Bypass Mux selects (decoded above).*/ ibar[19:17], /* IO Base Address Register output.*/ bp_sel_21d[2]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( /* IO Base Address Register output.*/ bp_sel_21d[2]+ /* Context Table Pointer Reg.*/ bp_sel_21d[1]+ /* combination of all Virtual addr.*/ bp_sel_21d[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( /* IO Base Address Register output.*/ bp_sel_21d[2]+ /* Context Table Pointer Reg.*/ bp_sel_21d[1]^ /* combination of all Virtual addr.*/ bp_sel_21d[0]===1'bx)) begin
$display("### %m.bypass_21: CMUX3D select error!\n");
$display(" /* IO Base Address Register output.*/ bp_sel_21d[2], /* Context Table Pointer Reg.*/ bp_sel_21d[1], /* combination of all Virtual addr.*/ bp_sel_21d[0]=%0d%0d%0d\n", /* IO Base Address Register output.*/ bp_sel_21d[2], /* Context Table Pointer Reg.*/ bp_sel_21d[1], /* combination of all Virtual addr.*/ bp_sel_21d[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/* Bypass Mux selects (decoded above).*/
/* DPA_21 mux (2:1) selects between Bypass addr. and TLB addr. */
// Expanded macro begin.
// cmux2(dpa_21, 3, data_pa[23:21], tb_out[17:15], /* TLB data output (PTP or PTE)*/ hack_par[23:21], /* Bypass address*/ dpa_sel_l1)
function [ 3:1] dpa_21 ;
input [ 3:1] in0_fn ;
input [ 3:1] in1_fn ;
input select_fn ;
reg [ 3:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
dpa_21 = out_fn ;
end
endfunction
assign data_pa[23:21] = dpa_21( tb_out[17:15], /* TLB data output (PTP or PTE)*/ hack_par[23:21], /* Bypass address*/ dpa_sel_l1) ;
// Expanded macro end.
/* DPA mux select (0 = tb_out).*/
/* */
/***** PA[20] definition. ************************************************/
/* BYPASS_20 mux (4:1) provides addresses that bypass the TLB. */
// Expanded macro begin.
// cmux4d(bypass_20, 1, bp_paddr[20], va_mux[20], bp_sel_20d[0], /* combination of all Virtual addr.*/ ctpr[16], bp_sel_20d[1], /* Context Table Pointer Reg.*/ ibar[16], bp_sel_20d[2], /* IO Base Address Register output.*/ io_addr[30], bp_sel_20d[3])
function [ 1:1] bypass_20 ;
input [ 1:1] in0_fn ;
input s0_fn ;
input [ 1:1] in1_fn ;
input s1_fn ;
input [ 1:1] in2_fn ;
input s2_fn ;
input [ 1:1] in3_fn ;
input s3_fn ;
reg [ 1:1] out_fn ;
begin
case ({ bp_sel_20d[3], bp_sel_20d[2], bp_sel_20d[1], bp_sel_20d[0]}) /* synopsys parallel_case */
4'b0001: out_fn = in0_fn;
4'b0010: out_fn = in1_fn;
4'b0100: out_fn = in2_fn;
4'b1000: out_fn = in3_fn;
default: out_fn = 65'hx;
endcase
bypass_20 = out_fn ;
end
endfunction
assign bp_paddr[20] = bypass_20( va_mux[20], bp_sel_20d[0], /* combination of all Virtual addr.*/ ctpr[16], bp_sel_20d[1], /* Context Table Pointer Reg.*/ ibar[16], bp_sel_20d[2], /* IO Base Address Register output.*/ io_addr[30], bp_sel_20d[3]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( bp_sel_20d[3]+ bp_sel_20d[2]+ bp_sel_20d[1]+ bp_sel_20d[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( bp_sel_20d[3]+ bp_sel_20d[2]+ bp_sel_20d[1]^ bp_sel_20d[0]===1'bx)) begin
$display("### %m.bypass_20: CMUX4D select error!\n");
$display(" bp_sel_20d[3], bp_sel_20d[2], bp_sel_20d[1], bp_sel_20d[0]=%0d%0d%0d%0d\n", bp_sel_20d[3], bp_sel_20d[2], bp_sel_20d[1], bp_sel_20d[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/* IO virtual address bit [30].*/
/* DPA_20 mux (2:1) selects between Bypass addr. and TLB addr. */
// Expanded macro begin.
// cmux2(dpa_20, 1, data_pa[20], tb_out[14], /* TLB data output (PTP or PTE)*/ hack_par[20], /* Bypass address*/ dpa_sel_l1)
function [ 1:1] dpa_20 ;
input [ 1:1] in0_fn ;
input [ 1:1] in1_fn ;
input select_fn ;
reg [ 1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
dpa_20 = out_fn ;
end
endfunction
assign data_pa[20] = dpa_20( tb_out[14], /* TLB data output (PTP or PTE)*/ hack_par[20], /* Bypass address*/ dpa_sel_l1) ;
// Expanded macro end.
/* DPA mux select (0 = tb_out).*/
/* */
/***** PA[19] definition. ************************************************/
/* BYPASS_19 mux (4:1) provides addresses that bypass the TLB. */
// Expanded macro begin.
// cmux4d(bypass_19, 1, bp_paddr[19], va_mux[19], bp_sel_19d[0], /* combination of all Virtual addr.*/ ctpr[15], bp_sel_19d[1], /* Context Table Pointer Reg.*/ ibar[15], bp_sel_19d[2], /* IO Base Address Register output.*/ io_addr[29], bp_sel_19d[3])
function [ 1:1] bypass_19 ;
input [ 1:1] in0_fn ;
input s0_fn ;
input [ 1:1] in1_fn ;
input s1_fn ;
input [ 1:1] in2_fn ;
input s2_fn ;
input [ 1:1] in3_fn ;
input s3_fn ;
reg [ 1:1] out_fn ;
begin
case ({ bp_sel_19d[3], bp_sel_19d[2], bp_sel_19d[1], bp_sel_19d[0]}) /* synopsys parallel_case */
4'b0001: out_fn = in0_fn;
4'b0010: out_fn = in1_fn;
| This page: |
Created: | Thu Aug 19 11:59:29 1999 |
| From: |
../../../sparc_v8/ssparc/mmu/dp_mmu/rtl/dp_mmu.v
|