4'b0100: out_fn = in2_fn;
4'b1000: out_fn = in3_fn;
default: out_fn = 65'hx;
endcase
bypass_19 = out_fn ;
end
endfunction
assign bp_paddr[19] = bypass_19( va_mux[19], bp_sel_19d[0], /* combination of all Virtual addr.*/ ctpr[15], bp_sel_19d[1], /* Context Table Pointer Reg.*/ ibar[15], bp_sel_19d[2], /* IO Base Address Register output.*/ io_addr[29], bp_sel_19d[3]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( bp_sel_19d[3]+ bp_sel_19d[2]+ bp_sel_19d[1]+ bp_sel_19d[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( bp_sel_19d[3]+ bp_sel_19d[2]+ bp_sel_19d[1]^ bp_sel_19d[0]===1'bx)) begin
$display("### %m.bypass_19: CMUX4D select error!\n");
$display(" bp_sel_19d[3], bp_sel_19d[2], bp_sel_19d[1], bp_sel_19d[0]=%0d%0d%0d%0d\n", bp_sel_19d[3], bp_sel_19d[2], bp_sel_19d[1], bp_sel_19d[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/* IO virtual address bit [29].*/
/* DPA_19 mux (2:1) selects between Bypass addr. and TLB addr. */
// Expanded macro begin.
// cmux2(dpa_19, 1, data_pa[19], tb_out[13], /* TLB data output (PTP or PTE)*/ hack_par[19], /* Bypass address*/ dpa_sel_l1)
function [ 1:1] dpa_19 ;
input [ 1:1] in0_fn ;
input [ 1:1] in1_fn ;
input select_fn ;
reg [ 1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
dpa_19 = out_fn ;
end
endfunction
assign data_pa[19] = dpa_19( tb_out[13], /* TLB data output (PTP or PTE)*/ hack_par[19], /* Bypass address*/ dpa_sel_l1) ;
// Expanded macro end.
/* DPA mux select (0 = tb_out).*/
/* */
/***** PA[18] definition. ************************************************/
/* BYPASS_18 mux (4:1) provides addresses that bypass the TLB. */
// Expanded macro begin.
// cmux4d(bypass_18, 1, bp_paddr[18], va_mux[18], bp_sel_18d[0], /* combo of all Virtual addr.*/ ctpr[14], bp_sel_18d[1], /* Context Table Pointer Reg.*/ ibar[14], bp_sel_18d[2], /* IO Base Address Reg output.*/ io_addr[28], bp_sel_18d[3])
function [ 1:1] bypass_18 ;
input [ 1:1] in0_fn ;
input s0_fn ;
input [ 1:1] in1_fn ;
input s1_fn ;
input [ 1:1] in2_fn ;
input s2_fn ;
input [ 1:1] in3_fn ;
input s3_fn ;
reg [ 1:1] out_fn ;
begin
case ({ bp_sel_18d[3], bp_sel_18d[2], bp_sel_18d[1], bp_sel_18d[0]}) /* synopsys parallel_case */
4'b0001: out_fn = in0_fn;
4'b0010: out_fn = in1_fn;
4'b0100: out_fn = in2_fn;
4'b1000: out_fn = in3_fn;
default: out_fn = 65'hx;
endcase
bypass_18 = out_fn ;
end
endfunction
assign bp_paddr[18] = bypass_18( va_mux[18], bp_sel_18d[0], /* combo of all Virtual addr.*/ ctpr[14], bp_sel_18d[1], /* Context Table Pointer Reg.*/ ibar[14], bp_sel_18d[2], /* IO Base Address Reg output.*/ io_addr[28], bp_sel_18d[3]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( bp_sel_18d[3]+ bp_sel_18d[2]+ bp_sel_18d[1]+ bp_sel_18d[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( bp_sel_18d[3]+ bp_sel_18d[2]+ bp_sel_18d[1]^ bp_sel_18d[0]===1'bx)) begin
$display("### %m.bypass_18: CMUX4D select error!\n");
$display(" bp_sel_18d[3], bp_sel_18d[2], bp_sel_18d[1], bp_sel_18d[0]=%0d%0d%0d%0d\n", bp_sel_18d[3], bp_sel_18d[2], bp_sel_18d[1], bp_sel_18d[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/* IO virtual address bit [28].*/
/* DPA_18 mux (2:1) selects between Bypass addr. and TLB addr. */
// Expanded macro begin.
// cmux2(dpa_18, 1, data_pa[18], tb_out[12], /* TLB data output (PTP or PTE)*/ hack_par[18], /* Bypass address*/ dpa_sel_l1)
function [ 1:1] dpa_18 ;
input [ 1:1] in0_fn ;
input [ 1:1] in1_fn ;
input select_fn ;
reg [ 1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
dpa_18 = out_fn ;
end
endfunction
assign data_pa[18] = dpa_18( tb_out[12], /* TLB data output (PTP or PTE)*/ hack_par[18], /* Bypass address*/ dpa_sel_l1) ;
// Expanded macro end.
/* DPA mux select (0 = tb_out).*/
/* */
/***** PA[17] definition. ************************************************/
/* BYPASS_17 mux (4:1) provides addresses that bypass the TLB. */
// Expanded macro begin.
// cmux4d(bypass_17, 1, bp_paddr[17], va_mux[17], bp_sel_17d[0], /* combo of all Virtual addr.*/ ctpr[13], bp_sel_17d[1], /* Context Table Pointer Reg.*/ ibar[13], bp_sel_17d[2], /* IO Base Address Reg output.*/ io_addr[27], bp_sel_17d[3])
function [ 1:1] bypass_17 ;
input [ 1:1] in0_fn ;
input s0_fn ;
input [ 1:1] in1_fn ;
input s1_fn ;
input [ 1:1] in2_fn ;
input s2_fn ;
input [ 1:1] in3_fn ;
input s3_fn ;
reg [ 1:1] out_fn ;
begin
case ({ bp_sel_17d[3], bp_sel_17d[2], bp_sel_17d[1], bp_sel_17d[0]}) /* synopsys parallel_case */
4'b0001: out_fn = in0_fn;
4'b0010: out_fn = in1_fn;
4'b0100: out_fn = in2_fn;
4'b1000: out_fn = in3_fn;
default: out_fn = 65'hx;
endcase
bypass_17 = out_fn ;
end
endfunction
assign bp_paddr[17] = bypass_17( va_mux[17], bp_sel_17d[0], /* combo of all Virtual addr.*/ ctpr[13], bp_sel_17d[1], /* Context Table Pointer Reg.*/ ibar[13], bp_sel_17d[2], /* IO Base Address Reg output.*/ io_addr[27], bp_sel_17d[3]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( bp_sel_17d[3]+ bp_sel_17d[2]+ bp_sel_17d[1]+ bp_sel_17d[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( bp_sel_17d[3]+ bp_sel_17d[2]+ bp_sel_17d[1]^ bp_sel_17d[0]===1'bx)) begin
$display("### %m.bypass_17: CMUX4D select error!\n");
$display(" bp_sel_17d[3], bp_sel_17d[2], bp_sel_17d[1], bp_sel_17d[0]=%0d%0d%0d%0d\n", bp_sel_17d[3], bp_sel_17d[2], bp_sel_17d[1], bp_sel_17d[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/* IO virtual address bit [27].*/
/* DPA_17 mux (2:1) selects between Bypass addr. and TLB addr. */
// Expanded macro begin.
// cmux2(dpa_17, 1, data_pa[17], tb_out[11], /* TLB data output (PTP or PTE)*/ hack_par[17], /* Bypass address*/ dpa_sel_l2)
function [ 1:1] dpa_17 ;
input [ 1:1] in0_fn ;
input [ 1:1] in1_fn ;
input select_fn ;
reg [ 1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
dpa_17 = out_fn ;
end
endfunction
assign data_pa[17] = dpa_17( tb_out[11], /* TLB data output (PTP or PTE)*/ hack_par[17], /* Bypass address*/ dpa_sel_l2) ;
// Expanded macro end.
/* DPA mux select (0 = tb_out).*/
/* */
/***** PA[16] definition. ************************************************/
/* BYPASS_16 mux (4:1) provides addresses that bypass the TLB. */
// Expanded macro begin.
// cmux4d(bypass_16, 1, bp_paddr[16], va_mux[16], bp_sel_16d[0], /* combo of all Virtual addr.*/ ctpr[12], bp_sel_16d[1], /* Context Table Pointer Reg.*/ ibar[12], bp_sel_16d[2], /* IO Base Address Reg output.*/ io_addr[26], bp_sel_16d[3])
function [ 1:1] bypass_16 ;
input [ 1:1] in0_fn ;
input s0_fn ;
input [ 1:1] in1_fn ;
input s1_fn ;
input [ 1:1] in2_fn ;
input s2_fn ;
input [ 1:1] in3_fn ;
input s3_fn ;
reg [ 1:1] out_fn ;
begin
case ({ bp_sel_16d[3], bp_sel_16d[2], bp_sel_16d[1], bp_sel_16d[0]}) /* synopsys parallel_case */
4'b0001: out_fn = in0_fn;
4'b0010: out_fn = in1_fn;
4'b0100: out_fn = in2_fn;
4'b1000: out_fn = in3_fn;
default: out_fn = 65'hx;
endcase
bypass_16 = out_fn ;
end
endfunction
assign bp_paddr[16] = bypass_16( va_mux[16], bp_sel_16d[0], /* combo of all Virtual addr.*/ ctpr[12], bp_sel_16d[1], /* Context Table Pointer Reg.*/ ibar[12], bp_sel_16d[2], /* IO Base Address Reg output.*/ io_addr[26], bp_sel_16d[3]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( bp_sel_16d[3]+ bp_sel_16d[2]+ bp_sel_16d[1]+ bp_sel_16d[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( bp_sel_16d[3]+ bp_sel_16d[2]+ bp_sel_16d[1]^ bp_sel_16d[0]===1'bx)) begin
$display("### %m.bypass_16: CMUX4D select error!\n");
$display(" bp_sel_16d[3], bp_sel_16d[2], bp_sel_16d[1], bp_sel_16d[0]=%0d%0d%0d%0d\n", bp_sel_16d[3], bp_sel_16d[2], bp_sel_16d[1], bp_sel_16d[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/* IO virtual address bit [26].*/
/* DPA_16 mux (2:1) selects between Bypass addr. and TLB addr. */
// Expanded macro begin.
// cmux2(dpa_16, 1, data_pa[16], tb_out[10], /* TLB data output (PTP or PTE)*/ hack_par[16], /* Bypass address*/ dpa_sel_l2)
function [ 1:1] dpa_16 ;
input [ 1:1] in0_fn ;
input [ 1:1] in1_fn ;
input select_fn ;
reg [ 1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
dpa_16 = out_fn ;
end
endfunction
assign data_pa[16] = dpa_16( tb_out[10], /* TLB data output (PTP or PTE)*/ hack_par[16], /* Bypass address*/ dpa_sel_l2) ;
// Expanded macro end.
/* DPA mux select (0 = tb_out).*/
/* */
/***** PA[15] definition. ************************************************/
/* BYPASS_15 mux (4:1) provides addresses that bypass the TLB. */
// Expanded macro begin.
// cmux4d(bypass_15, 1, bp_paddr[15], va_mux[15], bp_sel_15d[0], /* combo of all Virtual addr.*/ ctpr[11], bp_sel_15d[1], /* Context Table Pointer Reg.*/ ibar[11], bp_sel_15d[2], /* IO Base Address Reg output.*/ io_addr[25], bp_sel_15d[3])
function [ 1:1] bypass_15 ;
input [ 1:1] in0_fn ;
input s0_fn ;
input [ 1:1] in1_fn ;
input s1_fn ;
input [ 1:1] in2_fn ;
input s2_fn ;
input [ 1:1] in3_fn ;
input s3_fn ;
reg [ 1:1] out_fn ;
begin
case ({ bp_sel_15d[3], bp_sel_15d[2], bp_sel_15d[1], bp_sel_15d[0]}) /* synopsys parallel_case */
4'b0001: out_fn = in0_fn;
4'b0010: out_fn = in1_fn;
4'b0100: out_fn = in2_fn;
4'b1000: out_fn = in3_fn;
default: out_fn = 65'hx;
endcase
bypass_15 = out_fn ;
end
endfunction
assign bp_paddr[15] = bypass_15( va_mux[15], bp_sel_15d[0], /* combo of all Virtual addr.*/ ctpr[11], bp_sel_15d[1], /* Context Table Pointer Reg.*/ ibar[11], bp_sel_15d[2], /* IO Base Address Reg output.*/ io_addr[25], bp_sel_15d[3]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( bp_sel_15d[3]+ bp_sel_15d[2]+ bp_sel_15d[1]+ bp_sel_15d[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( bp_sel_15d[3]+ bp_sel_15d[2]+ bp_sel_15d[1]^ bp_sel_15d[0]===1'bx)) begin
$display("### %m.bypass_15: CMUX4D select error!\n");
$display(" bp_sel_15d[3], bp_sel_15d[2], bp_sel_15d[1], bp_sel_15d[0]=%0d%0d%0d%0d\n", bp_sel_15d[3], bp_sel_15d[2], bp_sel_15d[1], bp_sel_15d[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/* IO virtual address bit [25].*/
/* DPA_15 mux (2:1) selects between Bypass addr. and TLB addr. */
// Expanded macro begin.
// cmux2(dpa_15, 1, data_pa[15], tb_out[09], /* TLB data output (PTP or PTE)*/ hack_par[15], /* Bypass address*/ dpa_sel_l2)
function [ 1:1] dpa_15 ;
input [ 1:1] in0_fn ;
input [ 1:1] in1_fn ;
input select_fn ;
reg [ 1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
dpa_15 = out_fn ;
end
endfunction
assign data_pa[15] = dpa_15( tb_out[09], /* TLB data output (PTP or PTE)*/ hack_par[15], /* Bypass address*/ dpa_sel_l2) ;
// Expanded macro end.
/* DPA mux select (0 = tb_out).*/
/* */
/***** PA[14] definition. ************************************************/
/* BYPASS_14 mux (4:1) provides addresses that bypass the TLB. */
// Expanded macro begin.
// cmux4d(bypass_14, 1, bp_paddr[14], va_mux[14], bp_sel_14d[0], /* combo of all Virtual addr.*/ ctpr[10], bp_sel_14d[1], /* Context Table Pointer Reg.*/ ibar[10], bp_sel_14d[2], /* IO Base Address Reg output.*/ io_addr[24], bp_sel_14d[3])
function [ 1:1] bypass_14 ;
input [ 1:1] in0_fn ;
input s0_fn ;
input [ 1:1] in1_fn ;
input s1_fn ;
input [ 1:1] in2_fn ;
input s2_fn ;
input [ 1:1] in3_fn ;
input s3_fn ;
reg [ 1:1] out_fn ;
begin
case ({ bp_sel_14d[3], bp_sel_14d[2], bp_sel_14d[1], bp_sel_14d[0]}) /* synopsys parallel_case */
4'b0001: out_fn = in0_fn;
4'b0010: out_fn = in1_fn;
4'b0100: out_fn = in2_fn;
4'b1000: out_fn = in3_fn;
default: out_fn = 65'hx;
endcase
bypass_14 = out_fn ;
end
endfunction
assign bp_paddr[14] = bypass_14( va_mux[14], bp_sel_14d[0], /* combo of all Virtual addr.*/ ctpr[10], bp_sel_14d[1], /* Context Table Pointer Reg.*/ ibar[10], bp_sel_14d[2], /* IO Base Address Reg output.*/ io_addr[24], bp_sel_14d[3]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( bp_sel_14d[3]+ bp_sel_14d[2]+ bp_sel_14d[1]+ bp_sel_14d[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( bp_sel_14d[3]+ bp_sel_14d[2]+ bp_sel_14d[1]^ bp_sel_14d[0]===1'bx)) begin
$display("### %m.bypass_14: CMUX4D select error!\n");
$display(" bp_sel_14d[3], bp_sel_14d[2], bp_sel_14d[1], bp_sel_14d[0]=%0d%0d%0d%0d\n", bp_sel_14d[3], bp_sel_14d[2], bp_sel_14d[1], bp_sel_14d[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/* IO virtual address bit [24].*/
/* DPA_14 mux (2:1) selects between Bypass addr. and TLB addr. */
// Expanded macro begin.
// cmux2(dpa_14, 1, data_pa[14], tb_out[08], /* TLB data output (PTP or PTE)*/ hack_par[14], /* Bypass address*/ dpa_sel_l2)
function [ 1:1] dpa_14 ;
input [ 1:1] in0_fn ;
input [ 1:1] in1_fn ;
input select_fn ;
reg [ 1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
dpa_14 = out_fn ;
end
endfunction
assign data_pa[14] = dpa_14( tb_out[08], /* TLB data output (PTP or PTE)*/ hack_par[14], /* Bypass address*/ dpa_sel_l2) ;
// Expanded macro end.
/* DPA mux select (0 = tb_out).*/
/* */
/***** PA[13:12] definition. *********************************************/
/* BYPASS_12 mux (3:1) provides addresses that bypass the TLB. */
// Expanded macro begin.
// cmux3d(bypass_12, 2, bp_paddr[13:12], va_mux[13:12], /* combination of all Virtual addr.*/ bp_sel_21d[0], /* Bypass Mux select encoded above.*/ ctpr[09:08], /* Context Table Pointer Reg.*/ bp_sel_21d[1], /* Bypass Mux select encoded above.*/ io_addr[23:22], /* IO table walk virtual address */ bp_sel_21d[2])
function [ 2:1] bypass_12 ;
input [ 2:1] in0_fn ;
input s0_fn ;
input [ 2:1] in1_fn ;
input s1_fn ;
input [ 2:1] in2_fn ;
input s2_fn ;
reg [ 2:1] out_fn ;
begin
case ({ /* IO table walk virtual address */ bp_sel_21d[2], /* Context Table Pointer Reg.*/ bp_sel_21d[1], /* combination of all Virtual addr.*/ bp_sel_21d[0]}) /* synopsys parallel_case */
3'b001: out_fn = in0_fn;
3'b010: out_fn = in1_fn;
3'b100: out_fn = in2_fn;
default: out_fn = 65'hx;
endcase
bypass_12 = out_fn ;
end
endfunction
assign bp_paddr[13:12] = bypass_12( va_mux[13:12], /* combination of all Virtual addr.*/ bp_sel_21d[0], /* Bypass Mux select encoded above.*/ ctpr[09:08], /* Context Table Pointer Reg.*/ bp_sel_21d[1], /* Bypass Mux select encoded above.*/ io_addr[23:22], /* IO table walk virtual address */ bp_sel_21d[2]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( /* IO table walk virtual address */ bp_sel_21d[2]+ /* Context Table Pointer Reg.*/ bp_sel_21d[1]+ /* combination of all Virtual addr.*/ bp_sel_21d[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( /* IO table walk virtual address */ bp_sel_21d[2]+ /* Context Table Pointer Reg.*/ bp_sel_21d[1]^ /* combination of all Virtual addr.*/ bp_sel_21d[0]===1'bx)) begin
$display("### %m.bypass_12: CMUX3D select error!\n");
$display(" /* IO table walk virtual address */ bp_sel_21d[2], /* Context Table Pointer Reg.*/ bp_sel_21d[1], /* combination of all Virtual addr.*/ bp_sel_21d[0]=%0d%0d%0d\n", /* IO table walk virtual address */ bp_sel_21d[2], /* Context Table Pointer Reg.*/ bp_sel_21d[1], /* combination of all Virtual addr.*/ bp_sel_21d[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/* Bypass Mux selects (decoded above).*/
/* DPA_12 mux (2:1) selects between Bypass addr. and TLB addr. */
// Expanded macro begin.
// cmux2(dpa_12, 2, data_pa[13:12], tb_out[07:06], /* TLB data output (PTP or PTE)*/ hack_par[13:12], /* Bypass address*/ dpa_sel_l2)
function [ 2:1] dpa_12 ;
input [ 2:1] in0_fn ;
input [ 2:1] in1_fn ;
input select_fn ;
reg [ 2:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
dpa_12 = out_fn ;
end
endfunction
assign data_pa[13:12] = dpa_12( tb_out[07:06], /* TLB data output (PTP or PTE)*/ hack_par[13:12], /* Bypass address*/ dpa_sel_l2) ;
// Expanded macro end.
/* DPA mux select (0 = tb_out).*/
/* */
/***** PA[11:10] definition. *********************************************/
/* Bypass_10 mux (3:1) provides addresses that bypass the TLB. */
// Expanded macro begin.
// cmux3d(bypass_10, 2, bp_paddr[11:10], va_mux[11:10], bp_sel_10d[0], /* combo of all Virtual addr.*/ ctpr[07:06], bp_sel_10d[1], /* sel for CTPR for table walks*/ io_addr[21:20], bp_sel_10d[2])
function [ 2:1] bypass_10 ;
input [ 2:1] in0_fn ;
input s0_fn ;
input [ 2:1] in1_fn ;
input s1_fn ;
input [ 2:1] in2_fn ;
input s2_fn ;
reg [ 2:1] out_fn ;
begin
case ({ bp_sel_10d[2], bp_sel_10d[1], bp_sel_10d[0]}) /* synopsys parallel_case */
3'b001: out_fn = in0_fn;
3'b010: out_fn = in1_fn;
3'b100: out_fn = in2_fn;
default: out_fn = 65'hx;
endcase
bypass_10 = out_fn ;
end
endfunction
assign bp_paddr[11:10] = bypass_10( va_mux[11:10], bp_sel_10d[0], /* combo of all Virtual addr.*/ ctpr[07:06], bp_sel_10d[1], /* sel for CTPR for table walks*/ io_addr[21:20], bp_sel_10d[2]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( bp_sel_10d[2]+ bp_sel_10d[1]+ bp_sel_10d[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( bp_sel_10d[2]+ bp_sel_10d[1]^ bp_sel_10d[0]===1'bx)) begin
$display("### %m.bypass_10: CMUX3D select error!\n");
$display(" bp_sel_10d[2], bp_sel_10d[1], bp_sel_10d[0]=%0d%0d%0d\n", bp_sel_10d[2], bp_sel_10d[1], bp_sel_10d[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/* IO table walk virtual addr*/
/* DPA_10 mux (2:1) selects between Bypass addr. and TLB data_out. */
// Expanded macro begin.
// cmux2(dpa_10, 2, data_pa[11:10], tb_out[05:04], /* TLB data output (PTP)*/ hack_par[11:10], /* Bypass address */ dpa_sel_10d)
function [ 2:1] dpa_10 ;
input [ 2:1] in0_fn ;
input [ 2:1] in1_fn ;
input select_fn ;
reg [ 2:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
dpa_10 = out_fn ;
end
endfunction
assign data_pa[11:10] = dpa_10( tb_out[05:04], /* TLB data output (PTP)*/ hack_par[11:10], /* Bypass address */ dpa_sel_10d) ;
// Expanded macro end.
/* DPA mux select (0 = tb_out).*/
/* */
/***** PA[09:08] definition. *********************************************/
/* VA_ptp_8 mux (2:1) selects between the bypass VA and the VA *
* used for PTP (context table) look-ups during table walks. */
// Expanded macro begin.
// cmux2(va_ptp_8, 2, va_ptp_out[07:06], va_mux[09:08], /* combination of all Virtual addr.*/ va_mux[31:30], /* all VA's for Cntxt table PTP*/ va_ptp8_sel)
function [2:1] va_ptp_8 ;
input [2:1] in0_fn ;
input [2:1] in1_fn ;
input select_fn ;
reg [2:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
va_ptp_8 = out_fn ;
end
endfunction
assign va_ptp_out[07:06] = va_ptp_8( va_mux[09:08], /* combination of all Virtual addr.*/ va_mux[31:30], /* all VA's for Cntxt table PTP*/ va_ptp8_sel) ;
// Expanded macro end.
/* Sel PTP during Cntxt table walk*/
/* DPA_8 mux (4:1) selects between Bypass addr. and TLB data_out. */
// Expanded macro begin.
// cmux3d(bypass_8, 2, bp_paddr[09:08], va_ptp_out[07:06], bp_sel_10d[0], /* VA or PTP for tw*/ cxr[7:6], bp_sel_10d[1], /* select for Cxr for tw*/ io_addr[19:18], bp_sel_10d[2])
function [2:1] bypass_8 ;
input [2:1] in0_fn ;
input s0_fn ;
input [2:1] in1_fn ;
input s1_fn ;
input [2:1] in2_fn ;
input s2_fn ;
reg [2:1] out_fn ;
begin
case ({ bp_sel_10d[2], bp_sel_10d[1], bp_sel_10d[0]}) /* synopsys parallel_case */
3'b001: out_fn = in0_fn;
3'b010: out_fn = in1_fn;
3'b100: out_fn = in2_fn;
default: out_fn = 65'hx;
endcase
bypass_8 = out_fn ;
end
endfunction
assign bp_paddr[09:08] = bypass_8( va_ptp_out[07:06], bp_sel_10d[0], /* VA or PTP for tw*/ cxr[7:6], bp_sel_10d[1], /* select for Cxr for tw*/ io_addr[19:18], bp_sel_10d[2]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( bp_sel_10d[2]+ bp_sel_10d[1]+ bp_sel_10d[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( bp_sel_10d[2]+ bp_sel_10d[1]^ bp_sel_10d[0]===1'bx)) begin
$display("### %m.bypass_8: CMUX3D select error!\n");
$display(" bp_sel_10d[2], bp_sel_10d[1], bp_sel_10d[0]=%0d%0d%0d\n", bp_sel_10d[2], bp_sel_10d[1], bp_sel_10d[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/* IO table walk virtual addr*/
// Expanded macro begin.
// cmux2(dpa_8, 2, data_pa[09:08], tb_out[03:02], /* TLB data output on (PTP or PTE) rd*/ hack_par[09:08], /* Bypass address */ dpa_sel_8d)
function [2:1] dpa_8 ;
input [2:1] in0_fn ;
input [2:1] in1_fn ;
input select_fn ;
reg [2:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
dpa_8 = out_fn ;
end
endfunction
assign data_pa[09:08] = dpa_8( tb_out[03:02], /* TLB data output on (PTP or PTE) rd*/ hack_par[09:08], /* Bypass address */ dpa_sel_8d) ;
// Expanded macro end.
/* DPA mux select (0 = tb_out).*/
/* */
/***** PA[07:04] definition. *********************************************/
/* VA_ptp_4 mux (4:1) selects between the bypass VA and the VA *
* used for PTP (cntxt, level 1, level2) look-ups during table walks.*/
// Expanded macro begin.
// cmux4d(va_ptp_4, 4, va_ptp_out[05:02], va_mux[07:04], va_ptp4_sel[0], /* combo of all Virtual addr.*/ va_mux[29:26], va_ptp4_sel[1], /* all VA's for Cntxt table PTP*/ va_mux[23:20], va_ptp4_sel[2], /* all VA's for level 1 PTP*/ va_mux[17:14], va_ptp4_sel[3])
function [ 4:1] va_ptp_4 ;
input [ 4:1] in0_fn ;
input s0_fn ;
input [ 4:1] in1_fn ;
input s1_fn ;
input [ 4:1] in2_fn ;
input s2_fn ;
input [ 4:1] in3_fn ;
input s3_fn ;
reg [ 4:1] out_fn ;
begin
case ({ va_ptp4_sel[3], va_ptp4_sel[2], va_ptp4_sel[1], va_ptp4_sel[0]}) /* synopsys parallel_case */
4'b0001: out_fn = in0_fn;
4'b0010: out_fn = in1_fn;
4'b0100: out_fn = in2_fn;
4'b1000: out_fn = in3_fn;
default: out_fn = 65'hx;
endcase
va_ptp_4 = out_fn ;
end
endfunction
assign va_ptp_out[05:02] = va_ptp_4( va_mux[07:04], va_ptp4_sel[0], /* combo of all Virtual addr.*/ va_mux[29:26], va_ptp4_sel[1], /* all VA's for Cntxt table PTP*/ va_mux[23:20], va_ptp4_sel[2], /* all VA's for level 1 PTP*/ va_mux[17:14], va_ptp4_sel[3]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( va_ptp4_sel[3]+ va_ptp4_sel[2]+ va_ptp4_sel[1]+ va_ptp4_sel[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( va_ptp4_sel[3]+ va_ptp4_sel[2]+ va_ptp4_sel[1]^ va_ptp4_sel[0]===1'bx)) begin
$display("### %m.va_ptp_4: CMUX4D select error!\n");
$display(" va_ptp4_sel[3], va_ptp4_sel[2], va_ptp4_sel[1], va_ptp4_sel[0]=%0d%0d%0d%0d\n", va_ptp4_sel[3], va_ptp4_sel[2], va_ptp4_sel[1], va_ptp4_sel[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/* all VA's for level 2 PTP*/
/* DPA_4 mux (2:1) selects between CXR, Bypass addr. */
// Expanded macro begin.
// cmux2(dpa_4, 4, data_pa[07:04], hack_par[07:04], /* VA or PTP for Context table walk*/ cxr[05:02], /* Context register output*/ ctpr_sel)
function [ 4:1] dpa_4 ;
input [ 4:1] in0_fn ;
input [ 4:1] in1_fn ;
input select_fn ;
reg [ 4:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
dpa_4 = out_fn ;
end
endfunction
assign data_pa[07:04] = dpa_4( hack_par[07:04], /* VA or PTP for Context table walk*/ cxr[05:02], /* Context register output*/ ctpr_sel) ;
// Expanded macro end.
/* select cxr when selecting ctpr, too */
/* */
/***** PA[03:02] definition. *********************************************/
/* VA_ptp_2 mux (4:1) selects between the bypass VA and the VA *
* used for PTP (cntxt, level 1, level2) look-ups during table walks.*/
// Expanded macro begin.
// cmux4d(va_ptp_2, 2, va_ptp_out[01:00], va_mux[03:02], va_ptp4_sel[0], /* combo of all Virtual addr.*/ va_mux[25:24], va_ptp4_sel[1], /* all VA's for Cntxt table PTP*/ va_mux[19:18], va_ptp4_sel[2], /* all VA's for level 1 PTP*/ va_mux[13:12], va_ptp4_sel[3])
function [ 2:1] va_ptp_2 ;
input [ 2:1] in0_fn ;
input s0_fn ;
input [ 2:1] in1_fn ;
input s1_fn ;
input [ 2:1] in2_fn ;
input s2_fn ;
input [ 2:1] in3_fn ;
input s3_fn ;
reg [ 2:1] out_fn ;
begin
case ({ va_ptp4_sel[3], va_ptp4_sel[2], va_ptp4_sel[1], va_ptp4_sel[0]}) /* synopsys parallel_case */
4'b0001: out_fn = in0_fn;
4'b0010: out_fn = in1_fn;
4'b0100: out_fn = in2_fn;
4'b1000: out_fn = in3_fn;
default: out_fn = 65'hx;
endcase
va_ptp_2 = out_fn ;
end
endfunction
assign va_ptp_out[01:00] = va_ptp_2( va_mux[03:02], va_ptp4_sel[0], /* combo of all Virtual addr.*/ va_mux[25:24], va_ptp4_sel[1], /* all VA's for Cntxt table PTP*/ va_mux[19:18], va_ptp4_sel[2], /* all VA's for level 1 PTP*/ va_mux[13:12], va_ptp4_sel[3]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( va_ptp4_sel[3]+ va_ptp4_sel[2]+ va_ptp4_sel[1]+ va_ptp4_sel[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( va_ptp4_sel[3]+ va_ptp4_sel[2]+ va_ptp4_sel[1]^ va_ptp4_sel[0]===1'bx)) begin
$display("### %m.va_ptp_2: CMUX4D select error!\n");
$display(" va_ptp4_sel[3], va_ptp4_sel[2], va_ptp4_sel[1], va_ptp4_sel[0]=%0d%0d%0d%0d\n", va_ptp4_sel[3], va_ptp4_sel[2], va_ptp4_sel[1], va_ptp4_sel[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/* all VA's for level 2 PTP*/
/* DPA_2 mux (2:1) selects between CXR, Bypass addr */
// Expanded macro begin.
// cmux2(dpa_2, 2, data_pa[03:02], hack_par[03:02], /* VA or PTP for Context table walk*/ cxr[01:00], /* Context register output*/ ctpr_sel)
function [ 2:1] dpa_2 ;
input [ 2:1] in0_fn ;
input [ 2:1] in1_fn ;
input select_fn ;
reg [ 2:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
dpa_2 = out_fn ;
end
endfunction
assign data_pa[03:02] = dpa_2( hack_par[03:02], /* VA or PTP for Context table walk*/ cxr[01:00], /* Context register output*/ ctpr_sel) ;
// Expanded macro end.
/* select cxr when selecting ctpr, too */
/* */
/***** PA[01:00] definition. *********************************************/
/* DPA_0 mux (2:1) selects between Bypass addr. and padding "00". */
// Expanded macro begin.
// cmux2(dpa_0, 2, data_pa[01:00], hack_par[01:00], /* VA address bypass*/ 2'b0, /* "00" for instr pointer access, TLB reads*/ dpa_sel_0)
function [ 2:1] dpa_0 ;
input [ 2:1] in0_fn ;
input [ 2:1] in1_fn ;
input select_fn ;
reg [ 2:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
dpa_0 = out_fn ;
end
endfunction
assign data_pa[01:00] = dpa_0( hack_par[01:00], /* VA address bypass*/ 2'b0, /* "00" for instr pointer access, TLB reads*/ dpa_sel_0) ;
// Expanded macro end.
/* address data output select (dpa_0)*/
/***************************************************************************/
/*** Logic associated with the input to PAR (mm_dpa) ***/
/***************************************************************************/
/*** Memory address space map for ***/
/*** ***/
/*** PA[30:28] Address Space ***/
/*** --------- ------------- ***/
/*** 000 Main Memory space ***/
/*** 001 Control Space (Sun-4M system registers) ***/
/*** 010 Frame Buffer space (see AFX spec) ***/
/*** 011 I/O Space (Sbus slave select 0) ***/
/*** 100 I/O Space (Sbus slave select 1) ***/
/*** 101 I/O Space (Sbus slave select 2) ***/
/*** 110 I/O Space (Sbus slave select 3) ***/
/*** 111 I/O Space (Sbus slave select 4) ***/
/*** ***/
assign mem_space = ~(data_pa[30] | data_pa[29] | data_pa[28]);
assign cntl_space = ~data_pa[30] & ~data_pa[29] & data_pa[28];
// assign fb_space = ~data_pa[30] & data_pa[29] & ~data_pa[28];
// ARAY
assign fb_space = ~data_pa[30] & data_pa[29] &
(falcon_exists ? 1'b1 : ~data_pa[28]) ;
assign pci_space = fb_space & data_pa[28];
assign io_space = ~mem_space & ~cntl_space & ~fb_space;
// 4 special par register to store the data from par
/***************************************************************************/
/*** data PHY register ***/
MflipflopR_31 dpar_reg_31( dpar,data_pa,ss_clock,hld_dpar,ss_reset) ;
/*** instr. PHY register ***/
MflipflopR_31 ipar_reg_31( ipar,data_pa,ss_clock,hld_ipar,ss_reset) ;
// output mux for one of above par
assign bp_paddr1 = { bp_paddr, va_ptp_out[5:0], va_mux[1:0] };
/***************************************************************************/
// page hit detection logic (main memory) 8k pages
// Clear page hit regs on refresh.
// the valids must be turned off after an afx pci useage of memory
// since the ras's are left turned off. Failed banks.s
wire page_0_vld_in
= mm_page_hit_en[0] & ~mc_refresh & ~mem_idle &
~afx_rst_page_vld & ~(~mc_mbsy & precharge_early_0 );
wire page_1_vld_in = mm_page_hit_en[1] & ~mc_refresh & ~mem_idle &
~afx_rst_page_vld & ~(~mc_mbsy & precharge_early_1 );
wire update_vld_0 = ~(mc_refresh | mem_idle| (~mc_mbsy & precharge_early_0 ) |
afx_rst_page_vld |
(mm_issue_req & (~par[25] |
(~mm_page_hit_en[1] & mm_page_hit_en[0]))));
wire update_vld_1 = ~(mc_refresh | mem_idle | (~mc_mbsy & precharge_early_1 ) |
afx_rst_page_vld |
(mm_issue_req & (par[25] |
(~mm_page_hit_en[1] & mm_page_hit_en[0]))));
wire [30:12] page_0_reg, page_1_reg;
MflipflopR_19 page_0_reg_19(page_0_reg,par[30:12],ss_clock,update_vld_0,ss_reset) ;
MflipflopR_19 page_1_reg_19(page_1_reg,par[30:12],ss_clock,update_vld_1,ss_reset) ;
wire page_0_vld,page_1_vld;
MflipflopR_1 page_0_vld_reg_1(page_0_vld,page_0_vld_in,ss_clock, update_vld_0,ss_reset) ;
MflipflopR_1 page_1_vld_reg_1(page_1_vld,page_1_vld_in,ss_clock, update_vld_1,ss_reset) ;
//*** start page mode compare logice *****
assign page_miss0 = ~(par[30:12] == page_0_reg) & ~par[25] & page_0_vld;
assign page_miss1 = ~(par[30:12] == page_1_reg) & par[25] & page_1_vld;
wire page_hit0 = ( par[30:12] == page_0_reg ) & page_0_vld;
wire page_hit1 = ( par[30:12] == page_1_reg ) & page_1_vld;
assign page_hit = ( page_hit0 | page_hit1 );
/***************************************************************************/
/*** page hit detection logic (frame buffer - see AFX 2.0 spec) ***/
/*** ***/
/*** The Frame buffer (AFX) page hit is encoded in the signal ***/
/*** mm_fb_page which indicates a match of the cycle 0 address ***/
/*** ***/
/*** The Frame buffer physical address is broken up as follows: ***/
/*** ***/
/*** update row - PA[27:14] ***/
/*** transfer r/w - R/W, BM[3:0], PA[13:3] ***/
/*** ***/
wire fb_page_hld = ~(mm_issue_req & mm_fb_req) ;
wire [15:0] fb_page_in = {~fb_page_hld,par[28:14]} ;
wire [15:0] fb_page_reg ;
MflipflopR_16 fb_page_reg_16(fb_page_reg,fb_page_in,ss_clock,fb_page_hld,ss_reset) ;
assign mm_fb_page = (par[28:14] == fb_page_reg[14:00]) &
(fb_page_reg[15] == 1'b1) & mm_fbpage_en ;
/***************************************************************************/
/* PAR - physical address register (31 bits) pa[30:00] */
MflipflopR_31 par_31( par, data_pa, /* load PAR from the DATA Physical Addr*/ ss_clock,hold_par, /* load enable for PAR*/ ss_reset) ;
// CAS address output
// cas have send to memif one cycle early
/*****************************************************************************/
/* CAS ADDRESS MUX and REGISTER */
wire [11:3] mm_caddr_in;
/*** this mux selects par input any cycle par is loaded. */
// Expanded macro begin.
// cmux2(caddr_mux, 9, mm_caddr_in[11:03], data_pa[11:03], pa_out[11:03], hold_par)
function [9:1] caddr_mux ;
input [9:1] in0_fn ;
input [9:1] in1_fn ;
input select_fn ;
reg [9:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
caddr_mux = out_fn ;
end
endfunction
assign mm_caddr_in[11:03] = caddr_mux( data_pa[11:03], pa_out[11:03], hold_par) ;
// Expanded macro end.
wire [11:3] mm_caddr;
MflipflopR_9 mc_caddr_reg_9(mm_caddr,mm_caddr_in,ss_clock,mc_caddr_hld,ss_reset) ;
/*****************************************************************************/
/***************************************************************************/
/***** Read muxes for TLB, cache stat, and Physically address dp regs. *****/
wire [31:0] cache_stat = { va_mux[31:13], 1'b0, cxr[7:0], 4'b0 } ;
/***** dp_mux_1 - level 1 datapath muxing ***********************************/
/*** dp_mux1_sel0 - ctpr (asi_dcd4 & ~dva[8]) **/
/*** dp_mux1_sel1 - sfar (asi_dcd4 & dva[8]) **/
/*** dp_mux1_sel2 - mfar (pa_reg_dcd) **/
/*** dp_mux1_sel3 - ibar (default) **/
/*** dp_mux1_sel4 - tlb_data_reg ( asi read for tlb data shadow reg ) ***/
// update mfar_out to 32 bit since mfar is 31 bits need msb tight to zero
wire [31:0] mfar_out = { 1'b0, mfar };
// wire [31:0] tlb_data_asi_out = { 2'b0,tlb_data_reg[27:0],~tlb_cam_reg[1],tlb_cam_reg[1] };
wire [31:0] tlb_data_asi_out = { tlb_data_reg[27:25],2'b0,tlb_data_reg[24:0],~tlb_cam_reg[1],tlb_cam_reg[1] };
wire [31:0] dp_mux1_out;
// Expanded macro begin.
// cmux5d(dp_mux1, 32, dp_mux1_out, ctpr, dp_mux1_sel[0], sfar, dp_mux1_sel[1], mfar_out, dp_mux1_sel[2], ibar, dp_mux1_sel[3], tlb_data_asi_out, dp_mux1_sel[4])
function [32:1] dp_mux1 ;
input [32:1] in0_fn ;
input s0_fn ;
input [32:1] in1_fn ;
input s1_fn ;
input [32:1] in2_fn ;
input s2_fn ;
input [32:1] in3_fn ;
input s3_fn ;
input [32:1] in4_fn ;
input s4_fn ;
reg [32:1] out_fn ;
begin
case ({ dp_mux1_sel[4], dp_mux1_sel[3], dp_mux1_sel[2], dp_mux1_sel[1], dp_mux1_sel[0]}) /* synopsys parallel_case */
5'b00001: out_fn = in0_fn ;
5'b00010: out_fn = in1_fn ;
5'b00100: out_fn = in2_fn ;
5'b01000: out_fn = in3_fn ;
5'b10000: out_fn = in4_fn ;
default: out_fn = 65'hx;
endcase
dp_mux1 = out_fn ;
end
endfunction
assign dp_mux1_out = dp_mux1( ctpr, dp_mux1_sel[0], sfar, dp_mux1_sel[1], mfar_out, dp_mux1_sel[2], ibar, dp_mux1_sel[3], tlb_data_asi_out, dp_mux1_sel[4]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( dp_mux1_sel[4]+ dp_mux1_sel[3]+ dp_mux1_sel[2]+ dp_mux1_sel[1]+ dp_mux1_sel[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( dp_mux1_sel[4]+ dp_mux1_sel[3]+ dp_mux1_sel[2]+ dp_mux1_sel[1]^ dp_mux1_sel[0]===1'bx)) begin
$display("### %m.dp_mux1: CMUX5D select error!\n");
$display(" dp_mux1_sel[4], dp_mux1_sel[3], dp_mux1_sel[2], dp_mux1_sel[1], dp_mux1_sel[0]=%0d%0d%0d%0d%0d\n", dp_mux1_sel[4], dp_mux1_sel[3], dp_mux1_sel[2], dp_mux1_sel[1], dp_mux1_sel[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/***** Read Physically Addressed register mux (4:1) *****/
/***** since want one cycle late for , we use shdow register cam tag ******/
wire tlb_tag_sel = asi_dcd6 & ~r_d_vaddr[9] ;
wire [31:0] tlb_cam_reg_l = { 22'b0, tlb_cam_reg[9:0] };
wire [31:0] tlb_rd_out ;
// Expanded macro begin.
// cmux2(tlb_rd_mux, 32, tlb_rd_out, tlb_cam_reg[41:10], tlb_cam_reg_l, tlb_tag_sel)
function [32:1] tlb_rd_mux ;
input [32:1] in0_fn ;
input [32:1] in1_fn ;
input select_fn ;
reg [32:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
tlb_rd_mux = out_fn ;
end
endfunction
assign tlb_rd_out = tlb_rd_mux( tlb_cam_reg[41:10], tlb_cam_reg_l, tlb_tag_sel) ;
// Expanded macro end.
wire [31:0] pa_mux_rd;
// update afar_out to 32 bit since afar is 31 bits need msb tight to zero
wire [31:0] afar_out = { 1'b0, afar };
// Expanded macro begin.
// cmux2(lvl_probe_mux, 32, tlb_rd_data_byp, tlb_rd_data, misc_in, lvl_probe_hld)
function [32:1] lvl_probe_mux ;
input [32:1] in0_fn ;
input [32:1] in1_fn ;
input select_fn ;
reg [32:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
lvl_probe_mux = out_fn ;
end
endfunction
assign tlb_rd_data_byp = lvl_probe_mux( tlb_rd_data, misc_in, lvl_probe_hld) ;
// Expanded macro end.
| This page: |
Created: | Thu Aug 19 11:59:31 1999 |
| From: |
../../../sparc_v8/ssparc/mmu/dp_mmu/rtl/dp_mmu.v
|