/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
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/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
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/* registered trademarks of Sun Microsystems, Inc. in the United States and */
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/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)dp_mmu.v
***
****************************************************************************
****************************************************************************/
// @(#)dp_mmu.v 1.96 8/26/94
//
// MMU datapath module
// Description :
// This module describes the virtual address muxing model,
// of the input address to PA mux. This rtl model describe the
// muxing requirment in MMU datapath to form tlb_tag, tlb_data,
// table walk ( IU/IO ) address, and also support relatived ASI
// access to TLB/MFAR/SFAR/IBAR/CTPR..etc.
//
// Updated :
// 3/18/92 update to adjust new tlb
// 4/8/92 update for tlb megacell update.
// 6/11/92 update for asi cma/sram access mux ,
// move them above va_mux
// Dependencies :
// Instantiated by mmu.v module
//
//*************************************************************************
![[Up: mmu MMU_dp]](v2html-up.gif)
module dp_mmu
(va_tag_out, cxr, pcntr_a_co, pcntr_b_co,
page_hit, mm_fb_page, page_miss0, page_miss1,
r_d_vaddr_out, bm_sel, falcon_exists, io_s_bit,
pa_out, mm_sb_pa, mm_caddr,
pa_mux_rd, precharge_early_0, precharge_early_1, mc_mbsy,
io_space, cntl_space, fb_space, mem_space, pci_space,
wb_3_size, wb_3_asi, brk_pt_hit, odd_wd,
dp_mmu_scan_out,
mc_refresh,io_addr, i_vaddr, d_vaddr, tlb_data_in,
misc_bus_in,
mmu_ptp_in, iva_s_in, dva_s_in, msm_mbit_in,
sfar_write, sfar_read, asi_dcd6,
tlb_acc_cmp, tlb_mbit_cmp, mbit_sel,
va_mux0_sel, va_mux1_sel, va_mux_sel,
mm_page_hit_en, mm_issue_req, mm_fb_req,
hld_cxr, hld_sfar, tlb_ram_lvl, tlb_cam_lvl,
sel_mdat_mux, mm_fbpage_en,
tb_out, tw_io_bit,
hld_ctpr, hld_ibar, hold_par, hld_afar, hld_mfar,
afar_write, mfar_write,
bp_sel_30, bp_sel_28, bp_sel_21, bp_sel_20,
bp_sel_19, bp_sel_18, bp_sel_17, bp_sel_16,
bp_sel_15, bp_sel_14, bp_mux_sel0, cpu_walk, io_walk,
dpa_sel_b, dpa_sel_8d,
ctpr_sel, dpa_sel_0,
va_ptp8_sel, va_ptp4_sel,
dp_mux1_sel, pamux_rd_sel,
tlb_rd_tag, boot_out_30, io_tlb_nxt,
tw_rewrite_cam, tw_tlb_vbit,
tlb_s_bit, tlb_wrt_tag,
par_sel, hld_dpar, hld_ipar,
cam_reg_hld, ram_reg_hld,
iu_asi_e, iu_size_e, lvl_probe_hld,
mc_caddr_hld,
pipe_hold4mmu_dp,
wb0_hold_lo, wb1_hold_lo, wb2_hold_lo, wb3_hold_lo,
wb_1_sel, wb_2_sel, wb_3_sel,
ic_miss, mem_idle, afx_rst_page_vld,
ld_pcntr_a, ld_pcntr_b, trig_a, trig_b, sel_brkpt_mux, iva_wp_sel,
vaf_en_hld, va_bp_hld, va_src_sel,
ss_clock, ss_reset, ss_scan_mode, dp_mmu_scan_in);
output [41:0] va_tag_out; /* output of va_mux for TLB tag. */
output [7:0] cxr; /* Context register output. */
output pcntr_a_co; /* perf cntr A carry out */
output pcntr_b_co; /* perf cntr B carry out */
output page_hit; /* indicate page hit case for memif */
output mm_fb_page; /* indicate fb page hit case for memif */
output page_miss0; /* page miss (but valid) for page 0 */
output page_miss1; /* page miss (but valid) for page 1 */
output [12:2] r_d_vaddr_out; /* registered data virtual addr. */
output [27:0] tlb_data_in;
/* Output busses */
output [30:0] pa_out; /* Physical address output (NO buffer) */
output [30:0] mm_sb_pa; /* Physical address output to sbc */
output [11:3] mm_caddr; /* cas address output */
output [31:0] pa_mux_rd; /* read data from pa_mux datapath */
output io_space; /* mm_dpa[30:28] is non-zero. */
output cntl_space; /* mm_dpa[30:28] is "001". */
output fb_space; /* mm_dpa[30:28] is "010". */
output mem_space; /* mm_dpa[30:28] is "000". */
// ARAY
output pci_space;
output [1:0] wb_3_size; /* write buffer 3 size field */
output [1:0] wb_3_asi; /* write buffer 3 asi field */
output brk_pt_hit; /* Breakpoint logic addr match detected */
output odd_wd; /* Last memory op for an odd word */
output dp_mmu_scan_out;
/* Inputs */
input [1:0] bm_sel; // two bits, if 2,3 boot from PCI
input falcon_exists;
input io_s_bit;
input tw_io_bit;
input precharge_early_0;
input precharge_early_1;
input mc_mbsy;
input mc_refresh; /* dram is in refresh cycle */
input mm_fbpage_en; /* page hit en for afx */
input lvl_probe_hld; /* hold data from level probe miss memop */
input tw_rewrite_cam; /* TW re-writes CAM for L1,L2 PTE */
input [31:0] io_addr; /* IO address input. */
input [31:2] i_vaddr; /* instruction virtual address input. */
input [31:0] d_vaddr; /* data virtual address input. */
input [31:0] misc_bus_in; /* memory data input. */
input mmu_ptp_in; /* Data/control from MMU State Machine. */
input iva_s_in; /* Mem control supervisor bit input. */
input dva_s_in; /* Mem control supervisor bit input. */
input msm_mbit_in; /* Mem control modified bit input. */
input sfar_write; /* SFAR input mux select */
input sfar_read; /* SFAR input reset term */
input asi_dcd6; /* input for CXR mux select decode */
input [5:0] tlb_acc_cmp; /* TLB ACC bits for compares */
input tlb_mbit_cmp; /* TLB Mbit for compares */
input [2:0] mbit_sel; /* mux select fo mbit muxes. */
input [3:0] va_mux0_sel; /* mux select fo VA muxes. */
input [4:0] va_mux1_sel; /* mux select fo VA muxes. */
input [3:0] va_mux_sel; /* mux select fo VA muxes. */
input [1:0] mm_page_hit_en; /* enables for page hit registers */
input mm_issue_req; /* issue_req to memif */
input mm_fb_req; /* issue_req to FB memif */
input hld_cxr; /* Hold enable for CXR */
input hld_sfar; /* Hold enable for SFAR */
input [2:0] tlb_ram_lvl; /* TLB tag level input bits from tw sm. */
input [2:0] tlb_cam_lvl; /* TLB tag level input bits from tw sm. */
input sel_mdat_mux; /* regd mdat mux sel. w/ asi_dcd */
/* Input busses */
input [27:0] tb_out; /* tlb data output */
/* Input control from ASI decode */
input hld_ctpr; /* load enable for CTPR */
input hld_ibar; /* load enable for IBAR */
input hold_par; /* load enable for PAR */
input hld_afar; /* load enable for AFAR */
input hld_mfar; /* load enable for MFAR */
input afar_write; /* input mux select for AFAR. */
input mfar_write; /* input mux select for MFAR. */
/*** Mux select inputs */
input [1:0] bp_sel_30; /* Bypass mux selects for bits [30:29]. */
input [1:0] bp_sel_28; /* Bypass mux selects for bit [28]. */
input bp_sel_21; /* Bypass mux selects for bits [27:21]. */
input [1:0] bp_sel_20; /* Bypass mux selects for bit [20]. */
input [1:0] bp_sel_19; /* Bypass mux selects for bit [19]. */
input [1:0] bp_sel_18; /* Bypass mux selects for bit [18]. */
input [1:0] bp_sel_17; /* Bypass mux selects for bit [17]. */
input [1:0] bp_sel_16; /* Bypass mux selects for bit [16]. */
input [1:0] bp_sel_15; /* Bypass mux selects for bit [15]. */
input [1:0] bp_sel_14; /* Bypass mux selects for bit [14]. */
input bp_mux_sel0; /* Bypass mux select for D0 input */
input cpu_walk; /* Bypass mux select for cpu_walk */
input io_walk; /* Bypass mux select for io_walk */
input dpa_sel_b; /* DPA mux select for ROOT/level-1 PTE*/
input dpa_sel_8d; /* DPA mux select for bits [09:08] */
input ctpr_sel; /* DPA mux selects for bits [07:04].*/
input dpa_sel_0; /* DPA mux selects for bits [01:00].*/
input va_ptp8_sel;
input [3:0] va_ptp4_sel;
input [4:0] dp_mux1_sel; /* mux select for dp_mux1 read mux*/
input [4:0] pamux_rd_sel; /* mux select for PA regs read mux*/
input [41:0] tlb_rd_tag; /* TLB tag for ASI read operation*/
input boot_out_30; /* PA[30] for IO bypass path */
input io_tlb_nxt;
input tw_tlb_vbit; /* TLB write signal for v_in */
input tlb_s_bit; /* TLB write signal for s_in */
input tlb_wrt_tag; /* TLB write signal for s_in */
// added for swift
input [1:0] par_sel; /* select different par input */
// hold signal for the backup par register
input hld_ipar; /* hold signal for ipar reg */
input hld_dpar; /* hold signal for dpar reg */
input cam_reg_hld; /* hold signal for cam shadow reg */
input ram_reg_hld; /* hold signal for ram shadow reg */
input [1:0] iu_asi_e; /* asi fields from iu in e stage */
input [1:0] iu_size_e; /* iu access size */
input mc_caddr_hld;
input pipe_hold4mmu_dp;
input wb0_hold_lo;
input wb1_hold_lo;
input wb2_hold_lo;
input wb3_hold_lo;
input wb_1_sel;
input wb_2_sel;
input wb_3_sel;
input ic_miss; // i$ miss signal
input mem_idle; // mem idle just before standby mode
input afx_rst_page_vld; // reset the page valids after all
// pci afx transactions
input ld_pcntr_a;
input ld_pcntr_b;
input trig_a;
input trig_b;
input iva_wp_sel;
input sel_brkpt_mux;
input vaf_en_hld;
input va_bp_hld;
input [1:0] va_src_sel; /* VA breakpoint mux source select **/
input ss_clock;
input ss_reset;
input ss_scan_mode;
input dp_mmu_scan_in;
/**+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++**/
/***************************************************************************/
/***** DP_VA_MUX.V logic in first part **/
/***************************************************************************/
/**+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++**/
wire tlb_ptp_out;
wire tlb_sbit_out;
wire tw_mbit;
wire tlb_rbit_out;
wire tlb_vbit_out;
wire tlb_io_bit_out;
/***** wire definition for vx_mux (cam)*******/
wire asi_s_bit;
wire asi_v_in;
wire [5:0] asi_prot_in;
wire asi_mod_in;
wire asi_io_in;
wire asi_ptp_in;
wire [2:0] asi_lvl_in;
wire [7:0] asi_cntx_in;
wire [31:12] asi_va_in;
/****** start for data mux portion(sram) *******/
wire asi_data_r_in;
wire [19:0] misc1_in;
wire [2:0] misc2_in;
wire [2:0] asi_data_lvl_in;
/****** end of va mux asi ********/
wire [30:0] bp_paddr1;
wire [2:0] tlb_lvl_sram_out;
wire [5:0] tlb_pro_bits;
wire [5:0] prot_mux0_out;
wire [5:0] acc_prot;
wire [7:0] tlb_cntxt_out;
wire [19:0] tlb_pamux_out;
wire [19:0] va_tag_mux_out;
wire [31:0] va_mux;
wire [31:0] brkpt_mux;
wire [31:0] tlb_rd_data_byp;
wire [31:0] lvl_prb_data;
wire [2:0] tlb_lvl_out; /* in swift we, have lv1 */
wire [30:0] hack_par; /* output wire of 5 special mux */
wire [41:0] va_tag_out; /* size of va_tag_out */
wire tlb_cam_mbit; /* tlb cam mbit input wire */
wire mod_mux0_out; /* tlb cam mbit input wire */
// changed bit range from [39:0] to [35:0] to match other uses
wire [35:0] mux_2_out, mux_1_out, mux_3_out;
/* wire of mux out of store buffer */
/*************************************************************************/
wire [31:0] r_misc_in;
MflipflopR_32 misc_in_reg_32(r_misc_in,misc_bus_in,ss_clock,lvl_probe_hld,ss_reset) ;
wire [31:0] misc_in;
// Expanded macro begin.
// cmux2(misc_mux, 32, misc_in, misc_bus_in, r_misc_in, (tw_rewrite_cam | lvl_probe_hld))
function [32:1] misc_mux ;
input [32:1] in0_fn ;
input [32:1] in1_fn ;
input select_fn ;
reg [32:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
misc_mux = out_fn ;
end
endfunction
assign misc_in = misc_mux(misc_bus_in, r_misc_in, (tw_rewrite_cam | lvl_probe_hld)) ;
// Expanded macro end.
/*************************************************************************/
/* PA muxing defintions, defined by each bit. */
wire [30:0] data_pa; /* DATA physical address(for D$ and MCB)*/
wire [30:8] bp_paddr; /* bypass physical addr [30:12]*/
wire [7:0] va_ptp_out; /* output of VA Shift mux for tablewalks*/
wire [30:00] pa_out; /* Physical address is output from PAR*/
wire [30:0] mm_sb_pa = pa_out;
wire [30:0] par; /* def. moved from PAR reg. */
wire [30:0] ipar;
wire [30:0] dpar;
/** TLB CAM output register *********************************************/
/** Used for tablewalks and ASI write (R/M/W). **/
/** Uses software arrangement of fields. **/
/** **/
/*************************************************************************/
/** TLB TAG software representation **/
/** PTE **/
/** +---------+-------+-------+-----------+---+-----+-----+-+-+-+-+ **/
/** | INDX1 | INDX2 | INDX3 | Context | V | LVL | PTCT|S|I|P|M| **/
/** +---------+-------+-------+-----------+---+-----+-----+-+-+-+-+ **/
/** 41 34 33 28 27 22 21 14 13 12 10 9 4 3 2 1 0 **/
/** **/
/*************************************************************************/
wire [41:0] tlb_cam_reg ;
MflipflopR_42 tlb_cam_reg_42(tlb_cam_reg,tlb_rd_tag,ss_clock,cam_reg_hld,ss_reset) ;
/****************** Start the tlb_data_in register **********************/
/***** this is a registers to latch data for asi data write later on *****/
wire [27:0] tlb_data_reg;
MflipflopR_28 tlb_data_28(tlb_data_reg,tb_out,ss_clock,ram_reg_hld,ss_reset) ;
// Start store buffer address data path , asi also as a input.
// dva = 32 plus 2 bits asi --> iu_asi_e[1:0] signals
// remember 4 hold pin 3 mux pin from cache data store buffer
// sb_mux_sel 1 seleted sb_addr_input , 0 from upper register Shift
wire [35:0] wr_buf_0_out,wr_buf_1_out,wr_buf_2_out,wr_buf_3_out;
wire [35:0] sb_addr_in = { iu_size_e, iu_asi_e[1:0], d_vaddr };
// Expanded macro begin.
// cmux2(mux_1_out, 36, mux_1_out, sb_addr_in, wr_buf_0_out, wb_1_sel)
function [36:1] fn_mux_1_out ;
input [36:1] in0_fn ;
input [36:1] in1_fn ;
input select_fn ;
reg [36:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
fn_mux_1_out = out_fn ;
end
endfunction
assign mux_1_out = fn_mux_1_out(sb_addr_in, wr_buf_0_out, wb_1_sel) ;
// Expanded macro end.
// Expanded macro begin.
// cmux2(mux_2_out, 36, mux_2_out, sb_addr_in, wr_buf_1_out, wb_2_sel)
function [36:1] fn_mux_2_out ;
input [36:1] in0_fn ;
input [36:1] in1_fn ;
input select_fn ;
reg [36:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
fn_mux_2_out = out_fn ;
end
endfunction
assign mux_2_out = fn_mux_2_out(sb_addr_in, wr_buf_1_out, wb_2_sel) ;
// Expanded macro end.
// Expanded macro begin.
// cmux2(mux_3_out, 36, mux_3_out, sb_addr_in, wr_buf_2_out, wb_3_sel)
function [36:1] fn_mux_3_out ;
input [36:1] in0_fn ;
input [36:1] in1_fn ;
input select_fn ;
reg [36:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
fn_mux_3_out = out_fn ;
end
endfunction
assign mux_3_out = fn_mux_3_out(sb_addr_in, wr_buf_2_out, wb_3_sel) ;
// Expanded macro end.
MflipflopR_36 wr_buf_reg_0_36(wr_buf_0_out,sb_addr_in,ss_clock,~wb0_hold_lo,ss_reset) ;
MflipflopR_36 wr_buf_reg_1_36(wr_buf_1_out,mux_1_out,ss_clock,~wb1_hold_lo,ss_reset) ;
MflipflopR_36 wr_buf_reg_2_36(wr_buf_2_out,mux_2_out,ss_clock,~wb2_hold_lo,ss_reset) ;
MflipflopR_36 wr_buf_reg_3_36(wr_buf_3_out,mux_3_out,ss_clock,~wb3_hold_lo,ss_reset) ;
assign wb_3_size = wr_buf_3_out[35:34] ;
assign wb_3_asi = wr_buf_3_out[33:32] ;
//
// The following is the major mux control signals in this modules
//
// decode operation for asi tlb cam h/l write and sram direct write
wire asi_cam_write_h = asi_dcd6 & wr_buf_3_out[8] & wr_buf_3_out[9];
wire asi_cam_write_l = asi_dcd6 & wr_buf_3_out[8] & ~wr_buf_3_out[9];
wire asi_ram_write = asi_dcd6 & ~wr_buf_3_out[8] & ~wr_buf_3_out[9];
wire not_hld_cam_h = cam_reg_hld & ~asi_cam_write_h; // hold pin for cam high
wire not_hld_cam_l = (cam_reg_hld & ~asi_cam_write_l) | // hold pin for cam low
(cam_reg_hld & ~tw_tlb_vbit);
wire not_hld_ram = ram_reg_hld & ~asi_ram_write; // hold pin for ram write
// mux selection for context portion of va mux
wire [2:0] cxr_mux_sel = {(~asi_dcd6 & ~(cpu_walk & mmu_ptp_in & ~tw_io_bit)),
(~asi_dcd6 & (cpu_walk & mmu_ptp_in & ~cam_reg_hld) & ~tw_io_bit),
(asi_dcd6 | (cpu_walk & mmu_ptp_in & cam_reg_hld))};
// mux selection wire for level bit but for asi write mode
// REGWIRE mdat_sel_reg;
// REGR(mdat_sel_reg_ff,1,mdat_sel_reg,sel_mdat_mux,ss_clock,1'b0,ss_reset)
// Inverted copy (to match physical datapath)
// REGWIRE mdat_sel_reg2;
// REGR(mdat_sel_reg2_ff,1,mdat_sel_reg2,~sel_mdat_mux,ss_clock,1'b0,ss_reset)
/***************************************************************************/
/*** NOTE: change DPA muxes, such that tb_out doesn't need inversion ******/
/***************************************************************************/
/*** Decode for DPA level 1 address [23:18] selects */
/** TIMING NOTE: dpa_sel_l1 IS timing critical, the inputs "tb_out" */
/** are read from the TLB RAM in the current cycle. */
wire dpa_sel_l1 = (dpa_sel_b | (~cpu_walk & ~tb_out[26]));
/*** Decode for DPA level 2 address [17:12] selects */
/** TIMING NOTE: dpa_sel_l2 IS timing critical, the inputs "tb_out" */
/** are read from the TLB RAM in the current cycle. */
wire dpa_sel_l2 = (dpa_sel_b | (~cpu_walk & ~tb_out[25]));
wire dpa_sel_10d = ~(cpu_walk & ~ctpr_sel) ;
/***************************************************************************/
/** Registers added for iu_iva and iu_dva ** */
wire [31:02] i_vaddr_reg;
MflipflopR_30 iu_iva_reg_30(i_vaddr_reg,i_vaddr,ss_clock,ic_miss,ss_reset) ;
wire [31:0] r_i_vaddr = {i_vaddr_reg, 2'b0};
wire [31:0] r_d_vaddr;
MflipflopR_32 iu_dva_reg_32(r_d_vaddr,d_vaddr,ss_clock,pipe_hold4mmu_dp,ss_reset) ;
assign r_d_vaddr_out = r_d_vaddr[12:2];
/***************************************************************************/
/***** Add register for vbit to TLB. This pipeline reg. is for dp */
/********************************************************************/
/* Valid mux (2:1) selecting either vbit (always 1) or misc_in. */
/***** Bit [41] of the TLB TAG input ********************************/
/*** cam_reg_hld = 1 select from shdow reg ****/
/** this mux is to move the asi_w mux to top of va_mux for timing reason **/
// Expanded macro begin.
// cmux2(asi_v_mux, 1, asi_v_in, misc_in[3], tlb_cam_reg[13], not_hld_cam_h)
function [1:1] asi_v_mux ;
input [1:1] in0_fn ;
input [1:1] in1_fn ;
input select_fn ;
reg [1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
asi_v_mux = out_fn ;
end
endfunction
assign asi_v_in = asi_v_mux( misc_in[3], tlb_cam_reg[13], not_hld_cam_h) ;
// Expanded macro end.
// Expanded macro begin.
// cmux2(tlb_vbit_mux, 1, tlb_vbit_out, tw_tlb_vbit, asi_v_in, sel_mdat_mux)
function [1:1] tlb_vbit_mux ;
input [1:1] in0_fn ;
input [1:1] in1_fn ;
input select_fn ;
reg [1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
tlb_vbit_mux = out_fn ;
end
endfunction
assign tlb_vbit_out = tlb_vbit_mux( tw_tlb_vbit, asi_v_in, sel_mdat_mux) ;
// Expanded macro end.
/***** Bit [03] of the TLB TAG input ********************************/
// Expanded macro begin.
// cmux2(asi_s_mux, 1, asi_s_bit, misc_in[3], tlb_cam_reg[3], not_hld_cam_l)
function [1:1] asi_s_mux ;
input [1:1] in0_fn ;
input [1:1] in1_fn ;
input select_fn ;
reg [1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
asi_s_mux = out_fn ;
end
endfunction
assign asi_s_bit = asi_s_mux( misc_in[3], tlb_cam_reg[3], not_hld_cam_l) ;
// Expanded macro end.
wire asi_s_in = asi_s_bit | io_s_bit;
wire tlb_sbit_in = tlb_wrt_tag | tlb_s_bit ;
// Expanded macro begin.
// cmux4d(va_tag_mux_2, 1, tlb_sbit_out, iva_s_in, va_mux0_sel[0], dva_s_in, va_mux0_sel[1], asi_s_in, va_mux0_sel[2], tlb_sbit_in, va_mux0_sel[3])
function [ 1:1] va_tag_mux_2 ;
input [ 1:1] in0_fn ;
input s0_fn ;
input [ 1:1] in1_fn ;
input s1_fn ;
input [ 1:1] in2_fn ;
input s2_fn ;
input [ 1:1] in3_fn ;
input s3_fn ;
reg [ 1:1] out_fn ;
begin
case ({ va_mux0_sel[3], va_mux0_sel[2], va_mux0_sel[1], va_mux0_sel[0]}) /* synopsys parallel_case */
4'b0001: out_fn = in0_fn;
4'b0010: out_fn = in1_fn;
4'b0100: out_fn = in2_fn;
4'b1000: out_fn = in3_fn;
default: out_fn = 65'hx;
endcase
va_tag_mux_2 = out_fn ;
end
endfunction
assign tlb_sbit_out = va_tag_mux_2( iva_s_in, va_mux0_sel[0], dva_s_in, va_mux0_sel[1], asi_s_in, va_mux0_sel[2], tlb_sbit_in, va_mux0_sel[3]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( va_mux0_sel[3]+ va_mux0_sel[2]+ va_mux0_sel[1]+ va_mux0_sel[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( va_mux0_sel[3]+ va_mux0_sel[2]+ va_mux0_sel[1]^ va_mux0_sel[0]===1'bx)) begin
$display("### %m.va_tag_mux_2: CMUX4D select error!\n");
$display(" va_mux0_sel[3], va_mux0_sel[2], va_mux0_sel[1], va_mux0_sel[0]=%0d%0d%0d%0d\n", va_mux0_sel[3], va_mux0_sel[2], va_mux0_sel[1], va_mux0_sel[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/***** Bit [9:4] of the TLB TAG input ******************************/
// add tlb_pro from mmu-cntl --> decoded protection bits
// Decode prot bits from acc for tag - misc_in[4:2]
// Force all protection bits on for IO PTEs. (allows any compare).
// UE = prot[5]
assign acc_prot[5] = (misc_in[4:2] == 3'h2) | (misc_in[4:2] == 3'h3) |
(misc_in[4:2] == 3'h4) | io_walk;
// UR = prot[4]
assign acc_prot[4] = (misc_in[4:2] == 3'h0) | (misc_in[4:2] == 3'h1) |
(misc_in[4:2] == 3'h2) | (misc_in[4:2] == 3'h3) |
(misc_in[4:2] == 3'h5) | io_walk;
// UW = prot[3]
assign acc_prot[3] = (misc_in[4:2] == 3'h1) | (misc_in[4:2] == 3'h3) |
io_walk;
// SE = prot[2]
assign acc_prot[2] = (misc_in[4:2] == 3'h2) | (misc_in[4:2] == 3'h3) |
(misc_in[4:2] == 3'h4) | (misc_in[4:2] == 3'h6) |
(misc_in[4:2] == 3'h7) | io_walk;
// SR = prot[1]
assign acc_prot[1] = (misc_in[4:2] != 3'h4) | io_walk;
// SW = prot[0]
assign acc_prot[0] = (misc_in[4:2] == 3'h1) | (misc_in[4:2] == 3'h3) |
(misc_in[4:2] == 3'h5) | (misc_in[4:2] == 3'h7) |
io_walk;
// MUX of all possible prot sources
wire[5:0] iu_f_prot = 6'b000100 ;
/********* TLB TAG bit [9:4] ************/
// Expanded macro begin.
// cmux2(asi_prot_mux, 6, asi_prot_in, misc_in[9:4], tlb_cam_reg[9:4], not_hld_cam_l)
function [6:1] asi_prot_mux ;
input [6:1] in0_fn ;
input [6:1] in1_fn ;
input select_fn ;
reg [6:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
asi_prot_mux = out_fn ;
end
endfunction
assign asi_prot_in = asi_prot_mux( misc_in[9:4], tlb_cam_reg[9:4], not_hld_cam_l) ;
// Expanded macro end.
// Expanded macro begin.
// cmux3d(prot_mux, 6, tlb_pro_bits, tlb_acc_cmp, mbit_sel[0], /* For TLB lookups */ acc_prot, mbit_sel[1], /* For TW writes */ asi_prot_in, mbit_sel[2])
function [6:1] prot_mux ;
input [6:1] in0_fn ;
input s0_fn ;
input [6:1] in1_fn ;
input s1_fn ;
input [6:1] in2_fn ;
input s2_fn ;
reg [6:1] out_fn ;
begin
case ({ mbit_sel[2], mbit_sel[1], mbit_sel[0]}) /* synopsys parallel_case */
3'b001: out_fn = in0_fn;
3'b010: out_fn = in1_fn;
3'b100: out_fn = in2_fn;
default: out_fn = 65'hx;
endcase
prot_mux = out_fn ;
end
endfunction
assign tlb_pro_bits = prot_mux( tlb_acc_cmp, mbit_sel[0], /* For TLB lookups */ acc_prot, mbit_sel[1], /* For TW writes */ asi_prot_in, mbit_sel[2]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( mbit_sel[2]+ mbit_sel[1]+ mbit_sel[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( mbit_sel[2]+ mbit_sel[1]^ mbit_sel[0]===1'bx)) begin
$display("### %m.prot_mux: CMUX3D select error!\n");
$display(" mbit_sel[2], mbit_sel[1], mbit_sel[0]=%0d%0d%0d\n", mbit_sel[2], mbit_sel[1], mbit_sel[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/* For ASI writes */
// Now the same for the mod bit
//
/**** modify bit TLB TAG [0] *****/
/***** Bit [4] of the TLB DATA input (m bit)********************************/
/***** Set Mbit in if entry is a PTE and entry is written ***********/
// Always set Mbit for IO PTE.
wire tlb_mbit_in = (msm_mbit_in & misc_in[1]) | io_walk;
// Expanded macro begin.
// cmux2(asi_mod_mux, 1, asi_mod_in, misc_in[0], tlb_cam_reg[0], /* Software map */ not_hld_cam_l)
function [1:1] asi_mod_mux ;
input [1:1] in0_fn ;
input [1:1] in1_fn ;
input select_fn ;
reg [1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
asi_mod_mux = out_fn ;
end
endfunction
assign asi_mod_in = asi_mod_mux( misc_in[0], tlb_cam_reg[0], /* Software map */ not_hld_cam_l) ;
// Expanded macro end.
wire asi_data_m_in;
// Expanded macro begin.
// cmux2(asi_data_m_mux, 1, asi_data_m_in, misc_in[6], tlb_data_reg[4], not_hld_ram)
function [1:1] asi_data_m_mux ;
input [1:1] in0_fn ;
input [1:1] in1_fn ;
input select_fn ;
reg [1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
asi_data_m_mux = out_fn ;
end
endfunction
assign asi_data_m_in = asi_data_m_mux( misc_in[6], tlb_data_reg[4], not_hld_ram) ;
// Expanded macro end.
// Expanded macro begin.
// cmux2(tw_mbit_mux, 1, tw_mbit, asi_data_m_in, tlb_mbit_in, tlb_mbit_in)
function [ 1:1] tw_mbit_mux ;
input [ 1:1] in0_fn ;
input [ 1:1] in1_fn ;
input select_fn ;
reg [ 1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
tw_mbit_mux = out_fn ;
end
endfunction
assign tw_mbit = tw_mbit_mux( asi_data_m_in, tlb_mbit_in, tlb_mbit_in) ;
// Expanded macro end.
/* If mbit set, select it (LOAD a 1).*/
// Expanded macro begin.
// cmux3d(mbit_mux, 1, tlb_cam_mbit, tlb_mbit_cmp, mbit_sel[0], /* For TLB lookups */ tw_mbit, mbit_sel[1], /* For TW writes */ asi_mod_in, mbit_sel[2])
function [ 1:1] mbit_mux ;
input [ 1:1] in0_fn ;
input s0_fn ;
input [ 1:1] in1_fn ;
input s1_fn ;
input [ 1:1] in2_fn ;
input s2_fn ;
reg [ 1:1] out_fn ;
begin
case ({ mbit_sel[2], mbit_sel[1], mbit_sel[0]}) /* synopsys parallel_case */
3'b001: out_fn = in0_fn;
3'b010: out_fn = in1_fn;
3'b100: out_fn = in2_fn;
default: out_fn = 65'hx;
endcase
mbit_mux = out_fn ;
end
endfunction
assign tlb_cam_mbit = mbit_mux( tlb_mbit_cmp, mbit_sel[0], /* For TLB lookups */ tw_mbit, mbit_sel[1], /* For TW writes */ asi_mod_in, mbit_sel[2]) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( mbit_sel[2]+ mbit_sel[1]+ mbit_sel[0] !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( mbit_sel[2]+ mbit_sel[1]^ mbit_sel[0]===1'bx)) begin
$display("### %m.mbit_mux: CMUX3D select error!\n");
$display(" mbit_sel[2], mbit_sel[1], mbit_sel[0]=%0d%0d%0d\n", mbit_sel[2], mbit_sel[1], mbit_sel[0]);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
/* For ASI writes */
/* IO bit register and mux providing mdata visibility */
/***** Bit [02] of the TLB TAG input ********************************/
// Expanded macro begin.
// cmux2(asi_io_mux, 1, asi_io_in, misc_in[2], tlb_cam_reg[2], /* Software map */ not_hld_cam_l)
function [1:1] asi_io_mux ;
input [1:1] in0_fn ;
input [1:1] in1_fn ;
input select_fn ;
reg [1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
asi_io_mux = out_fn ;
end
endfunction
assign asi_io_in = asi_io_mux( misc_in[2], tlb_cam_reg[2], /* Software map */ not_hld_cam_l) ;
// Expanded macro end.
// Expanded macro begin.
// cmux2(tlb_iobit_mux, 1, tlb_io_bit_out, io_tlb_nxt, asi_io_in, sel_mdat_mux)
function [ 1:1] tlb_iobit_mux ;
input [ 1:1] in0_fn ;
input [ 1:1] in1_fn ;
input select_fn ;
reg [ 1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
tlb_iobit_mux = out_fn ;
end
endfunction
assign tlb_io_bit_out = tlb_iobit_mux( io_tlb_nxt, asi_io_in, sel_mdat_mux) ;
// Expanded macro end.
/* PTP bit mux providing mdata visibility */
/***** Bit [3] of the TLB DATA input ********************************/
// Expanded macro begin.
// cmux2(asi_data_r_mux, 1, asi_data_r_in, misc_in[5], tlb_data_reg[3], not_hld_ram)
function [1:1] asi_data_r_mux ;
input [1:1] in0_fn ;
input [1:1] in1_fn ;
input select_fn ;
reg [1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
asi_data_r_mux = out_fn ;
end
endfunction
assign asi_data_r_in = asi_data_r_mux( misc_in[5], tlb_data_reg[3], not_hld_ram) ;
// Expanded macro end.
// here is , if not_hld_ram means not in asi tlb ram read access process
// so, r bit will be decide bit bit [1] & bit [5]
wire misc_or_asi_in = misc_in[1] & ~not_hld_ram;
wire pte_r_bit = (misc_in[1] & tw_tlb_vbit) |
(~tw_tlb_vbit & misc_in[5]) ;
// Expanded macro begin.
// cmux2(tlb_rbit_mux, 1, tlb_rbit_out, asi_data_r_in, pte_r_bit, misc_or_asi_in)
function [ 1:1] tlb_rbit_mux ;
input [ 1:1] in0_fn ;
input [ 1:1] in1_fn ;
input select_fn ;
reg [ 1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
tlb_rbit_mux = out_fn ;
end
endfunction
assign tlb_rbit_out = tlb_rbit_mux( asi_data_r_in, pte_r_bit, misc_or_asi_in) ;
// Expanded macro end.
/* If input PTE select mdata[01] */
/***** TLB data input mux (3-bits). Selects between misc_in ******/
/**** and state machine input for bits [5:4]. ******/
wire [27:0] tlb_data_in_mem = { tlb_lvl_sram_out, /* sram level bits */
misc1_in,
tw_mbit, /* modified bit input*/
tlb_rbit_out, /* reference bit input*/
misc2_in};
// Expanded macro begin.
// cmux2(tlb_dtat_in_mux, 28, tlb_data_in, tlb_data_in_mem, /* PTP/PTE from mem */ tb_out, /* TLB output */ tw_rewrite_cam)
function [28:1] tlb_dtat_in_mux ;
input [28:1] in0_fn ;
input [28:1] in1_fn ;
input select_fn ;
reg [28:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
tlb_dtat_in_mux = out_fn ;
end
endfunction
assign tlb_data_in = tlb_dtat_in_mux( tlb_data_in_mem, /* PTP/PTE from mem */ tb_out, /* TLB output */ tw_rewrite_cam) ;
// Expanded macro end.
/* PTP bit mux providing mdata visibility */
/***** Bit [1] of the TLB TAG input ********************************/
// Expanded macro begin.
// cmux2(asi_ptp_mux, 1, asi_ptp_in, misc_in[1], tlb_cam_reg[1], /* Software map */ not_hld_cam_l)
function [1:1] asi_ptp_mux ;
input [1:1] in0_fn ;
input [1:1] in1_fn ;
input select_fn ;
reg [1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
asi_ptp_mux = out_fn ;
end
endfunction
assign asi_ptp_in = asi_ptp_mux( misc_in[1], tlb_cam_reg[1], /* Software map */ not_hld_cam_l) ;
// Expanded macro end.
// Expanded macro begin.
// cmux2(tlb_bits_mux, 1, tlb_ptp_out, mmu_ptp_in, asi_ptp_in, sel_mdat_mux)
function [ 1:1] tlb_bits_mux ;
input [ 1:1] in0_fn ;
input [ 1:1] in1_fn ;
input select_fn ;
reg [ 1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
| This page: |
Created: | Thu Aug 19 11:59:27 1999 |
| From: |
../../../sparc_v8/ssparc/mmu/dp_mmu/rtl/dp_mmu.v
|