/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
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/******************************************************************************/
// @(#)herbulator.v 1.14 2/24/93
//
// This file contains the
// fpu rotator for aligning the FP load bus
// and a 64b IU load aligner
// add little_endian input to indicate Current Little Endian if its value is 1
![[Up: rl_dc_cntl herbulator]](v2html-up.gif)
module herbulator
(
little_endian, // added to indicate Current_Little_Endian if it is a 1
din, // Input bus to load aligner, 64b
ld_iu, // Output to IU, timing critical
ld_fpu, // Output to FPU
lddi_r, // Only int load double is 2 cycles
sel_ld_fpu_w, // fp_op_e, floating point ld
iu_held,
sgnd_ld_e, // signed/unsigned ld ?
size_w, // byte/hw/w/dw ?
iu_dva_w, // 3 lsb's of dva address [2:0]
ss_reset,
rt_clk
) ;
input little_endian;
input [63:0] din;
output [31:0] ld_iu;
output [63:0] ld_fpu;
input [1:0] size_w;
input [2:0] iu_dva_w;
input lddi_r ;
input sel_ld_fpu_w ;
input iu_held ;
input sgnd_ld_e ;
input rt_clk ;
input ss_reset ;
wire [7:0] int_mux_sel;
wire [31:0] iu_odd_r;
wire [63:0] ld_iu_w;
wire [1:0] size_w;
wire sb_w;
// Register the odd word for 2 cycle lddi, upto the IU to select
// this in the next cycle, with "lddi_r".
Mflipflop_32 iu_odd_reg(iu_odd_r[31:0], ld_iu_w[63:32], rt_clk, iu_held);
// scan in, scan out.
// assign rt_scan_out = iu_odd_r[31];
// FPU related bus
wire [2:0] fpu_sel;
assign fpu_sel = {little_endian, sel_ld_fpu_w, iu_dva_w[2]};
assign ld_fpu[63:56] = fpu_sel7(fpu_sel, din);
assign ld_fpu[55:48] = fpu_sel6(fpu_sel, din);
assign ld_fpu[47:40] = fpu_sel5(fpu_sel, din);
assign ld_fpu[39:32] = fpu_sel4(fpu_sel, din);
assign ld_fpu[31:24] = fpu_sel3(fpu_sel, din);
assign ld_fpu[23:16] = fpu_sel2(fpu_sel, din);
assign ld_fpu[15:08] = fpu_sel1(fpu_sel, din);
assign ld_fpu[07:00] = fpu_sel0(fpu_sel, din);
function [7:0] fpu_sel7;
input [2:0] fpu_sel;
input [63:00] din;
begin
casex (fpu_sel)
3'b11x: fpu_sel7 = din[07:00];
3'b10x: fpu_sel7 = din[39:32];
3'b0x1: fpu_sel7 = din[31:24];
3'b0x0: fpu_sel7 = din[63:56];
endcase
end
endfunction
function [7:0] fpu_sel6;
input [2:0] fpu_sel;
input [63:00] din;
begin
casex (fpu_sel)
3'b11x: fpu_sel6 = din[15:08];
3'b10x: fpu_sel6 = din[47:40];
3'b0x1: fpu_sel6 = din[23:16];
3'b0x0: fpu_sel6 = din[55:48];
endcase
end
endfunction
function [7:0] fpu_sel5;
input [2:0] fpu_sel;
input [63:00] din;
begin
casex (fpu_sel)
3'b11x: fpu_sel5 = din[23:16];
3'b10x: fpu_sel5 = din[55:48];
3'b0x1: fpu_sel5 = din[15:08];
3'b0x0: fpu_sel5 = din[47:40];
endcase
end
endfunction
function [7:0] fpu_sel4;
input [2:0] fpu_sel;
input [63:00] din;
begin
casex (fpu_sel)
3'b11x: fpu_sel4 = din[31:24];
3'b10x: fpu_sel4 = din[63:56];
3'b0x1: fpu_sel4 = din[07:00];
3'b0x0: fpu_sel4 = din[39:32];
endcase
end
endfunction
function [7:0] fpu_sel3;
input [2:0] fpu_sel;
input [63:00] din;
begin
casex (fpu_sel)
3'b1x1: fpu_sel3 = din[07:00];
3'b1x0: fpu_sel3 = din[39:32];
3'b01x: fpu_sel3 = din[31:24];
3'b00x: fpu_sel3 = din[63:56];
endcase
end
endfunction
function [7:0] fpu_sel2;
input [2:0] fpu_sel;
input [63:00] din;
begin
casex (fpu_sel)
3'b1x1: fpu_sel2 = din[15:08];
3'b1x0: fpu_sel2 = din[47:40];
3'b01x: fpu_sel2 = din[23:16];
3'b00x: fpu_sel2 = din[55:48];
endcase
end
endfunction
function [7:0] fpu_sel1;
input [2:0] fpu_sel;
input [63:00] din;
begin
casex (fpu_sel)
3'b1x1: fpu_sel1 = din[23:16];
3'b1x0: fpu_sel1 = din[55:48];
3'b01x: fpu_sel1 = din[15:08];
3'b00x: fpu_sel1 = din[47:40];
endcase
end
endfunction
function [7:0] fpu_sel0;
input [2:0] fpu_sel;
input [63:00] din;
begin
casex (fpu_sel)
3'b1x1: fpu_sel0 = din[31:24];
3'b1x0: fpu_sel0 = din[63:56];
3'b01x: fpu_sel0 = din[07:00];
3'b00x: fpu_sel0 = din[39:32];
endcase
end
endfunction
/*
assign ld_fpu[63:56] = little_endian? (sel_ld_fpu_w ? din[07:00] : din[39:32]) : (iu_dva_w[2] ? din[31:24] : din[63:56]);
assign ld_fpu[55:48] = little_endian? (sel_ld_fpu_w ? din[15:08] : din[47:40]) : (iu_dva_w[2] ? din[23:16] : din[55:48]);
assign ld_fpu[47:40] = little_endian? (sel_ld_fpu_w ? din[23:16] : din[55:48]) : (iu_dva_w[2] ? din[15:08] : din[47:40]);
assign ld_fpu[39:32] = little_endian? (sel_ld_fpu_w ? din[31:24] : din[63:56]) : (iu_dva_w[2] ? din[07:00] : din[39:32]);
assign ld_fpu[31:24] = little_endian? (iu_dva_w[2] ? din[07:00] : din[39:32]) : (sel_ld_fpu_w ? din[31:24] : din[63:56]);
assign ld_fpu[23:16] = little_endian? (iu_dva_w[2] ? din[15:08] : din[47:40]) : (sel_ld_fpu_w ? din[23:16] : din[55:48]);
assign ld_fpu[15:08] = little_endian? (iu_dva_w[2] ? din[23:16] : din[55:48]) : (sel_ld_fpu_w ? din[15:08] : din[47:40]);
assign ld_fpu[07:00] = little_endian? (iu_dva_w[2] ? din[31:24] : din[63:56]) : (sel_ld_fpu_w ? din[07:00] : din[39:32]);
*/
// address{ 7, 6, 5, 4, 3, 2, 1, 0 }
// INPUT {(S0,B0),(S1,B1),(S2,B2),(S3,B3),(S4,B4),(S5,B5),(S6,B6),(S7,B7)}
// Big-endian odering
// INPUT {(S0,B7),(S1,B6),(S2,B5),(S3,B4),(S4,B3),(S5,B2),(S6,B1),(S7,B0)}
// Little-endian odering
// Datapath ? or standard cell muxes..
// Control bits
MflipflopR sgnd_ld_ff(s_ld_w, sgnd_ld_e, rt_clk, iu_held, ss_reset);
// Mutually exclusive signals
wire by_w = (size_w==0);
wire hw_w = (size_w==1);
wire wd_w = (size_w==2);
wire dw_w = (size_w==3);
// Mutually exclusive signals
wire dva_0 = (iu_dva_w==0);
wire dva_1 = (iu_dva_w==1);
wire dva_2 = (iu_dva_w==2);
wire dva_3 = (iu_dva_w==3);
wire dva_4 = (iu_dva_w==4);
wire dva_5 = (iu_dva_w==5);
wire dva_6 = (iu_dva_w==6);
wire dva_7 = (iu_dva_w==7);
wire [5:0] iu_data_sel;
wire [6:0] sb_data_sel;
assign iu_data_sel[5:0] = {little_endian, size_w[1:0], iu_dva_w[2:0]};
assign sb_data_sel[6:0] = {s_ld_w, iu_data_sel[5:0]};
assign sb_w = sb_w_bit(sb_data_sel, din);
function sb_w_bit;
input [6:0] sb_data_sel;
input [63:00] din;
begin
casex (sb_data_sel)
7'b1100111: sb_w_bit = din[07];
7'b1101110: sb_w_bit = din[07];
7'b1100110: sb_w_bit = din[15];
7'b1100101: sb_w_bit = din[23];
7'b1101100: sb_w_bit = din[23];
7'b1100100: sb_w_bit = din[31];
7'b1100011: sb_w_bit = din[39];
7'b1101010: sb_w_bit = din[39];
7'b1100010: sb_w_bit = din[47];
7'b1100001: sb_w_bit = din[55];
7'b1101000: sb_w_bit = din[55];
7'b1100000: sb_w_bit = din[63];
7'b1000111: sb_w_bit = din[07];
7'b1000110: sb_w_bit = din[15];
7'b1001110: sb_w_bit = din[15];
7'b1000101: sb_w_bit = din[23];
7'b1000100: sb_w_bit = din[31];
7'b1001100: sb_w_bit = din[31];
7'b1000011: sb_w_bit = din[39];
7'b1000010: sb_w_bit = din[47];
7'b1001010: sb_w_bit = din[47];
7'b1000001: sb_w_bit = din[55];
7'b1000000: sb_w_bit = din[63];
7'b1001000: sb_w_bit = din[63];
7'b0xxxxxx: sb_w_bit = 1'b0;
default: sb_w_bit = 1'bx;
endcase
end
endfunction
/*
// Cache RAMs should try to generate these sign bits fast
// {63,55,47,39,31,23,15,7}
wire sb_w = little_endian ? ((s_ld_w & by_w & dva_7)|(s_ld_w & hw_w & dva_6)) ? din[07] : (
(s_ld_w & by_w & dva_6) ? din[15] : (
((s_ld_w & by_w & dva_5)|(s_ld_w & hw_w & dva_4)) ? din[23] : (
(s_ld_w & by_w & dva_4) ? din[31] : (
((s_ld_w & by_w & dva_3)|(s_ld_w & hw_w & dva_2)) ? din[39] : (
(s_ld_w & by_w & dva_2) ? din[47] : (
((s_ld_w & by_w & dva_1)|(s_ld_w & hw_w & dva_0)) ? din[55] : (
(s_ld_w & by_w & dva_0) ? din[63] : (
(~s_ld_w) ? 1'b0 : (
'bx ))))))))) :
(s_ld_w & by_w & dva_7) ? din[07] : (
((s_ld_w & by_w & dva_6)|(s_ld_w & hw_w & dva_6)) ? din[15] : (
(s_ld_w & by_w & dva_5) ? din[23] : (
((s_ld_w & by_w & dva_4)|(s_ld_w & hw_w & dva_4)) ? din[31] : (
(s_ld_w & by_w & dva_3) ? din[39] : (
((s_ld_w & by_w & dva_2)|(s_ld_w & hw_w & dva_2)) ? din[47] : (
(s_ld_w & by_w & dva_1) ? din[55] : (
((s_ld_w & by_w & dva_0)|(s_ld_w & hw_w & dva_0)) ? din[63] : (
(~s_ld_w) ? 1'b0 : (
'bx )))))))));
*/
// IU bus
assign ld_iu_w[07:00] = data_sel0(iu_data_sel, din, sb_w);
assign ld_iu_w[15:08] = data_sel1(iu_data_sel, din, sb_w);
assign ld_iu_w[23:16] = data_sel2(iu_data_sel, din, sb_w);
assign ld_iu_w[31:24] = data_sel3(iu_data_sel, din, sb_w);
function [7:0] data_sel0;
input [5:0] iu_data_sel;
input [63:00] din;
input sb_w;
begin
casex (iu_data_sel)
6'b100111: data_sel0 = din[07:00];
6'b100110: data_sel0 = din[15:08];
6'b101110: data_sel0 = din[15:08];
6'b100101: data_sel0 = din[23:16];
6'b100100: data_sel0 = din[31:24];
6'b101100: data_sel0 = din[31:24];
6'b110100: data_sel0 = din[31:24];
6'b111xxx: data_sel0 = din[31:24];
6'b100011: data_sel0 = din[39:32];
6'b100010: data_sel0 = din[47:40];
6'b101010: data_sel0 = din[47:40];
6'b100001: data_sel0 = din[55:48];
6'b100000: data_sel0 = din[63:56];
6'b101000: data_sel0 = din[63:56];
6'b110000: data_sel0 = din[63:56];
6'b000111: data_sel0 = din[07:00];
6'b001110: data_sel0 = din[07:00];
6'b010100: data_sel0 = din[07:00];
6'b000110: data_sel0 = din[15:08];
6'b000101: data_sel0 = din[23:16];
6'b001100: data_sel0 = din[23:16];
6'b000100: data_sel0 = din[31:24];
6'b000011: data_sel0 = din[39:32];
6'b001010: data_sel0 = din[39:32];
6'b010000: data_sel0 = din[39:32];
6'b011xxx: data_sel0 = din[39:32];
6'b000010: data_sel0 = din[47:40];
6'b000001: data_sel0 = din[55:48];
6'b001000: data_sel0 = din[55:48];
6'b000000: data_sel0 = din[63:56];
default: data_sel0 = 8'bx;
endcase
end
endfunction
function [7:0] data_sel1;
input [5:0] iu_data_sel;
input [63:00] din;
input sb_w;
begin
casex (iu_data_sel)
6'b101110: data_sel1 = din[07:00];
6'b101100: data_sel1 = din[23:16];
6'b110100: data_sel1 = din[23:16];
6'b111xxx: data_sel1 = din[23:16];
6'b101010: data_sel1 = din[39:32];
6'b101000: data_sel1 = din[55:48];
6'b110000: data_sel1 = din[55:48];
6'b100xxx: data_sel1 = {8{sb_w}};
6'b001110: data_sel1 = din[15:08];
6'b010100: data_sel1 = din[15:08];
6'b001100: data_sel1 = din[31:24];
6'b001010: data_sel1 = din[47:40];
6'b010000: data_sel1 = din[47:40];
6'b011xxx: data_sel1 = din[47:40];
6'b001000: data_sel1 = din[63:56];
6'b000xxx: data_sel1 = {8{sb_w}};
default: data_sel1 = 8'bx;
endcase
end
endfunction
function [7:0] data_sel2;
input [5:0] iu_data_sel;
input [63:00] din;
input sb_w;
begin
casex (iu_data_sel)
6'b110100: data_sel2 = din[15:08];
6'b111xxx: data_sel2 = din[15:08];
6'b110000: data_sel2 = din[47:40];
6'b100xxx: data_sel2 = {8{sb_w}};
6'b101xxx: data_sel2 = {8{sb_w}};
6'b010100: data_sel2 = din[23:16];
6'b010000: data_sel2 = din[55:48];
6'b011xxx: data_sel2 = din[55:48];
6'b000xxx: data_sel2 = {8{sb_w}};
6'b001xxx: data_sel2 = {8{sb_w}};
default: data_sel2 = 8'bx;
endcase
end
endfunction
function [7:0] data_sel3;
input [5:0] iu_data_sel;
input [63:00] din;
input sb_w;
begin
casex (iu_data_sel)
6'b110100: data_sel3 = din[07:00];
6'b111xxx: data_sel3 = din[07:00];
6'b110000: data_sel3 = din[39:32];
6'b100xxx: data_sel3 = {8{sb_w}};
6'b101xxx: data_sel3 = {8{sb_w}};
6'b010100: data_sel3 = din[31:24];
6'b010000: data_sel3 = din[63:56];
6'b011xxx: data_sel3 = din[63:56];
6'b000xxx: data_sel3 = {8{sb_w}};
6'b001xxx: data_sel3 = {8{sb_w}};
default: data_sel3 = 8'bx;
endcase
end
endfunction
/*
// BYTE 0
assign ld_iu_w[7:0] = little_endian ?
(by_w & dva_7) ? din[07:00] : (
((by_w & dva_6)|(hw_w & dva_6)) ? din[15:08] : (
(by_w & dva_5) ? din[23:16] : (
((by_w & dva_4) |(hw_w & dva_4) |(wd_w & dva_4) | (dw_w)) ? din[31:24] : (
(by_w & dva_3) ? din[39:32] : (
((by_w & dva_2)|(hw_w & dva_2)) ? din[47:40] : (
(by_w & dva_1) ? din[55:48] : (
((by_w & dva_0)|(hw_w & dva_0)|(wd_w & dva_0)) ? din[63:56] : (
'bx )))))))) :
((by_w & dva_7)|(hw_w & dva_6)|(wd_w & dva_4)) ? din[07:00] : (
(by_w & dva_6) ? din[15:08] : (
((by_w & dva_5)|(hw_w & dva_4)) ? din[23:16] : (
(by_w & dva_4) ? din[31:24] : (
((by_w & dva_3)|(hw_w & dva_2)|(wd_w & dva_0)|(dw_w)) ? din[39:32] : (
((by_w & dva_2) ? din[47:40] : (
((by_w & dva_1)|(hw_w & dva_0)) ? din[55:48] : (
(by_w & dva_0 ) ? din[63:56] : (
'bx )))))))));
// BYTE 1
assign ld_iu_w[15:8] = little_endian ?
(hw_w & dva_6) ? din[07:00] : (
((hw_w & dva_4)|(wd_w & dva_4)|(dw_w)) ? din[23:16] : (
(hw_w & dva_2) ? din[39:32] : (
((hw_w & dva_0)|(wd_w & dva_0)) ? din[55:48] : (
(by_w) ? {{8{sb_w}} : (
'bx ))))) :
((hw_w & dva_6)|(wd_w & dva_4)) ? din[15:08] : (
(hw_w & dva_4) ? din[31:24] : (
((hw_w & dva_2)|(wd_w & dva_0)|(dw_w)) ? din[47:40] : (
(hw_w & dva_0) ? din[63:56] : (
(by_w) ? {{8{sb_w}} : (
'bx )))));
// BYTE 2
assign ld_iu_w[23:16] = little_endian ?
((wd_w & dva_4)|(dw_w)) ? din[15:08] : (
(wd_w & dva_0) ? din[47:40] : (
(by_w | hw_w) ? {{8{sb_w}} : (
'bx ))) :
(wd_w & dva_4) ? din[23:16] : (
(wd_w & dva_0) ? din[55:48] : (
(dw_w) ? din[55:48] : (
(by_w | hw_w) ? {{8{sb_w}} : (
'bx ))));
// BYTE 3
assign ld_iu_w[31:24] = little_endian ?
((wd_w & dva_4)|(dw_w)) ? din[07:00] : (
(wd_w & dva_0) ? din[39:32] : (
(by_w | hw_w) ? {{8{sb_w}} : (
'bx ))) :
(wd_w & dva_4) ? din[31:24] : (
(wd_w & dva_0) ? din[63:56] : (
(dw_w) ? din[63:56] : (
(by_w | hw_w) ? {{8{sb_w}} : (
'bx ))));
*/
assign ld_iu_w [63:56] = little_endian ? din[39:32] : din[31:24];
assign ld_iu_w [55:48] = little_endian ? din[47:40] : din[23:16];
assign ld_iu_w [47:40] = little_endian ? din[55:48] : din[15:08];
assign ld_iu_w [39:32] = little_endian ? din[63:56] : din[07:00];
assign ld_iu[31:0] = lddi_r ? iu_odd_r[31:0] : ld_iu_w[31:0] ;
endmodule
| This page: |
Created: | Thu Aug 19 11:57:43 1999 |
| From: |
../../../sparc_v8/ssparc/cc/rl_dc_cntl/rtl/herbulator.v
|