if ( (devsel_val !== 1'b0) ) begin
if ( (devsel_val !== 1'bz) ) begin
pdevselnn_out(1'bx, model_times.tpr_pclk_pdevselnn, -2 *`time_scale_multiplier);
end else begin
pdevselnn_out(1'bx, model_times.tpr_pclk_pdevselnn, 0 *`time_scale_multiplier);
end // if
pdevselnn_out(1'b0, model_times.tpr_pclk_pdevselnn,0 *`time_scale_multiplier);
devsel_val = 1'b0;
end // if
if ( (trdy_val !== 1'b0) ) begin
if ( (trdy_val!== 1'bz) ) begin
ptrdynn_out(1'bx, model_times.tpr_pclk_ptrdynn,-2 *`time_scale_multiplier);
end else begin
ptrdynn_out(1'bx, model_times.tpr_pclk_ptrdynn, 0 *`time_scale_multiplier);
end // if
ptrdynn_out(1'b0, model_times.tpr_pclk_ptrdynn, 0 *`time_scale_multiplier);
trdy_val = 1'b0;
end // if
case ( config_addr )
8'b00000000 : begin
pad_out(32'hxxxxxxxx, model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
reg_vector = {device_id,vendor_id};
pad_out(reg_vector, model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
// ad_val = reg_vector;
if (!((msg_level<`debug_1))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" ");
$display("");
$write("CONFIG READ");
$display("");
$write("ADDRESS = ");
$write("%h",(config_addr));
$write(" (DEVICE_ID | VENDOR_ID)");
$display("");
$write("DEVICE_ID = ");
$write("%h",(reg_vector[31:16]));
$display("");
$write("VECDOR_ID = ");
$write("%h",(reg_vector[15:0]));
$display("");
$display("\"");
end
end
8'b00000100 : begin
reg_vector = {status_reg,command_reg};
pad_out(32'hxxxxxxxx, model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
pad_out(reg_vector, model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
// ad_val = {status_reg,command_reg};
if (!((msg_level<`debug_1))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" ");
$display("");
$write("CONFIG READ");
$display("");
$write("ADDRESS = ");
$write("%h",config_addr);
$write(" (STATUS | COMMAND)");
$display("");
$write("STATUS = ");
$write("%h",reg_vector[31:16]);
$display("");
$write("COMMAND = ");
$write("%h",reg_vector[15:0]);
$display("");
$display("\"");
end
end
8'b00001000 : begin
reg_vector = {class_code,revision_id};
reg_vector = {class_code,revision_id};
pad_out(32'hxxxxxxxx, model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
pad_out(reg_vector, model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
// ad_val = {status_reg,command_reg};
if (!((msg_level<`debug_1))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" ");
$display("");
$write("CONFIG READ");
$display("");
$write("ADDRESS = ");
$write("%h",config_addr);
$write(" (CLASS CODE | REVISION_ID)");
$display("");
$write("CLASS CODE = ");
$write("%h",reg_vector[31:8]);
$display("");
$write("REVISION_ID = ");
$write("%h",reg_vector[7:0]);
$display("");
$display("\"");
end
end
8'b00001100 : begin
reg_vector = {16'b0000000000000000,latency_timer_reg,cacheline_size_reg}; // 12/13/94 added cacheline size reg to config-read.
pad_out(32'hxxxxxxxx, model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
pad_out(reg_vector, model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
// ad_val = {16'b0000000000000000,latency_timer_reg,8'b00000000};
if (!((msg_level<`debug_1))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" ");
$display("");
$write("CONFIG READ");
$display("");
$write("ADDRESS = ");
$write("%h",config_addr);
$write(" (LATENCY TIMER | CACHELINE SIZE)");
$display("");
$write("LATENCY TIMER = ");
$write("%h",reg_vector[15:8]);
$display("");
$write("CACHELINE SIZE = ");
$write("%h",reg_vector[7:0]);
$display("");
$display("\"");
end
end
default begin
reg_vector = 32'b00000000000000000000000000000000;
pad_out(32'hxxxxxxxx, model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
pad_out(reg_vector, model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
// ad_val = 32'b00000000000000000000000000000000;
if (!((msg_level<`debug_1))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" ");
$display("");
$write("CONFIG READ");
$display("");
$write("ADDRESS = ");
$write("%h",config_addr);
$write(" (NOT IMPLEMENTED)");
$display("");
$write("LATENCY TIMER = ");
$write("%h",reg_vector);
$display("");
$display("\"");
end
end
endcase
end // if
end
endtask // configure_read;
task configure_write;
begin
if ( wait_one_clk ) begin // wait one clock for write cycle
wait_one_clk = `false;
// if ( INP.pclk === 1'b1 ) begin
if ( (devsel_val !== 1'b0) ) begin
if ( (devsel_val !== 1'bz) ) begin
pdevselnn_out(1'bx, model_times.tpr_pclk_pdevselnn, -2 *`time_scale_multiplier);
end else begin
pdevselnn_out(1'bx, model_times.tpr_pclk_pdevselnn, 0 *`time_scale_multiplier);
end // if
pdevselnn_out(1'b0, model_times.tpr_pclk_pdevselnn, 0 *`time_scale_multiplier);
devsel_val = 1'b0;
end // if
if ( (trdy_val !== 1'b0) ) begin
if ( (trdy_val!== 1'bz) ) begin
ptrdynn_out(1'bx, model_times.tpr_pclk_ptrdynn,-2 *`time_scale_multiplier);
end else begin
ptrdynn_out(1'bx, model_times.tpr_pclk_ptrdynn, 0 *`time_scale_multiplier);
end // if
ptrdynn_out(1'b0, model_times.tpr_pclk_ptrdynn, 0 *`time_scale_multiplier);
trdy_val = 1'b0;
end // if
// end // if
end else begin
config_cycle = `false;
// first_a = `false; // added on 10/95 by Yu
// if ( INP.pclk === 1'b1 ) begin
// if ( (devsel_val !== 1'bz) ) begin
// pdevselnn_out(1'bz, model_times.tpr_pclk_pdevselnn, 0 *`time_scale_multiplier);
// devsel_val = 1'bz;
// end // if
// if ( (trdy_val !== 1'bz) ) begin
// ptrdynn_out(1'bz, model_times.tpr_pclk_ptrdynn, 0 *`time_scale_multiplier);
// trdy_val = 1'bz;
// end // if
// end // if
case ( config_addr )
8'b00000100 : begin
if ( (INP.pcxbenn[0] === 1'b0) ) begin
if ( INP.pad[6] === 1'b1 ) begin
command_reg[6] = 1'b1; // set parity error response bit
end else if ( INP.pad[6] === 1'b0 ) begin
command_reg[6] = 1'b0; // reset parity error response bit
end // if
end // if
if ( (INP.pcxbenn[3] === 1'b0) ) begin
if ( INP.pad[24] === 1'b1 ) begin
status_reg[8] = 1'b0; // reset data parity detected bit
end // if
if ( INP.pad[28] === 1'b1 ) begin
status_reg[12] = 1'b0; // reset received target abort bit
end // if
if ( INP.pad[29] === 1'b1 ) begin
status_reg[13] = 1'b0; // reset received master abort bit
end // if
if ( INP.pad[31] === 1'b1 ) begin
status_reg[15] = 1'b0; // reset detected parity error bit
end // if
end // if
if (!((msg_level<`debug_1))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" ");
$display("");
$write("CONFIG WRITE");
$display("");
$write("ADDRESS = ");
$write("%h",config_addr);
$write(" (STATUS | COMMAND)");
$display("");
$write("STATUS = ");
$write("%h",(status_reg));
$display("");
$write("COMMAND = ");
$write("%h",(command_reg));
$display("");
$display("\"");
end
end
8'b00001100 : begin
if ( (INP.pcxbenn[1] === 1'b0) ) begin
latency_timer_reg = INP.pad[15 : 8]; // set latency_timer bit
timeout_limit = (INP.pad[15 : 8]); // set timeout_limit
if (!((msg_level<`debug_1))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" ");
$display("");
$write("CONFIG WRITE");
$display("");
$write("ADDRESS = ");
$write("%h",config_addr);
$write(" (LATENCY TIMER)");
$display("");
$write("LATENCY TIMER = ");
$write("%h",(latency_timer_reg));
$display("");
$display("\"");
end
end // if
if ( (INP.pcxbenn[0] === 1'b0) ) begin
cacheline_size_reg = INP.pad[7 : 0]; // set cacheline size register 12/13/94 (rev 2.1)
// cacheline_size_int = (INP.pad[7 : 0]);
if (!((msg_level<`debug_1))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" ");
$display("");
$write("CONFIG WRITE");
$display("");
$write("ADDRESS = ");
$write("%h",config_addr);
$write(" (CACHELINE SIZE)");
$display("");
$write("CACHELINE SIZE = ");
$write("%h",(cacheline_size_reg));
$display("");
$display("\"");
end
end // if
end
default begin
if (!((msg_level<`debug_1))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" ");
$display("");
$write("CONFIG WRITE");
$display("");
$write("ADDRESS = ");
$write("%h",config_addr);
$write("(NOT IMPLEMENTED)");
$display("");
$write("DATA = ");
$write("%h",(INP.pad));
$display("");
$display("\"");
end
end
endcase
end // if
end
endtask // configure_write;
task config;
begin
if ( (INP.pperrnn === 1'b0) && (command_reg[6] === 1'b1) && !(last_bstate === sidle) ) begin
status_reg[8] = 1'b1; // set data parity detected bit
end // if
if ( (target_abort === 1'b1) ) begin
status_reg[12] = 1'b1; // set received target abort bit
end // if
if ( (master_abort === 1'b1) && !(cmmd === 4'b0001) ) begin
status_reg[13] = 1'b1; // set received master abort bit
end // if
if ( (INP.pperrnn === 1'b0) ) begin
status_reg[15] = 1'b1; // set detected parity error bit
end // if
// StarID #343 address_phase true only on neg edge of pframenn
if ( (INP.pframenn === 1'b0) && (pframenn_last === 1'b1) ) begin
address_phase = `true;
end // if
pframenn_last = INP.pframenn;
if ( (INP.pframenn === 1'b0) && (INP.pidsel === 1'b1) && ((INP.pcxbenn === 4'b1010) || (INP.pcxbenn === 4'b1011))
&& (bstate === sidle) && address_phase &&
((INP.pad[1 :0] === 2'b00) ||
(INP.pad[1 :0] === 2'b01 && type1_access_l))) begin
config_perr_check = `true; // to check perr on the next clock
config_cycle = `true;
// first_a = `true;
config_addr = (INP.pad[7 : 0]);
wait_one_clk = `true;
if ( (INP.pcxbenn === 4'b1010) ) begin
commd = read;
end else if ( (INP.pcxbenn === 4'b1011) ) begin
commd = write;
end // if
end // if
if ( address_phase ) begin
address_phase = `false;
end // if
if ( config_cycle && (commd === write) ) begin
configure_write;
if (!config_cycle) begin
first_a = `true; // tristate s/t/s pins
end
end
if (first_a) begin
config_par_check = `false;
config_perr_check = `false;
if ( tri_pins) begin
if (INP.pirdynn === 1'b0) begin
pdevselnn_out(1'bx, model_times.tpr_pclk_pdevselnn, -2 *`time_scale_multiplier);
pdevselnn_out(1'b1, model_times.tpr_pclk_pdevselnn, 0 *`time_scale_multiplier);
ptrdynn_out(1'bx, model_times.tpr_pclk_ptrdynn, -2 *`time_scale_multiplier);
ptrdynn_out(1'b1, model_times.tpr_pclk_ptrdynn, 0 *`time_scale_multiplier);
tri_pins = `false;
if (commd === read) begin
pad_out(32'hxxxxxxxx, model_times.tpr_pclk_pad, -2 *`time_scale_multiplier);
pad_out(32'hzzzzzzzz, model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
end
end
end else begin
tri_pins = `true;
first_a = `false;
pdevselnn_out(1'bz, model_times.tpr_pclk_pdevselnn, 0 *`time_scale_multiplier);
devsel_val = 1'bz;
ptrdynn_out(1'bz, model_times.tpr_pclk_ptrdynn, 0 *`time_scale_multiplier);
trdy_val = 1'bz;
end // if
end // if
if ( config_cycle && (commd === read) ) begin
configure_read;
if (!config_cycle) begin
first_a = `true; // tristate s/t/s pins on next clock edge
end
end
end
endtask // config;
task bus_machine;
begin: task_bus_machine
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \"bus_machine");
$display("\"");
end
last_bstate = bstate;
case ( bstate )
sidle : begin
if ( (b(request) && ! b(step_local)) && ! b(INP.pgntnn) && b(INP.pframenn) &&
b(INP.pirdynn) ) begin
bstate = saddr;
end else if ( ((b(request) && b(step_local)) || ! b(request)) && ! b(INP.pgntnn) &&
b(INP.pframenn) && b(INP.pirdynn) ) begin
bstate = sdr_bus;
end else begin
bstate = sidle;
end // if
end
saddr : begin
first_64out = `true; // to control pd and pbe output when 64-bit default to 32-bit (pack64nn /= '0')
if ( addr_64 && !(second_addr) ) begin
second_addr = `true;
end else begin
bstate = sm_data;
second_addr = `false;
end // if
end
sm_data : begin
if ( cstate_rw && (INP.ptrdynn === 1'b0) ) begin
first_64out = `false; // to control pd and pbe output when 64 bit default to 32 bit (pack64nn /= '0')
end // if
if ( ! b(INP.pframenn) ||
(b(INP.pframenn) && b(INP.ptrdynn) && b(INP.pstopnn) && ! b(dev_to)) ) begin
bstate = sm_data;
end else if ( (b(request) && ! b(step_local)) && ! b(INP.pgntnn) && b(INP.pframenn) &&
! b(INP.ptrdynn) && b(l_cycle) &&
(b(back_to_back) && (b(sa) || b(fb2b_ena))) ) begin
bstate = saddr;
end else if ( (b(INP.pframenn) && ! b(INP.pstopnn)) || (b(INP.pframenn) && b(dev_to)) ) begin
bstate = ss_tar;
end else begin
bstate = sturn_ar;
end // if
end
sturn_ar : begin
if ( b(request) && ! b(step_local) && ! b(INP.pgntnn) ) begin
bstate = saddr;
end else if ( ((b(request) && b(step_local)) || ! b(request)) && ! b(INP.pgntnn) ) begin
bstate = sdr_bus;
end else if ( b(INP.pgntnn) ) begin
bstate = sidle;
end else begin
if (!((`false))) begin
$display("ERROR at %0t from %m",$time);
$write(" \"pci_master: no path out of turn_ar state");
$display("\"");
end
end // if
end
ss_tar : begin
if ( ! b(INP.pgntnn) ) begin
bstate = sdr_bus;
end else if ( b(INP.pgntnn) ) begin
bstate = sidle;
end // if
end
sdr_bus : begin
if ( ((b(request) && b(step_local)) || ! b(request)) && ! b(INP.pgntnn) ) begin
bstate = sdr_bus;
end else if ( b(request) && ! b(step_local) && ! b(INP.pgntnn) ) begin
bstate = saddr;
end else if ( b(INP.pgntnn) ) begin
bstate = sidle;
end else begin
if (!((`false))) begin
$display("ERROR at %0t from %m",$time);
$write(" \"pci_master: no path out of dr_bus state");
$display("\"");
end
end // if
end
endcase
end
endtask // bus_machine;
task irdy_oe_maker;
begin
case ( bstate )
sm_data , saddr : begin
irdy_oe = 1'b1;
end
default begin
irdy_oe = 1'b0;
end
endcase
end
endtask // irdy_oe_maker;
task irdy_maker;
begin
if ( irdy_oe === 1'b1 ) begin
if ( (irdy_val !== irdy_int) ) begin
if ( (irdy_val !== 1'bz) ) begin
pirdynn_out(1'bx, model_times.tpr_pclk_pirdynn, - 2 *`time_scale_multiplier);
end else begin
pirdynn_out(1'bx, model_times.tpr_pclk_pirdynn, 0 *`time_scale_multiplier);
end // if
pirdynn_out(irdy_int, model_times.tpr_pclk_pirdynn, 0 *`time_scale_multiplier);
irdy_val = irdy_int;
end // if
end else begin
if ( (irdy_val !== 1'bz) ) begin
pirdynn_out(1'bz, model_times.tpr_pclk_pirdynn, 0 *`time_scale_multiplier);
irdy_val = 1'bz;
end // if
end // if
end
endtask // irdy_maker;
task irdy_int_maker;
begin
if ( bstate === sm_data && (b(ready) || b(dev_to)) ) begin
irdy_int = 1'b0;
end else begin
irdy_int = 1'b1;
end // if
end
endtask // irdy_int_maker;
task req_maker;
begin
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \"req_maker");
$display("\"");
end
if ( !(old_reset_model) ) begin
if ( ((b(request) && ! b(lock_a)) || (b(request) && b(lock_a) && lstate===free))
&& ! (bstate===ss_tar) && ! (last_bstate === ss_tar) && (enable === 1'b1) ) begin
if ( (req_val !== 1'b0) ) begin
preqnn_out(1'bx, model_times.tpr_pclk_preqnn, 0 *`time_scale_multiplier);
preqnn_out(1'b0, model_times.tpr_pclk_preqnn, 0 *`time_scale_multiplier);
req_val = 1'b0;
end // if
end else begin
if ( (req_val !== 1'b1) ) begin
preqnn_out(1'bx, model_times.tpr_pclk_preqnn, 0 *`time_scale_multiplier);
preqnn_out(1'b1, model_times.tpr_pclk_preqnn, 0 *`time_scale_multiplier);
req_val = 1'b1;
end // if
end // if
end // if
old_reset_model = reset_model;
end
endtask // req_maker;
task frame_maker;
begin
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \"frame_maker");
$display("\"");
end
case ( bstate )
saddr , sm_data : begin
if ( (frame_val !== frame_int) ) begin
if ( (frame_val !== 1'bz) ) begin
pframenn_out(1'bx, model_times.tpr_pclk_pframenn, -2 *`time_scale_multiplier);
end else begin
pframenn_out(1'bx, model_times.tpr_pclk_pframenn, 0 *`time_scale_multiplier);
end // if
pframenn_out(frame_int, model_times.tpr_pclk_pframenn,0 *`time_scale_multiplier);
frame_val = frame_int;
if ( (bus_64) && !(retry64_32) ) begin // preq64nn follows frame_int for 64-bit extention
if ( (req64_val !== frame_int) ) begin
if ( (req64_val !== 1'bz) ) begin
preq64nn_out(1'bx, model_times.tpr_pclk_preq64nn, -2 *`time_scale_multiplier);
end else begin
preq64nn_out(1'bx, model_times.tpr_pclk_preq64nn, 0 *`time_scale_multiplier);
end // if
preq64nn_out(frame_int, model_times.tpr_pclk_preq64nn, 0 *`time_scale_multiplier);
req64_val = frame_int;
end // if
end // if
end // if
end
default begin
if ( (frame_val !== 1'bz) ) begin
pframenn_out(1'bz, model_times.tpr_pclk_pframenn,0 *`time_scale_multiplier);
frame_val = 1'bz;
end // if
if ( (req64_val !== 1'bz) ) begin
preq64nn_out(1'bz, model_times.tpr_pclk_preq64nn,0 *`time_scale_multiplier);
req64_val = 1'bz;
end // if
end
endcase
end
endtask // frame_maker;
task frame_int_maker;
begin
if ( (bstate === saddr) || ((bstate===sm_data) && ! b(dev_to) &&
((! b(comp) && ((! b(time_out)) || (! b(INP.pgntnn))) && b(INP.pstopnn)) ||
! b(ready))) ) begin
frame_int = 1'b0;
end else begin
frame_int = 1'b1;
end // if
end
endtask // frame_int_maker;
task latch_variables;
begin
latched_comp = comp;
latched_lock_a = lock_a;
latched_bstate = bstate;
end
endtask // latch_variables;
task lock_int_maker;
begin
INP.pstopnn = INP.pstopnn;
if ( (b(own_lock) && (bstate===saddr)) || (b(own_lock) && ! b(latched_lock_a) &&
b(latched_comp) && (latched_bstate===sm_data) && b(INP.pframenn) && !
b(INP.ptrdynn)) || b(target_abort) || b(master_abort) || (latched_bstate===sm_data
&& ! b(INP.pstopnn) && b(INP.ptrdynn) && ! b(lock_data_transferred)) ) begin
if ( (second_addr) ) begin
lock_int = 1'b0;
end else begin
lock_int = 1'b1;
end // if
end else begin
lock_int = 1'b0;
end // if
end
endtask // lock_int_maker;
task own_lock_maker;
begin
if ( (b(INP.plocknn) && b(INP.pframenn) && b(INP.pirdynn) && ! b(INP.preqnn)
&& ! b(INP.pgntnn) && b(lock_a)) ||
(b(own_lock) && (! b(INP.pframenn) || ! b(INP.plocknn))) ) begin
own_lock = 1'b1;
end else begin
own_lock = 1'b0;
end // if
end
endtask // own_lock_maker;
task lock_state;
begin
case ( lstate )
free : begin
if ( b(INP.plocknn) || (! b(INP.plocknn) && b(own_lock)) ) begin
lstate = free;
end else if ( ! b(INP.plocknn) && ! b(own_lock) ) begin
lstate = busy;
end // if
end
busy : begin
if ( b(INP.plocknn) && b(INP.pframenn) ) begin
lstate = free;
end else if ( ! b(INP.plocknn) || ! b(INP.pframenn) ) begin
lstate = busy;
end // if
end
endcase
end
endtask // lock_state;
task lock_maker;
begin
if ( lock_en === 1'b1 ) begin
if ( (lock_val !== lock_int) ) begin
if ( (lock_val !== 1'bz) ) begin
plocknn_out(1'bx, model_times.tpr_pclk_plocknn,-2 *`time_scale_multiplier);
end else begin
plocknn_out(1'bx, model_times.tpr_pclk_plocknn, 0 *`time_scale_multiplier);
end // if
plocknn_out(lock_int, model_times.tpr_pclk_plocknn, 0 *`time_scale_multiplier);
lock_val = lock_int;
end // if
end else begin
if ( (lock_val !== 1'bz) ) begin
plocknn_out(1'bz, model_times.tpr_pclk_plocknn, 0 *`time_scale_multiplier);
lock_val = 1'bz;
end // if
end // if
end
endtask // lock_maker;
task lock_en_maker;
begin
if ( reset_model ) begin
lock_en = 1'b0;
end else begin
if ( (b(own_lock) && (bstate===sm_data || second_addr)) ||
(b(lock_en) && ( ! b(INP.pframenn) || ! b(INP.plocknn))) ) begin
lock_en = 1'b1;
end else begin
lock_en = 1'b0;
end // if
end // if
end
endtask // lock_en_maker;
// generate a signal that keeps track of whether any data transfer
// have happened during a locked sequence. this is needed so that
// the lock# line can be deasserted if a locked access is retried
// before any data is transferred.
task lock_data;
begin
case ( lock_data_transferred )
1'b0 : begin
if ( bstate === sm_data && ! b(INP.ptrdynn) && ! b(INP.pirdynn) && b(own_lock) ) begin
lock_data_transferred = 1'b1;
end // if
end
1'b1 : begin
if ( (b(own_lock) && ! b(lock_a) && b(comp) && bstate===sm_data &&
b(INP.pframenn) && ! b(INP.ptrdynn)) ) begin
lock_data_transferred = 1'b0;
end // if
end
default begin // added for lock_data_transfered changed from bit to std_logic
lock_data_transferred = 1'b0;
end
endcase
end
endtask // lock_data;
// generate the to signal. basically this little machine
// counts whenever the bus machine is in m_data and resets itself
// whenever it is not.
task to_maker;
begin
case ( bstate )
sm_data : begin
if ( cmmd !== 4'b1111 ) begin // mem_write_inv cycle not effected by to_limit
to_counter = to_counter + 1;
end // if
if ( to_counter > timeout_limit && INP.ptrdynn === 1'b0 ) begin // trdy must be asserted
time_out = 1'b1;
end // if
end
default begin
to_counter = 0;
time_out = 1'b0;
end
endcase
end
endtask // to_maker;
// this signal goes to the backend and tells when the bus
// interface is doing address stepping.
task stepping_maker;
begin
if ( bstate === sdr_bus && ! b(INP.preqnn) ) begin
stepping = 1'b1;
end else begin
stepping = 1'b0;
end // if
end
endtask // stepping_maker;
task parity_maker;
integer pcnt;
begin
if ( ((bstate === sm_data) && (cycle_command === write)) || (bstate === saddr) || config_par_check || (bstate === sdr_bus) ) begin
pcnt = 0;
for (i = 31; i >= 0; i = i - 1) begin
if ( INP.pad[i] === 1'b1 ) begin
pcnt = pcnt + 1;
end // if
end // loop
for (i = 3; i >= 0; i = i - 1) begin
if ( INP.pcxbenn[i] === 1'b1 ) begin
pcnt = pcnt + 1;
end // if
end // loop
if ( bstate === saddr ) begin
if ( bad_addr_parity ) begin
pcnt = pcnt + 1;
end // if
end else begin
if ( bad_data_parity ) begin
pcnt = pcnt + 1;
end // if
end // if
if ( lmcver.rem(pcnt,2) === 1 ) begin
if ( (par_val !== 1'b1) ) begin
ppar_out(1'bx, model_times.tpr_pclk_ppar, 0 *`time_scale_multiplier);
ppar_out(1'b1, model_times.tpr_pclk_ppar, 0 *`time_scale_multiplier);
par_val = 1'b1;
end // if
end else begin
if ( (par_val !== 1'b0) ) begin
ppar_out(1'bx, model_times.tpr_pclk_ppar, 0 *`time_scale_multiplier);
ppar_out(1'b0, model_times.tpr_pclk_ppar, 0 *`time_scale_multiplier);
par_val = 1'b0;
end // if
end // if
end else begin
if ( (par_val !== 1'bz) ) begin
ppar_out(1'bz, model_times.tpr_pclk_ppar, 0 *`time_scale_multiplier);
par_val = 1'bz;
end // if
end // if
end
endtask // parity_maker;
task parity64_maker;
integer pcnt;
begin
if ( ((bstate === saddr) && addr_64 && (INP.preq64nn === 1'b0)) ||
((bstate === sm_data) && (cycle_command === write) && bus_64 && (INP.pdevselnn === 1'b0) && (INP.pack64nn === 1'b0)) ) begin
pcnt = 0;
for (i = 63; i >= 32; i = i - 1) begin
if ( INP.pd[i] === 1'b1 ) begin
pcnt = pcnt + 1;
end // if
end // loop
for (i = 7; i >= 4; i = i - 1) begin
if ( (INP.pbenn[i] === 1'b1) ) begin
pcnt = pcnt + 1;
end // if
end // loop
if ( bstate === saddr ) begin
if ( bad_addr_parity ) begin
pcnt = pcnt + 1;
end // if
end else begin
if ( bad_data_parity ) begin
pcnt = pcnt + 1;
end // if
end // if
if ( lmcver.rem(pcnt,2) === 1 ) begin
if ( (par64_val !== 1'b1) ) begin
ppar64_out(1'bx, model_times.tpr_pclk_ppar64, 0 *`time_scale_multiplier);
ppar64_out(1'b1, model_times.tpr_pclk_ppar64, 0 *`time_scale_multiplier);
par64_val = 1'b1;
end // if
end else begin
if ( (par64_val !== 1'b0) ) begin
ppar64_out(1'bx, model_times.tpr_pclk_ppar64, 0 *`time_scale_multiplier);
ppar64_out(1'b0, model_times.tpr_pclk_ppar64, 0 *`time_scale_multiplier);
par64_val = 1'b0;
end // if
end // if
end else begin
if ( (par64_val !== 1'bz) ) begin
ppar64_out(1'bz, model_times.tpr_pclk_ppar64, 0 *`time_scale_multiplier);
par64_val = 1'bz;
end // if
end // if
end
endtask // parity64_maker;
task parity_checker;
integer pcnt;
integer pcnt64;
begin
if ( (command_reg[6] === 1'b1) &&
(((last_bstate === sm_data) && !(last_irdy) && !(last_trdy) && (last_cycle_command === read)) || config_perr_check) ) begin
pcnt = 0;
for (i = 31; i >= 0; i = i - 1) begin
if ( last_ad[i] === 1'b1 ) begin
pcnt = pcnt + 1;
end // if
end // loop
for (i = 3; i >= 0; i = i - 1) begin
if ( last_cbe[i] === 1'b1 ) begin
pcnt = pcnt + 1;
end // if
end // loop
if ( ppar === 1'b1 ) begin // do not use inp.ppar, otherwise 'H' is filtered to '1'
pcnt = pcnt + 1;
end // if
if ( ((last_bstate === sm_data) && !(last_irdy) && !(last_trdy) && (last_cycle_command === read) &&
last_bus_64 && (last_pack64nn === 1'b0)) ) begin
pcnt64 = 0;
for (i = 63; i >= 32; i = i - 1) begin
if ( INP.pd[i] === 1'b1 ) begin
pcnt64 = pcnt64 + 1;
end // if
end // loop
for (i = 7; i >= 4; i = i - 1) begin
if ( (INP.pbenn[i] === 1'b1) ) begin
pcnt64 = pcnt64 + 1;
end // if
end // loop
if ( ppar64 === 1'b1 ) begin // do not use inp.ppar64, otherwise 'H' is filtered to '1'
pcnt64 = pcnt64 + 1;
end // if
end // if
if ( (lmcver.rem(pcnt,2) === 1) || (lmcver.rem(pcnt64,2) === 1) ) begin
if ( (perr_val !== 1'b0) ) begin
if ( (perr_val !== 1'bz) ) begin
pperrnn_out(1'bx, model_times.tpr_pclk_pperrnn,-2 *`time_scale_multiplier);
end else begin
pperrnn_out(1'bx, model_times.tpr_pclk_pperrnn,0 *`time_scale_multiplier);
end // if
pperrnn_out(1'b0, model_times.tpr_pclk_pperrnn,0 *`time_scale_multiplier);
perr_val = 1'b0;
end // if
end else begin
if ( (perr_val !== 1'b1) ) begin
if ( (perr_val !== 1'bz) ) begin
pperrnn_out(1'bx, model_times.tpr_pclk_pperrnn,-2 *`time_scale_multiplier);
end else begin
pperrnn_out(1'bx, model_times.tpr_pclk_pperrnn,0 *`time_scale_multiplier);
end // if
pperrnn_out(1'b1, model_times.tpr_pclk_pperrnn,0 *`time_scale_multiplier);
perr_val = 1'b1;
end // if
end // if
end else begin
if ( (perr_val === 1'b0) ) begin
if ( (perr_val !== 1'bz) ) begin
pperrnn_out(1'bx, model_times.tpr_pclk_pperrnn,-2 *`time_scale_multiplier);
end else begin
pperrnn_out(1'bx, model_times.tpr_pclk_pperrnn,0 *`time_scale_multiplier);
end // if
pperrnn_out(1'b1, model_times.tpr_pclk_pperrnn,0 *`time_scale_multiplier);
perr_val = 1'b1;
end else if ( (perr_val !== 1'bz) ) begin
pperrnn_out(1'bz, model_times.tpr_pclk_pperrnn,0 *`time_scale_multiplier);
perr_val = 1'bz;
end // if
end // if
last_cycle_command = cycle_command;
last_bus_64 = bus_64;
last_pack64nn = INP.pack64nn;
last_trdy = b(INP.ptrdynn);
last_irdy = b(INP.pirdynn);
last_ad = (INP.pad);
last_cbe = (INP.pcxbenn);
end
endtask // parity_checker;
task dev_to_maker;
begin
if ( (INP.prstnn === 1'b0) ) begin // changed on 3/15/94 Yu
dtstate = idle;
dev_to = 1'b0;
end // if
case ( dtstate )
idle : begin
if ( last_bstate === saddr ) begin // laverty (bstate)
dtstate = counting;
if ( INP.pcxbenn === 4'b1101 ) begin
counter = 5;
end else begin
counter = 4;
end // if
end else begin
dtstate = idle;
end // if
end
counting : begin
if ( (INP.pdevselnn === 1'b0) || (INP.pdevselnn === 1'b0 /* 'L' */) ) begin
dtstate = idle;
end else begin
counter = counter - 1;
if ( counter === 0 ) begin
dev_to = 1'b1;
dtstate = timed_out;
end // if
end // if
end
timed_out : begin
if ( last_bstate === ss_tar ) begin // laverty (bstate)
dev_to = 1'b0;
dtstate = idle;
end else begin
dtstate = timed_out;
end // if
end
endcase
end
endtask // dev_to_maker;
task ad_maker;
reg [1 : 64*8] message ;
begin
case ( bstate )
saddr: begin
first_b = `true;
if ( addr_64 && !(second_addr) ) begin // dual address
if ( (d_val !== upper_addr) ) begin
if ( pd !== z_adbus ) begin
pd_out(32'hxxxxxxxx, model_times.tpr_pclk_pd, -2 *`time_scale_multiplier);
end else begin
pd_out(32'hxxxxxxxx, model_times.tpr_pclk_pd, 0 *`time_scale_multiplier);
end // if
pd_out(upper_addr, model_times.tpr_pclk_pd, 0 *`time_scale_multiplier);
d_val = upper_addr;
end // if
if ( (be_val !== (cmmd)) ) begin
if ( pbenn !== z_cxbe ) begin
pbenn_out(4'bxxxx, model_times.tpr_pclk_pbenn, -2 *`time_scale_multiplier);
end else begin
pbenn_out(4'bxxxx, model_times.tpr_pclk_pbenn, 0 *`time_scale_multiplier);
end // if
pbenn_out((cmmd), model_times.tpr_pclk_pbenn, 0 *`time_scale_multiplier);
This page: |
Created: | Thu Aug 19 11:57:11 1999 |
| From: |
../../../sparc_v8/system/lmc/rtl/pcimaster_fm.v
|