be_val = (cmmd);
end // if
if ( (ad_val !== (addr)) ) begin
if ( pad !== z_adbus ) begin
pad_out(32'hxxxxxxxx, model_times.tpr_pclk_pad, -2 *`time_scale_multiplier);
end else begin
pad_out(32'hxxxxxxxx, model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
end // if
pad_out((addr), model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
ad_val = (addr);
end // if
if ( (cxbe_val !== 4'b1101) ) begin
if ( pcxbenn !== z_cxbe ) begin
pcxbenn_out( 4'bxxxx, model_times.tpr_pclk_pcxbenn, -2 *`time_scale_multiplier);
end else begin
pcxbenn_out( 4'bxxxx, model_times.tpr_pclk_pcxbenn, 0 *`time_scale_multiplier);
end // if
pcxbenn_out( 4'b1101, model_times.tpr_pclk_pcxbenn, 0 *`time_scale_multiplier);
cxbe_val = 4'b1101;
end // if
end else begin
if ( addr_64 ) begin
if ( (ad_val !== upper_addr) ) begin
if ( pad !== z_adbus ) begin
pad_out(32'hxxxxxxxx, model_times.tpr_pclk_pad, -2 *`time_scale_multiplier);
end else begin
pad_out(32'hxxxxxxxx, model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
end // if
pad_out(upper_addr, model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
ad_val = upper_addr;
end // if
if ( (cxbe_val !== (cmmd)) ) begin
if ( pcxbenn !== z_cxbe ) begin
pcxbenn_out( 4'bxxxx, model_times.tpr_pclk_pcxbenn, -2 *`time_scale_multiplier);
end else begin
pcxbenn_out( 4'bxxxx, model_times.tpr_pclk_pcxbenn, 0 *`time_scale_multiplier);
end // if
pcxbenn_out((cmmd), model_times.tpr_pclk_pcxbenn, 0 *`time_scale_multiplier);
cxbe_val = (cmmd);
end // if
end else begin
if ( (ad_val !== (addr)) ) begin
if ( pad !== z_adbus ) begin
pad_out(32'hxxxxxxxx, model_times.tpr_pclk_pad, -2 *`time_scale_multiplier);
end else begin
pad_out(32'hxxxxxxxx, model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
end // if
pad_out((addr), model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
ad_val = (addr);
end // if
if ( (cxbe_val !== (cmmd)) ) begin
if ( pcxbenn !== z_cxbe ) begin
pcxbenn_out( 4'bxxxx, model_times.tpr_pclk_pcxbenn, -2 *`time_scale_multiplier);
end else begin
pcxbenn_out( 4'bxxxx, model_times.tpr_pclk_pcxbenn, 0 *`time_scale_multiplier);
end // if
pcxbenn_out((cmmd), model_times.tpr_pclk_pcxbenn, 0 *`time_scale_multiplier);
cxbe_val = (cmmd);
end // if
end // if
if ( !(second_addr) ) begin
if ( (d_val !== z_adbus) ) begin
pd_out(32'hzzzzzzzz, model_times.tpr_pclk_pd, 0 *`time_scale_multiplier);
d_val = z_adbus;
end // if
if ( (be_val !== 4'bzzzz) ) begin
pbenn_out(4'bzzzz, model_times.tpr_pclk_pbenn, 0 *`time_scale_multiplier);
be_val = 4'bzzzz;
end // if
end // if
end // if
end
sm_data: begin
first_b = `true;
if ( cycle_command === write ) begin
if ( (ad_val !== (data_int)) ) begin
if ( pad !== z_adbus ) begin
pad_out(32'hxxxxxxxx, model_times.tpr_pclk_pad, -2 *`time_scale_multiplier);
end else begin
pad_out(32'hxxxxxxxx, model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
end // if
pad_out((data_int), model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
ad_val = (data_int);
end // if
if ( bus_64 && !(retry64_32) && (first_64out || ((INP.pdevselnn === 1'b0) && (INP.pack64nn === 1'b0))) ) begin
if ( (d_val !== (data_int_63to32)) ) begin
if ( pd !== z_adbus ) begin
pd_out(32'hxxxxxxxx, model_times.tpr_pclk_pd, -2 *`time_scale_multiplier);
end else begin
pd_out(32'hxxxxxxxx, model_times.tpr_pclk_pd, 0 *`time_scale_multiplier);
end // if
pd_out((data_int_63to32), model_times.tpr_pclk_pd, 0 *`time_scale_multiplier);
d_val = (data_int_63to32);
end // if
end // if
if ( bus_64 && !(first_64out) && (INP.pdevselnn === 1'b0) && (INP.pack64nn === 1'b1) ) begin
if ( (d_val !== z_adbus) ) begin
pd_out(32'hzzzzzzzz, model_times.tpr_pclk_pd, 0 *`time_scale_multiplier);
d_val = z_adbus;
end // if
end // if
if ( !(bus_64) ) begin
if ( (d_val !== z_adbus) ) begin
pd_out(32'hzzzzzzzz, model_times.tpr_pclk_pd, 0 *`time_scale_multiplier);
d_val = z_adbus;
end // if
end // if
end else begin
if ( (ad_val !== z_adbus) ) begin
pad_out(32'hzzzzzzzz, model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
ad_val = z_adbus;
end // if
if ( (d_val !== z_adbus) ) begin
pd_out(32'hzzzzzzzz, model_times.tpr_pclk_pd, 0 *`time_scale_multiplier);
d_val = z_adbus;
end // if
end // if
if ( (cxbe_val !== (byte_en)) ) begin
if ( pcxbenn !== z_cxbe ) begin
pcxbenn_out( 4'bxxxx, model_times.tpr_pclk_pcxbenn, -2 *`time_scale_multiplier);
end else begin
pcxbenn_out( 4'bxxxx, model_times.tpr_pclk_pcxbenn, 0 *`time_scale_multiplier);
end // if
pcxbenn_out((byte_en), model_times.tpr_pclk_pcxbenn, 0 *`time_scale_multiplier);
cxbe_val = (byte_en);
end // if
if ( bus_64 && !(retry64_32) && (first_64out || ((INP.pdevselnn === 1'b0) && (INP.pack64nn === 1'b0))) ) begin
if ( (be_val !== (byte_en_7to4)) ) begin
if ( pbenn !== z_adbus ) begin
pbenn_out(4'bxxxx, model_times.tpr_pclk_pbenn, -2 *`time_scale_multiplier);
end else begin
pbenn_out(4'bxxxx, model_times.tpr_pclk_pbenn, 0 *`time_scale_multiplier);
end // if
pbenn_out((byte_en_7to4), model_times.tpr_pclk_pbenn, 0 *`time_scale_multiplier);
be_val = (byte_en_7to4);
end // if
end // if
if ( bus_64 && !(first_64out) && (INP.pdevselnn === 1'b0) && (INP.pack64nn === 1'b1) ) begin
if ( (be_val !== 4'bzzzz) ) begin
pbenn_out(4'bzzzz, model_times.tpr_pclk_pbenn, 0 *`time_scale_multiplier);
be_val = 4'bzzzz;
end // if
end // if
if ( !(bus_64) ) begin
if ( (be_val !== 4'bzzzz) ) begin
pbenn_out(4'bzzzz, model_times.tpr_pclk_pbenn, 0 *`time_scale_multiplier);
be_val = 4'bzzzz;
end // if
end // if
end
sdr_bus: begin
first_b = `true;
if ( (step_local || stepping) && ! b(INP.preqnn) ) begin
if ( (ad_val !== 32'hffffffff) ) begin
if ( pad !== z_adbus ) begin
pad_out(32'hxxxxxxxx, model_times.tpr_pclk_pad, -2 *`time_scale_multiplier);
end else begin
pad_out(32'hxxxxxxxx, model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
end // if
pad_out(32'hffffffff, model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
ad_val = 32'hffffffff;
end // if
if ( (cxbe_val !== (cmmd)) ) begin
if ( pcxbenn !== z_cxbe ) begin
pcxbenn_out( 4'bxxxx, model_times.tpr_pclk_pcxbenn, -2 *`time_scale_multiplier);
end else begin
pcxbenn_out( 4'bxxxx, model_times.tpr_pclk_pcxbenn, 0 *`time_scale_multiplier);
end // if
pcxbenn_out((cmmd), model_times.tpr_pclk_pcxbenn, 0 *`time_scale_multiplier);
cxbe_val = (cmmd);
end // if
end else begin
if ( (ad_val !== (32'ha5a5a5a5)) ) begin
if ( pad !== z_adbus ) begin
pad_out(32'hxxxxxxxx, model_times.tpr_pclk_pad, -2 *`time_scale_multiplier);
end else begin
pad_out(32'hxxxxxxxx, model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
end // if
pad_out((32'ha5a5a5a5), model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
ad_val = (32'ha5a5a5a5);
end // if
if ( (cxbe_val !== 4'b0101) ) begin
if ( pcxbenn !== z_cxbe ) begin
pcxbenn_out( 4'bxxxx, model_times.tpr_pclk_pcxbenn, -2 *`time_scale_multiplier);
end else begin
pcxbenn_out( 4'bxxxx, model_times.tpr_pclk_pcxbenn, 0 *`time_scale_multiplier);
end // if
pcxbenn_out(4'b0101, model_times.tpr_pclk_pcxbenn, 0 *`time_scale_multiplier);
cxbe_val = 4'b0101;
end // if
end // if
end
default begin
if ( first_b ) begin
first_b = `false;
if ( (ad_val !== z_adbus) ) begin
pad_out(32'hzzzzzzzz, model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
ad_val = z_adbus;
end // if
if ( (d_val !== z_adbus) ) begin
pd_out(32'hzzzzzzzz, model_times.tpr_pclk_pd, 0 *`time_scale_multiplier);
d_val = z_adbus;
end // if
if ( (cxbe_val !== 4'bzzzz) ) begin
pcxbenn_out(4'bzzzz, model_times.tpr_pclk_pcxbenn, 0 *`time_scale_multiplier);
cxbe_val = 4'bzzzz;
end // if
if ( (be_val !== 4'bzzzz) ) begin
pbenn_out(4'bzzzz, model_times.tpr_pclk_pbenn, 0 *`time_scale_multiplier);
be_val = 4'bzzzz;
end // if
end // if
end
endcase
end
endtask // ad_maker;
task command_maker;
begin
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \"command_maker");
$display("\"");
end
if ( bstate === saddr ) begin
if ( cmmd[0] === 1'b0 ) begin
cycle_command = read;
end else begin
cycle_command = write;
end // if
end // if
end
endtask // command_maker;
task update_timing_flags;
begin
// control setup and hold checks
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \"update_timing_flags");
$display("\"");
end
if ( bstate === saddr && INP.pframenn === 1'b0 ) begin
enabled = `true;
first = `true;
turn = `false;
end // if
if ( (enabled) ) begin
if ( (INP.pclk_event && INP.pclk === 1'b1) ) begin
if ( (first) ) begin
if ( (bstate === saddr) ) begin
if ( !(addr_64) ) begin // 64-bit address phase needs two clocks
first = `false;
end // if
read_cycle = `false;
write_cycle = `false;
if ( (cmmd[0] === 1'b0) ) begin // read cycle
read_cycle = `true;
write_cycle = `false;
turn = `true;
end else if ( (cmmd[0] === 1'b1) ) begin // write cycle
read_cycle = `false;
write_cycle = `true;
end // if
end // if
end else begin
if ( (read_cycle) ) begin
if ( (turn) ) begin
turn = `false;
CNTRL.r_pad_pclk <= #(0) `false;
CNTRL.r_ptrdynn_pclk <= #(0) `false;
CNTRL.r_pdevselnn_pclk <= #(0) `false;
CNTRL.r_pd_pclk <= #(0) `false;
end else begin
if ( (INP.pstopnn !== 1'b0) ) begin
CNTRL.r_pad_pclk <= #(0) `true;
CNTRL.r_ptrdynn_pclk <= #(0) `true;
CNTRL.r_pdevselnn_pclk <= #(0) `true;
if ( INP.pack64nn === 1'b0 ) begin
CNTRL.r_pd_pclk <= #(0) `true;
end // if
end else begin
CNTRL.r_pad_pclk <= #(0) `false;
CNTRL.r_ptrdynn_pclk <= #(0) `false;
CNTRL.r_pdevselnn_pclk <= #(0) `false;
CNTRL.r_pd_pclk <= #(0) `false;
end // if
end // if
end else if ( (write_cycle) ) begin
CNTRL.r_pad_pclk <= #(0) `false;
CNTRL.r_pd_pclk <= #(0) `false;
if ( (INP.pstopnn !== 1'b0) ) begin
CNTRL.r_ptrdynn_pclk <= #(0) `true;
CNTRL.r_pdevselnn_pclk <= #(0) `true;
end else begin
CNTRL.r_ptrdynn_pclk <= #(0) `false;
CNTRL.r_pdevselnn_pclk <= #(0) `false;
end // if
end // if
end // if
if ( (INP.pdevselnn !== 1'b0) && (INP.pframenn !== 1'b0) && (INP.pirdynn !== 1'b0) ) begin
enabled = `false;
CNTRL.r_pad_pclk <= #(0) `false;
CNTRL.r_pd_pclk <= #(0) `false;
CNTRL.r_ptrdynn_pclk <= #(0) `false;
CNTRL.r_pdevselnn_pclk <= #(0) `false;
CNTRL.r_pstopnn_pclk <= #(0) `false;
CNTRL.pdevselnn <= #(0) `false;
CNTRL.ptrdynn <= #(0) `false;
end // if
end // if
end // if
if ( (bstate === sidle) ) begin
CNTRL.pdevselnn <= #(0) `false;
CNTRL.ptrdynn <= #(0) `false;
CNTRL.r_ptrdynn_pclk <= #(0) `false;
CNTRL.r_pdevselnn_pclk <= #(0) `false;
end // if
if ( (back2back === 1'b1) ) begin
CNTRL.r_pstopnn_pclk <= #(0) `false;
CNTRL.ptrdynn <= #(0) `false;
CNTRL.pdevselnn <= #(0) `false;
CNTRL.r_ptrdynn_pclk <= #(0) `false;
CNTRL.r_pdevselnn_pclk <= #(0) `false;
end // if
if ( INP.prstnn === 1'b1 ) begin
CNTRL.r_pgntnn_pclk <= #(0) `true;
end else begin
CNTRL.r_pgntnn_pclk <= #(0) `false;
end // if
end
endtask // update_timing_flags;
task init_master;
begin
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \"init_master");
$display("\"");
end
CNTRL.pad <= #(0) `true;
CNTRL.pad_in <= #(0) `true;
CNTRL.r_pad_pclk <= #(0) `false;
CNTRL.pcxbenn <= #(0) `true;
CNTRL.pcxbenn_in <= #(0) `true;
CNTRL.r_pcxbenn_pclk <= #(0) `false;
CNTRL.ppar <= #(0) `true;
CNTRL.ppar_in <= #(0) `true;
CNTRL.r_ppar_pclk <= #(0) `false;
CNTRL.pframenn <= #(0) `true;
CNTRL.pframenn_in <= #(0) `true;
CNTRL.r_pframenn_pclk <= #(0) `false;
CNTRL.ptrdynn <= #(0) `false;
CNTRL.ptrdynn_in <= #(0) `true;
CNTRL.r_ptrdynn_pclk <= #(0) `false;
CNTRL.pirdynn <= #(0) `true;
CNTRL.pirdynn_in <= #(0) `true;
CNTRL.r_pirdynn_pclk <= #(0) `false;
CNTRL.pstopnn <= #(0) `true;
CNTRL.r_pstopnn_pclk <= #(0) `false;
CNTRL.pdevselnn <= #(0) `false;
CNTRL.pdevselnn_in <= #(0) `true;
CNTRL.r_pdevselnn_pclk <= #(0) `false;
CNTRL.pidsel <= #(0) `false;
CNTRL.r_pidsel_pclk <= #(0) `false;
CNTRL.preqnn <= #(0) `true;
CNTRL.preqnn_in <= #(0) `true;
CNTRL.r_preqnn_pclk <= #(0) `false;
CNTRL.pgntnn <= #(0) `true;
CNTRL.r_pgntnn_pclk <= #(0) `false;
CNTRL.pclk <= #(0) `true;
CNTRL.pclkrunnn <= #(0) `true;
CNTRL.ck_pclk <= #(0) `true;
CNTRL.prstnn <= #(0) `true;
CNTRL.ck_prstnn <= #(0) `true;
CNTRL.pd <= #(0) `false;
CNTRL.pd_in <= #(0) `false;
CNTRL.r_pd_pclk <= #(0) `false;
CNTRL.pbenn <= #(0) `false;
CNTRL.pbenn_in <= #(0) `false;
CNTRL.r_pbenn_pclk <= #(0) `false;
CNTRL.ppar64 <= #(0) `false;
CNTRL.ppar64_in <= #(0) `false;
CNTRL.r_ppar64_pclk <= #(0) `false;
CNTRL.preq64nn <= #(0) `false;
CNTRL.preq64nn_in <= #(0) `false;
CNTRL.r_preq64nn_pclk <= #(0) `false;
CNTRL.pack64nn <= #(0) `false;
CNTRL.r_pack64nn_pclk <= #(0) `false;
CNTRL.plocknn <= #(0) `false;
CNTRL.plocknn_in <= #(0) `false;
CNTRL.r_plocknn_pclk <= #(0) `false;
CNTRL.pperrnn <= #(0) `false;
CNTRL.pperrnn_in <= #(0) `false;
CNTRL.r_pperrnn_pclk <= #(0) `false;
CNTRL.pserrnn <= #(0) `false;
CNTRL.r_pserrnn_pclk <= #(0) `false;
CNTRL.psbonn <= #(0) `false;
CNTRL.r_psbonn_pclk <= #(0) `false;
CNTRL.psdone <= #(0) `false;
CNTRL.r_psdone_pclk <= #(0) `false;
if ( (version === "pci66") ) begin
status_reg[5] = 1'b1;
end else begin
status_reg[5] = 1'b0;
end // if
timeout_limit = to_limit;
latency_timer_reg = to_limit;
max_clk_period_l = max_clk_period;
x_transition_l = x_transition;
internal_retry_limit = retry_limit;
device_id_reg = device_id;
vendor_id_reg = vendor_id;
revision_id_reg = revision_id;
class_code_reg = class_code;
cacheline_size_reg = (cacheline_size);
if ( pclk === 1'b1 ) begin
pirdynn_out(1'bz, model_times.tpr_pclk_pirdynn, 0 *`time_scale_multiplier);
preqnn_out(1'bz, model_times.tpr_pclk_preqnn, 0 *`time_scale_multiplier);
preq64nn_out(1'bz, model_times.tpr_pclk_preq64nn, 0 *`time_scale_multiplier);
pframenn_out(1'bz, model_times.tpr_pclk_pframenn, 0 *`time_scale_multiplier);
plocknn_out(1'bz, model_times.tpr_pclk_plocknn, 0 *`time_scale_multiplier);
ppar_out(1'bz, model_times.tpr_pclk_ppar, 0 *`time_scale_multiplier);
ppar64_out(1'bz, model_times.tpr_pclk_ppar64, 0 *`time_scale_multiplier);
pperrnn_out(1'bz, model_times.tpr_pclk_pperrnn, 0 *`time_scale_multiplier);
pad_out(32'hzzzzzzzz, model_times.tpr_pclk_pad, 0 *`time_scale_multiplier);
pd_out(32'hzzzzzzzz, model_times.tpr_pclk_pd, 0 *`time_scale_multiplier);
pcxbenn_out(4'hz, model_times.tpr_pclk_pcxbenn, 0 *`time_scale_multiplier);
pbenn_out(4'hz, model_times.tpr_pclk_pbenn, 0 *`time_scale_multiplier);
pdevselnn_out(1'bz, model_times.tpr_pclk_pdevselnn, 0 *`time_scale_multiplier);
ptrdynn_out(1'bz, model_times.tpr_pclk_ptrdynn, 0 *`time_scale_multiplier);
end // if
end
endtask // init_master;
task update_internal;
begin
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \"update_internal");
$display("\"");
end
// this signal goes to masterbe process and says that the bus interface
// has accepted the request and owns the pci bus.
if ( bstate === saddr ) begin
cmd_ack = 1'b1;
end else begin
cmd_ack = 1'b0;
end // if
// this signal goes to masterbe process and bstate = m_data
if ( bstate === sm_data ) begin
data_phase = 1'b1;
end else begin
data_phase = 1'b0;
end // if
// generate the target_abort signal
if ( ! b(INP.pstopnn) && b(INP.pdevselnn) && bstate===sm_data &&
b(INP.pframenn) && ! b(INP.pirdynn) ) begin
target_abort = 1'b1;
end else begin
target_abort = 1'b0;
end // if
// generate the master_abort signal
if ( bstate===sm_data && b(dev_to) ) begin
master_abort = 1'b1;
end else begin
master_abort = 1'b0;
end // if
// internal signals used for communication between the backend
// and the bus interface. most of these are described in the
// state machine section of the pci spec.
l_cycle = was_wr;
sa = same_agnt;
lock_a = lock;
data_int = dataout;
data_int_63to32 = dataout_63to32;
comp = last_data;
// the request signal gets asserted whenever the backend wants the bus
// interface to request the bus. three things make this happen. first
// when a command has been read from the file then cmmd_ready is used to
// start the command. if the master leaves data phase and the
// proper number of bytes haven't been transferred then it is also
// asserted. the last case takes care of back to back accesses to the
// same agent.
if ( (cmmd_ready===1'b1) || ((cmd_in_progress===1'b1) && (data_phase===1'b0)) ||
((back_to_back === 1'b1) && (next_cmd[incode1:incode2] !== `idle_cmd))) begin
request = 1'b1;
end else begin
request = 1'b0;
end // if
end
endtask // update_internal;
task reset_master;
begin
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \"reset_master");
$display("\"");
end
bstate = sidle; // Laverty 12/17/94
pirdynn_out(1'bz, model_times.tpd_prstnn_pirdynn, 0 *`time_scale_multiplier);
preqnn_out(1'bz, model_times.tpd_prstnn_preqnn, 0 *`time_scale_multiplier);
preq64nn_out(1'bz, model_times.tpd_prstnn_preqnn, 0 *`time_scale_multiplier);
req_val = 1'bz;
pframenn_out(1'bz, model_times.tpd_prstnn_pframenn, 0 *`time_scale_multiplier);
plocknn_out(1'bz, model_times.tpd_prstnn_plocknn, 0 *`time_scale_multiplier);
ppar_out(1'bz, model_times.tpd_prstnn_ppar, 0 *`time_scale_multiplier);
ppar64_out(1'bz, model_times.tpd_prstnn_ppar64, 0 *`time_scale_multiplier);
pperrnn_out(1'bz, model_times.tpd_prstnn_pperrnn, 0 *`time_scale_multiplier);
pad_out(32'hzzzzzzzz, model_times.tpd_prstnn_pad, 0 *`time_scale_multiplier);
pd_out(32'hzzzzzzzz, model_times.tpd_prstnn_pd, 0 *`time_scale_multiplier);
pcxbenn_out(4'hz, model_times.tpd_prstnn_pcxbenn, 0 *`time_scale_multiplier);
pbenn_out(4'hz, model_times.tpd_prstnn_pbenn, 0 *`time_scale_multiplier);
pdevselnn_out(1'bz, model_times.tpd_prstnn_pdevselnn, 0 *`time_scale_multiplier);
ptrdynn_out(1'bz, model_times.tpd_prstnn_ptrdynn, 0 *`time_scale_multiplier);
command_reg[6] = 1'b0;
fb2b_ena = command_reg[9];
end
endtask // reset_master;
task report_master;
begin
if (!((msg_level===`no_msg))) begin
$display("NOTE at %0t from %m",$time);
$write(" \"SYNOPSYS PCIMASTER MODEL 5.3");
$display("");
$display("");
$write(" Initialized Configuration");
$display("");
$write(" Device ID = ");
$write("%h",(device_id));
$display("");
$write(" Vendor ID = ");
$write("%h",(vendor_id));
$display("");
$write(" Status = ");
$write("%h",(status_reg));
$display("");
$write(" Command = ");
$write("%h",(command_reg));
$display("");
$write(" Class Code = ");
$write("%h",(class_code));
$display("");
$write(" Revision ID = ");
$write("%h",(revision_id));
$display("");
$write(" Latency Timer = ");
$write("%h",(latency_timer_reg));
$display("");
$write(" Cacheline_size = ");
$write("%h",(cacheline_size_reg));
$display("");
$display("\"");
end
end
endtask // report_master;
task trace_master;
reg [1 : 11*8] sstr ;
reg [1 : 6*8] lstr ;
reg [1 : 8*8] bstr ;
reg [1 : 15*8] cstr ;
reg [1 : 10*8] dstr ;
reg [1 : 5*8] dtstr ;
reg [1 : 5*8] rstr ;
reg [1 : 5*8] rdystr ;
begin
dtstr = "FALSE";
rstr = "FALSE";
rdystr = "FALSE";
case ( sstate )
counting : begin sstr = "COUNTING ";
end
waiting : begin sstr = "WAITING ";
end
deasserting : begin sstr = "DEASSERTING";
end
endcase
case ( lstate )
free : begin lstr = "FREE ";
end
busy : begin lstr = "BUSY ";
end
endcase
case ( bstate )
sidle : begin bstr = "SIDLE ";
end
saddr : begin bstr = "SADDR ";
end
sm_data : begin bstr = "SM_DATA ";
end
sturn_ar : begin bstr = "STURN_AR";
end
ss_tar : begin bstr = "SS_TAR ";
end
sdr_bus : begin bstr = "SDR_BUS ";
end
endcase
case ( cstate )
cmd_rdy : begin cstr = "CMD_RDY ";
end
data_rd : begin cstr = "DATA_RD ";
end
data_wr : begin cstr = "DATA_WR ";
end
ddelay : begin cstr = "DELAY ";
end
cmd_dly : begin cstr = "CMD_DLY ";
end
disabled : begin cstr = "DISABLED ";
end
endcase
case ( dtstate )
counting : begin dstr = "COUNTING ";
end
idle : begin dstr = "IDLE ";
end
timed_out : begin dstr = "TIMED_OUT ";
end
endcase
if ( b(request) ) begin
rstr = "TRUE ";
end // if
if ( b(ready) ) begin
rdystr = "TRUE ";
end // if
if ( b(dev_to) ) begin
dtstr = "TRUE ";
end // if
if (!((`false))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" ");
$display("");
$write(" BSTATE = ");
$write("%s",bstr);
$display("");
$write(" CSTATE = ");
$write("%s",cstr);
$display("");
$write(" LSTATE = ");
$write("%s",lstr);
$display("");
$write(" SSTATE = ");
$write("%s",sstr);
$display("");
$write(" DTSTATE = ");
$write("%s",dstr);
$display("");
$display("");
$write(" REQUEST = ");
$write("%s",rstr);
$display("");
$write(" READY = ");
$write("%s",rdystr);
$display("");
$write(" DEV_TO = ");
$write("%s",dtstr);
$display("");
$display("\"");
end
end
endtask // trace_master;
task gen_output;
begin
end
endtask // gen_output;
task cycle_stalled;
begin
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \"cycle_stalled");
$display("\"");
end
// to get rid of burst cycles
tc = 1;
get_addr = `true;
burst_cycle = `false;
ready = 1'b0;
if ( (command === write) ) begin
// if ( (transfer_cnt !== transfer_limit) ) begin // prevent to eat up the command following write command
if ( curr_cmd[incode1:incode2] === `write_cycle_cmd || curr_cmd[incode1:incode2] === `write_continue_cmd ) begin
delete_cmd_code = `write_continue_cmd;
get_nxt_cmd;
end // if
// end // if
end else if ( (command === read) ) begin
if (master_abort === 1'b0) begin
if ( (INP.pdevselnn === 1'b0) && (INP.pack64nn === 1'b0) ) begin
return_data_addrv(addr,x_64);
end else begin
return_data_addrv(addr,x_32);
end // if
end // if
if ( curr_cmd[incode1:incode2] === `read_cycle_cmd || curr_cmd[incode1:incode2] === `read_continue_cmd ) begin
delete_cmd_code = `read_continue_cmd;
get_nxt_cmd;
end // if
end // if
end
endtask // cycle_stalled;
// increment hexaddress. takes the top 30 bits and turns them
// into an integer, adds 1 and then converts back.
task increment_address;
integer address;
begin
case ( hexaddress[1 : 0] )
2'b00 , 2'b10 : begin // linear incrementing or cacheline wrap mode
if ( bus_64 && (INP.pdevselnn === 1'b0) && (INP.pack64nn === 1'b0) ) begin
address = (hexaddress[31 : 2]) + 2; // address increases by 8 for 64-bit data transfer
end else begin
address = (hexaddress[31 : 2]) + 1; // address increases by 4 for 32-bit data transfer
end // if
if ( hexaddress[1] === 1'b1 ) begin
if ( cacheline_size_reg !== 0 ) begin
if ( (address % cacheline_size_reg === 0) ) begin
address = address - cacheline_size_reg;
end // if
if ( (address === starting_addr) ) begin
address = address + cacheline_size_reg;
starting_addr = address;
end // if
end // if
end // if
hexaddress[31 : 2] = address;
end
default begin
end
endcase
end
endtask // increment_address;
// this procedure reads in a line from the input file and then extracts
// the appropriate information to start the next commands.
task read_write_cmd;
reg [3 : 0] bit_cmd ;
reg [1 : 25*8] cmdstr ;
reg [1 : 5*8] lock_str ;
reg [1 : 5*8] back_str ;
reg [1 : 5*8] same_str ;
reg [1 : 5*8] a64_str ;
begin
lock_str = "FALSE";
back_str = "FALSE";
same_str = "FALSE";
a64_str = "FALSE";
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \"read_write_cmd");
$display("\"");
end
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \"curr_cmd[incode1:incode2] = %0d",curr_cmd[incode1:incode2]);
$display("\"");
end
case ( curr_cmd[incode1:incode2] )
`wait_on_cmd , `idle_cmd , `sleep_cmd , `wakeup_cmd :
begin
pci_command = none;
cdelay_local = 1000; // set any big number
cstate = disabled;
cstate_rw = `false;
cmmd_ready = 1'b0;
if ( curr_cmd[incode1:incode2] ===`sleep_cmd ) begin
if ( (curr_cmd[inwait_num1:inwait_num2] === 0) ) begin
wait_sync[0] = `true;
end else if ( (curr_cmd[inwait_num1:inwait_num2] === 1) ) begin
wait_sync[1] = `true;
end else if ( (curr_cmd[inwait_num1:inwait_num2] === 2) ) begin
wait_sync[2] = `true;
end else if ( (curr_cmd[inwait_num1:inwait_num2] === 3) ) begin
wait_sync[3] = `true;
end else if ( (curr_cmd[inwait_num1:inwait_num2] === 4) ) begin
wait_sync[4] = `true;
end else if ( (curr_cmd[inwait_num1:inwait_num2] === 5) ) begin
wait_sync[5] = `true;
end else if ( (curr_cmd[inwait_num1:inwait_num2] === 6) ) begin
wait_sync[6] = `true;
end else if ( (curr_cmd[inwait_num1:inwait_num2] === 7) ) begin
wait_sync[7] = `true;
end // if
end // if
if ( (wakeup_num === 0) && !(syncout_active[0]) ) begin // for wakeup command followed by idle, sleep command
syncout[0] <= #(1*`time_scale_multiplier) 1'b1 ;
syncout_active[0] = `true;
end // if
if ( (wakeup_num === 1) && !(syncout_active[1]) ) begin
syncout[1] <= #(1*`time_scale_multiplier) 1'b1 ;
syncout_active[1] = `true;
end // if
if ( (wakeup_num === 2) && !(syncout_active[2]) ) begin
syncout[2] <= #(1*`time_scale_multiplier) 1'b1 ;
syncout_active[2] = `true;
end // if
if ( (wakeup_num === 3) && !(syncout_active[3]) ) begin
syncout[3] <= #(1*`time_scale_multiplier) 1'b1 ;
syncout_active[3] = `true;
end // if
if ( (wakeup_num === 4) && !(syncout_active[4]) ) begin
syncout[4] <= #(1*`time_scale_multiplier) 1'b1 ;
syncout_active[4] = `true;
end // if
if ( (wakeup_num === 5) && !(syncout_active[5]) ) begin
syncout[5] <= #(1*`time_scale_multiplier) 1'b1 ;
syncout_active[5] = `true;
end // if
if ( (wakeup_num === 6) && !(syncout_active[6]) ) begin
syncout[6] <= #(1*`time_scale_multiplier) 1'b1 ;
syncout_active[6] = `true;
end // if
if ( (wakeup_num === 7) && !(syncout_active[7]) ) begin
syncout[7] <= #(1*`time_scale_multiplier) 1'b1 ;
syncout_active[7] = `true;
end // if
wakeup_num = -1;
if ( curr_cmd[incode1:incode2] === `idle_cmd ) begin
// curr_cmd_is_idle = `true;
command = idle;
end else begin
get_nxt_cmd;
end // if
end
`read_cycle_cmd , `write_cycle_cmd , `read_continue_cmd , `write_continue_cmd :
begin // read / write commands
if ( get_addr ) begin // only get the first command of the burst cycles
transfer_cnt = 1;
retry_counter = 0;
retry64_32 = `false;
hexaddress = curr_cmd[inaddr1:inaddr2];
tc = curr_cmd[intc1:intc2];
transfer_limit = curr_cmd[intc1:intc2];
if ( curr_cmd[incode1:incode2] === `read_cycle_cmd ) begin
case ( curr_cmd[inrtype1:inrtype2] )
intr_ack: begin
bus_64 = `false;
size = 32;
bit_cmd = 4'b0000;
tc = 1;
transfer_limit = 1;
hexaddress = 32'hffffffff;
sdelay = 0;
end
io_read: begin
bus_64 = `false;
size = 32;
bit_cmd = 4'b0010;
end
rsvd4: begin
bus_64 = `false;
size = 32;
bit_cmd = 4'b0100;
hexaddress[1 : 0] = mode_local;
end
mem_read: begin
bus_64 = `false;
size = 32;
bit_cmd = 4'b0110;
hexaddress[1 : 0] = mode_local;
end
mem_read64: begin
bus_64 = `true;
size = 64;
bit_cmd = 4'b0110;
hexaddress[1 : 0] = mode_local;
end
rsvd8: begin
bus_64 = `false;
size = 32;
bit_cmd = 4'b1000;
hexaddress[1 : 0] = mode_local;
end
config_read: begin
bus_64 = `false;
size = 32;
bit_cmd = 4'b1010;
end
mem_read_mul : begin
bus_64 = `false;
size = 32;
bit_cmd = 4'b1100;
hexaddress[1 : 0] = mode_local;
end
mem_read_mul64: begin
bus_64 = `true;
size = 64;
bit_cmd = 4'b1100;
hexaddress[1 : 0] = mode_local;
end
mem_read_line: begin
bus_64 = `false;
size = 32;
bit_cmd = 4'b1110;
hexaddress[1 : 0] = mode_local;
end
mem_read_line64: begin
bus_64 = `true;
size = 64;
bit_cmd = 4'b1110;
hexaddress[1 : 0] = mode_local;
end
endcase
end else begin
case ( curr_cmd[inwtype1:inwtype2] )
special_cyc: begin
bus_64 = `false;
size = 32;
bit_cmd = 4'b0001;
tc = 1;
transfer_limit = 1;
hexaddress = 32'hffffffff;
end
io_write: begin
bus_64 = `false;
size = 32;
bit_cmd = 4'b0011;
end
rsvd5: begin
bus_64 = `false;
size = 32;
bit_cmd = 4'b0101;
hexaddress[1 : 0] = mode_local;
end
mem_write: begin
bus_64 = `false;
size = 32;
bit_cmd = 4'b0111;
hexaddress[1 : 0] = mode_local;
| This page: |
Created: | Thu Aug 19 11:57:14 1999 |
| From: |
../../../sparc_v8/system/lmc/rtl/pcimaster_fm.v
|