end
mem_write64: begin
bus_64 = `true;
size = 64;
bit_cmd = 4'b0111;
hexaddress[1 : 0] = mode_local;
end
rsvd9: begin
bus_64 = `false;
size = 32;
bit_cmd = 4'b1001;
hexaddress[1 : 0] = mode_local;
end
config_write: begin
bus_64 = `false;
size = 32;
bit_cmd = 4'b1011;
end
mem_write_inv: begin
bus_64 = `false;
size = 32;
bit_cmd = 4'b1111;
hexaddress[1 : 0] = mode_local;
end
mem_write_inv64: begin
bus_64 = `true;
size = 64;
bit_cmd = 4'b1111;
hexaddress[1 : 0] = mode_local;
end
endcase
end // if
addr = hexaddress;
pci_command = (bit_cmd);
cmmd = bit_cmd;
if ( bit_cmd[0] ===1'b0 ) begin
command = read;
end else if ( bit_cmd[0] ===1'b1 ) begin
command = write;
end else begin
if (!((msg_level<`warnings))) begin
$display("NOTE at %0t from %m",$time);
$write(" \"error! command is unknown");
$display("\"");
end
end // if
cdelay_local = cdelay_local_tmp;
if ( curr_cmd[inlock1:inlock2] ) begin
bits[1] = 1'b1;
end else begin
bits[1] = 1'b0;
end // if
bits[3] = 1'b1; // set to check_data true always
if ( command === write ) begin
was_wr = 1'b1;
end else begin
was_wr = 1'b0;
end // if
same_agnt = bits[0];
lock = bits[1];
back2back = bits[2];
check_data = (bits[3] === 1'b1); // not used in the model
// do the following so that the step line gets initialized appropriately
if ( initialize && sdelay !== 0 && cdelay_local === 0 ) begin
cdelay_local = 1;
end // if
if ( cdelay_local !== 0 ) begin
cstate = cmd_dly;
cstate_rw = `false;
cmd_in_progress = 1'b0;
cmmd_ready = 1'b0;
back_to_back = 1'b0;
end else if ( !(burst_cycle) ) begin // cstate becomes cmd_rdy only after burst cycles
cstate = cmd_rdy;
cstate_rw = `false;
cmmd_ready = 1'b1;
back_to_back = back2back;
end // if
end // if
if ( (wakeup_num === 0) && !(syncout_active[0]) ) begin
syncout[0] <= #(1*`time_scale_multiplier) 1'b1 ;
syncout_active[0] = `true;
end // if
if ( (wakeup_num === 1) && !(syncout_active[1]) ) begin
syncout[1] <= #(1*`time_scale_multiplier) 1'b1 ;
syncout_active[1] = `true;
end // if
if ( (wakeup_num === 2) && !(syncout_active[2]) ) begin
syncout[2] <= #(1*`time_scale_multiplier) 1'b1 ;
syncout_active[2] = `true;
end // if
if ( (wakeup_num === 3) && !(syncout_active[3]) ) begin
syncout[3] <= #(1*`time_scale_multiplier) 1'b1 ;
syncout_active[3] = `true;
end // if
if ( (wakeup_num === 4) && !(syncout_active[4]) ) begin
syncout[4] <= #(1*`time_scale_multiplier) 1'b1 ;
syncout_active[4] = `true;
end // if
if ( (wakeup_num === 5) && !(syncout_active[5]) ) begin
syncout[5] <= #(1*`time_scale_multiplier) 1'b1 ;
syncout_active[5] = `true;
end // if
if ( (wakeup_num === 6) && !(syncout_active[6]) ) begin
syncout[6] <= #(1*`time_scale_multiplier) 1'b1 ;
syncout_active[6] = `true;
end // if
if ( (wakeup_num === 7) && !(syncout_active[7]) ) begin
syncout[7] <= #(1*`time_scale_multiplier) 1'b1 ;
syncout_active[7] = `true;
end // if
wakeup_num = -1;
if ( pe === 1 ) begin
bad_data_parity = `true;
bad_addr_parity = `false;
end else if ( pe === 2 ) begin
bad_addr_parity = `true;
bad_data_parity = `false;
end else begin
bad_data_parity = `false;
bad_addr_parity = `false;
end // if
temp_byte = curr_cmd[inbyten1:inbyten2];
byte_enables = temp_byte[3:0];
if ( (size === 64) ) begin
// {byte_enables_7to4, byte_enables} = curr_cmd[inbyten1:inbyten2];
byte_enables_7to4 = temp_byte[7:4];
end // if
delays = curr_cmd[indelay1:indelay2];
if ( command === write ) begin
if ( (size === 64) ) begin
temp_data = curr_cmd[indata1:indata2];
data_words = temp_data[31 : 0];
data_words_63to32 = temp_data[63 : 32];
end else begin
temp_data = curr_cmd[indata1:indata2];
data_words = temp_data[31 : 0];
// data_words = curr_cmd[indata1:indata2];
end // if
end // if
case ( pci_command )
0 : begin cmdstr = "INTERRUPT ACKNOWLEDGE ";
end
1 : begin cmdstr = "SPECIAL CYCLE ";
end
2 : begin cmdstr = "I/O READ ";
end
3 : begin cmdstr = "I/O WRITE ";
end
4 : begin cmdstr = "RESERVED 4 ";
end
5 : begin cmdstr = "RESERVED 5 ";
end
6 : begin cmdstr = "MEMORY READ ";
end
7 : begin cmdstr = "MEMORY WRITE ";
end
8 : begin cmdstr = "RESERVED 8 ";
end
9 : begin cmdstr = "RESERVED 9 ";
end
10 : begin cmdstr = "CONFIGURATION READ ";
end
11 : begin cmdstr = "CONFIGURATION WRITE ";
end
12 : begin cmdstr = "MEMORY READ MULTIPLE ";
end
13 : begin cmdstr = "DUAL ADDRESS CYCLE ";
end
14 : begin cmdstr = "MEMORY READ LINE ";
end
15 : begin cmdstr = "MEMORY WRITE & INVALIDATE";
end
16 : begin cmdstr = "NONE ";
end
default begin cmdstr = "UNKNOWN COMMAND ";
end
endcase
if ((pci_command === 15) && ((curr_cmd[incode1:incode2] ===
`write_cycle_cmd)||(curr_cmd[incode1:incode2]===`read_cycle_cmd))) begin
if (mode_local != 2'b00) begin
if (!((msg_level<`warnings))) begin
$display("NOTE at %0t from %m",$time);
$write(" Illegal MWI command : Only linear addressing order can be used");
$display(" for Memory write and Invalidate cycles");
end
end
if (tc-1 != cacheline_size_reg) begin
if (!((msg_level<`warnings))) begin
$display("NOTE at %0t from %m",$time);
$write(" Illegal MWI command : transfer count parameter specified in command");
$display(" is not equal to cacheline size");
end
end
if (cacheline_size_reg === 0) begin
if (!((msg_level<`warnings))) begin
$display("NOTE at %0t from %m",$time);
$write(" Illegal MWI command : cacheline size = 0");
$display("");
end
end
else if ((addr[9:2] % (cacheline_size_reg + 1)) !== 0) begin
$display($time, ,"%h %h",addr[9:2], cacheline_size_reg);
$display("NOTE at %0t from %m",$time);
$write(" Illegal MWI command : address is not cacheline size aligned");
$display("");
end
end
if ( curr_cmd[inlock1:inlock2] === `true ) begin
lock_str = "TRUE ";
end // if
if ( lastcmd_back === `true ) begin
back_str = "TRUE ";
end // if
if ( lastcmd_same === `true ) begin
same_str = "TRUE ";
end // if
if ( addr_64 === `true ) begin
a64_str = "TRUE ";
end // if
if (!((msg_level<`debug_2))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" ");
$display("");
$write("READ_WRITE_CMD");
$display("");
$write("CODE = ");
$write("%0h",(pci_command));
$write(" : ");
$write("%s",cmdstr);
$display("");
$write("SIZE = ");
$write("%0d",size);
$display("");
$write("UPPER_ADDR = ");
$write("%h",upper_addr);
$display("");
$write("ADDR = ");
$write("%h",(curr_cmd[inaddr1:inaddr2]));
$display("");
$write("TC = ");
$write("%0d",(curr_cmd[intc1:intc2]));
$display("");
$write("BYTEN = ");
$write("%h",(curr_cmd[inbyten1:inbyten2]));
$display("");
$write("CDELAY = ");
$write("%0d",cdelay_local1);
$display("");
$write("UPPER_DATA = ");
$write("%h",(data_words_63to32));
$display("");
$write("DATA = ");
$write("%h",(data_words));
$display("");
$write("DELAY = ");
$write("%0d",(curr_cmd[indelay1:indelay2]));
$display("");
$write("LOCK = ");
$write("%s",lock_str);
$display("");
$write("BACK = ");
$write("%s",back_str);
$display("");
$write("SAME = ");
$write("%s",same_str);
$display("");
$write("STEP = ");
$write("%0d",sdelay);
$display("");
$write("ADDR_64 = ");
$write("%s",a64_str);
$display("");
$write("PE = ");
$write("%0d",pe);
$display("");
$display("\"");
end
get_non_immed(2, next_cmd);
if ( tc > 1 ) begin
get_addr = `false;
tc = tc - 1;
burst_cycle = `true;
end else if ( tc === 1 ) begin
get_addr = `true;
burst_cycle = `false;
end else begin
// $write("tc is not a correct value \n");
end // if
if ( (transfer_cnt < transfer_limit) && (cstate === data_rd) ) begin // for burst read cycle delays
transfer_cnt = transfer_cnt + 1;
byte_en = byte_enables;
byte_en_7to4 = byte_enables_7to4;
if ( delays === 0 ) begin
ready = 1'b1;
if ( transfer_cnt === transfer_limit && !(bus_64 && (INP.pack64nn === 1'b1)) ) begin
last_data = 1'b1;
end else begin
last_data = 1'b0;
end // if
cstate = data_rd;
cstate_rw = `true;
end else begin
if ( !(disconnect_b) ) begin
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" delays > 0 , ready => '0' after time_unit");
$display("\"");
end
ready = 1'b0; // frame to '0' and irdy to '1'
end // if
delay_cnt = delays;
cstate = ddelay;
cstate_rw = `false;
end // if
end // if
end
default
begin
if (!((INP.prstnn===1'b0))) begin
$display("NOTE at %0t from %m",$time);
$write(" \"READ_WRITE CMD : CMD unknown ");
$display("\"");
end
end
endcase
end
endtask // read_write_cmd;
task masterbe;
begin
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \"masterbe");
$display("\"");
end
if ( gnc ) begin
end else begin
if ( first_command ) begin
if ( (curr_cmd[incode1:incode2] !== `configure_cmd) ) begin
read_write_cmd;
if ( ! first_reset ) begin
first_command = `false;
end // if
end // if
if ( sync_first ) begin
sync_first = `false;
syncout[7 : 0] <= #(`time_unit) (8'b00000000) ;
end // if
end // if
if ( INP.prstnn_event && (INP.prstnn === 1'b0) && !(reset_model) ) begin // do reset
reset_model = `true;
old_reset_model = `true; // laverty
end else if ( INP.pclk_event && (INP.pclk === 1'b1) && reset_model && (INP.prstnn === 1'b1) ) begin
reset_model = `false;
if ( (cstate === data_wr) ) begin
tc = 1;
get_addr = `true;
burst_cycle = `false;
// to get rid of burst cycles for write cycles
gnc = `true;
ready = 1'b0;
if ( curr_cmd[incode1:incode2] === `write_cycle_cmd || curr_cmd[incode1:incode2] === `write_continue_cmd ) begin
delete_cmd_code = `write_continue_cmd;
get_nxt_cmd;
end // if
end else if ( (cstate === data_rd) ) begin
tc = 1;
get_addr = `true;
burst_cycle = `false;
// to get rid of burst cycles for read cycles
gnc = `true;
ready = 1'b0;
if ( (INP.pack64nn === 1'b0) ) begin
return_data_addrv(addr,x_64);
end else begin
return_data_addrv(addr,x_32);
end // if
if ( curr_cmd[incode1:incode2] === `read_cycle_cmd || curr_cmd[incode1:incode2] === `read_continue_cmd ) begin
delete_cmd_code = `read_continue_cmd;
get_nxt_cmd;
end // if
end // if
end else if ( INP.pclk_event && (INP.pclk === 1'b1) && (INP.prstnn === 1'b1) ) begin
if ( syncout_active[0] ) begin // deactive syncout after being actived for one clk
syncout[0] <= #(1*`time_scale_multiplier) 1'b0 ;
syncout_active[0] = `false;
end // if
if ( syncout_active[1] ) begin
syncout[1] <= #(1*`time_scale_multiplier) 1'b0 ;
syncout_active[1] = `false;
end // if
if ( syncout_active[2] ) begin
syncout[2] <= #(1*`time_scale_multiplier) 1'b0 ;
syncout_active[2] = `false;
end // if
if ( syncout_active[3] ) begin
syncout[3] <= #(1*`time_scale_multiplier) 1'b0 ;
syncout_active[3] = `false;
end // if
if ( syncout_active[4] ) begin
syncout[4] <= #(1*`time_scale_multiplier) 1'b0 ;
syncout_active[4] = `false;
end // if
if ( syncout_active[5] ) begin
syncout[5] <= #(1*`time_scale_multiplier) 1'b0 ;
syncout_active[5] = `false;
end // if
if ( syncout_active[6] ) begin
syncout[6] <= #(1*`time_scale_multiplier) 1'b0 ;
syncout_active[6] = `false;
end // if
if ( syncout_active[7] ) begin
syncout[7] <= #(1*`time_scale_multiplier) 1'b0 ;
syncout_active[7] = `false;
end // if
if ( (enable === 1'b0) ) begin
cycle_stalled;
back_to_back = 1'b0;
cstate = disabled;
cstate_rw = `false;
end // if
if ( wait_sync[0] ) begin
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" wait_sync[0] is true");
$display("\"");
end
end // if
if ( wait_sync[1] ) begin
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" wait_sync[1] is true");
$display("\"");
end
end // if
if ( wait_sync[2] ) begin
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" wait_sync[2] is true");
$display("\"");
end
end // if
if ( wait_sync[3] ) begin
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" wait_sync[3] is true");
$display("\"");
end
end // if
if ( wait_sync[4] ) begin
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" wait_sync[4] is true");
$display("\"");
end
end // if
if ( wait_sync[5] ) begin
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" wait_sync[5] is true");
$display("\"");
end
end // if
if ( wait_sync[6] ) begin
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" wait_sync[6] is true");
$display("\"");
end
end // if
if ( wait_sync[7] ) begin
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" wait_sync[7] is true");
$display("\"");
end
end // if
if ( retry_counter >= internal_retry_limit ) begin
retry_counter= 0;
cycle_stalled;
gnc = `true;
end // if
if ( (INP.pstopnn === 1'b0) && (INP.pframenn === 1'b0) && (INP.pirdynn === 1'b1) &&
(INP.ptrdynn === 1'b0) && (INP.pdevselnn === 1'b0) && (last_bstate === sm_data) && !(disconnect_a || disconnect_b || disconnect_c) ) begin
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" disconnect_a is true ");
$display("\"");
end
disconnect_a = `true;
disconnect_b = `false;
disconnect_c = `false;
if ( (cmmd === 4'b1111) ) begin // disconnect mem_write_inv will switch command to mem_write
cmmd = (4'b0111);
end // if
if ( bus_64 && (INP.pdevselnn === 1'b0) && (INP.pack64nn !== 1'b0) ) begin
retry64_32 = `true;
end // if
if ( bus_64 && (transfer_cnt > transfer_limit) && (transfer_limit !== 1) ) begin // for 64-bit single data transfer(disconnected laster burst)
cstate = cmd_rdy;
cstate_rw = `false;
ready = 1'b0;
end // if
end else if ( (INP.pstopnn === 1'b0) && (INP.pframenn === 1'b0) && (INP.pirdynn === 1'b0) &&
(INP.ptrdynn === 1'b0) && (INP.pdevselnn === 1'b0) && (last_bstate === sm_data) && !(disconnect_a || disconnect_b || disconnect_c) ) begin
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" disconnect_b is true ");
$display("\"");
end
disconnect_a = `false;
disconnect_b = `true;
disconnect_c = `false;
if ( (cmmd === 4'b1111) ) begin // disconnect mem_write_inv will switch command to mem_write
cmmd = (4'b0111);
end // if
if ( bus_64 && (INP.pdevselnn === 1'b0) && (INP.pack64nn !== 1'b0) ) begin
retry64_32 = `true;
end // if
if ( bus_64 && (transfer_cnt === transfer_limit) && (transfer_limit !== 1) ) begin // for 64-bit single data transfer(disconnected laster burst)
cstate = cmd_rdy;
cstate_rw = `false;
ready = 1'b0;
end // if
end else if ( (INP.pstopnn === 1'b0) && (INP.pframenn === 1'b1) &&
(INP.ptrdynn === 1'b1) && (INP.pdevselnn === 1'b0) && (last_bstate === sm_data) && !(disconnect_a || disconnect_b || disconnect_c) ) begin
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" disconnect_c is true ");
$display("\"");
end
disconnect_a = `false;
disconnect_b = `false;
disconnect_c = `true;
if ( (cmmd === 4'b1111) && (transfer_cnt > 1)) begin // disconnect mem_write_inv will switch command to mem_write
cmmd = (4'b0111);
end // if
if ( bus_64 && (INP.pdevselnn === 1'b0) && (INP.pack64nn !== 1'b0) ) begin
retry64_32 = `true;
end // if
retry_counter = retry_counter + 1;
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \"retry_counter is ");
$write("%0d",(retry_counter));
$display("\"");
end
if ( (delays > 0) ) begin // to restart retry cycle with irdy delay information
ready = 1'b0; // set irdy to '1'
delay_cnt = delays;
cstate = cmd_rdy;
cstate_rw = `false;
cmmd_ready = 1'b1;
end // if
if ( bus_64 && (transfer_cnt === transfer_limit) && (transfer_limit !== 1) ) begin // for 64-bit single data transfer(disconnected laster burst)
cstate = cmd_rdy;
cstate_rw = `false;
ready = 1'b0;
end // if
end else if ( (INP.pstopnn === 1'b0) && (INP.pdevselnn === 1'b1) && (bstate === sm_data) ) begin
if ( (delays > 0) ) begin
ready = 1'b1; // set frame to '1' and irdy to '0'
end // if
end // if
if ( INP.pstopnn === 1'b1 ) begin
disconnect_a = `false;
disconnect_b = `false;
disconnect_c = `false;
end // if
// if burst mode is reserved, cycle is ended
if ((disconnect_a || disconnect_b || disconnect_c) && (mode_local[0] !== 1'b0)&&
((curr_cmd[incode1:incode2] === `read_continue_cmd) ||
(curr_cmd[incode1:incode2] === `write_continue_cmd))) begin
cycle_stalled;
get_addr = `true;
gnc = `true;
end
// disconnect-c case
if ( (INP.pstopnn === 1'b0) && (INP.pframenn === 1'b0) &&
(INP.pdevselnn === 1'b0) && (INP.ptrdynn === 1'b1) &&
(bstate === sm_data)) begin
end else if ( (master_abort === 1'b1) ) begin
if (!((msg_level<`debug_3))) begin
$display("WARNING at %0t from %m",$time);
$write(" \"pci_master_backend: received a master_abort");
$display("\"");
end
cycle_stalled;
gnc = `true;
end else if ( (target_abort === 1'b1) ) begin
if (!((msg_level<`debug_3))) begin
$display("WARNING at %0t from %m",$time);
$write(" \"pci_master_backend: received a target_abort");
$display("\"");
end
cycle_stalled;
gnc = `true;
end // if
case ( cstate )
cmd_rdy : begin
if ( cmd_ack === 1'b1 && double_addr ) begin
double_addr = `false;
end else if ( cmd_ack === 1'b1 ) begin
cmmd_ready = 1'b0;
byte_en = byte_enables;
byte_en_7to4 = byte_enables_7to4;
if ( delays !== 0 ) begin
delay_cnt = delays;
cstate = ddelay;
cstate_rw = `false;
end else begin
delay_cnt = 0;
if ( transfer_cnt === transfer_limit ) begin
if ( bus_64 ) begin // for 64-bit single data transfer
cstate = ddelay;
cstate_rw = `false;
end else begin
if ( (cmmd === 4'b0001) ) begin
last_data = 1'b0; // special cycle keeps frame asserted (bstate stay in mdata phase) to do master abort
// get_nxt_cmd;
end else begin
last_data = 1'b1;
end // if
ready = 1'b1;
case ( command )
read : begin
cstate = data_rd;
cstate_rw = `true;
end
write : begin
dataout = (data_words);
if ( bus_64 ) begin
dataout_63to32 = (data_words_63to32);
end // if
cstate = data_wr;
cstate_rw = `true;
end
default begin /* null */
end
endcase
end // if
end else begin
last_data = 1'b0;
ready = 1'b1;
case ( command )
read : begin
cstate = data_rd;
cstate_rw = `true;
end
write : begin
dataout = (data_words);
if ( bus_64 ) begin
dataout_63to32 = (data_words_63to32);
end // if
cstate = data_wr;
cstate_rw = `true;
end
default begin /* null */
end
endcase
end // if
end // if
end // if
end
data_wr : begin
if ( INP.ptrdynn === 1'b0 && data_phase === 1'b1 && master_abort === 1'b0) begin
increment_address;
addr = hexaddress;
if ( transfer_cnt < transfer_limit ) begin
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" transfer_cnt < transfer_limit");
$display("\"");
end
if ( !(bus_64) ) begin
get_nxt_cmd;
read_write_cmd; // get next command to update the data before output them
transfer_cnt = transfer_cnt + 1;
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" transfer_cnt value increased 1 when cstate = data_wr ");
$display("\"");
end
byte_en = byte_enables;
end else if ( bus_64 && (((INP.pdevselnn === 1'b0) && (INP.pack64nn === 1'b0)) || second_be_transfer) ) begin
get_nxt_cmd;
read_write_cmd;
transfer_cnt = transfer_cnt + 1;
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" transfer_cnt value increased 1 when cstate = data_wr ");
$display("\"");
end
byte_en = byte_enables;
byte_en_7to4 = byte_enables_7to4;
second_be_transfer = `false;
end else if ( bus_64 && (INP.pdevselnn === 1'b0) && (INP.pack64nn === 1'b1) ) begin
byte_en = byte_enables_7to4; // previous cycle pbenn data send to pcxbenn
second_be_transfer = `true;
end // if
if ( delays === 0 ) begin
if ( !(bus_64) ) begin
dataout = (data_words);
end else if ( bus_64 && (((INP.pdevselnn === 1'b0) && (INP.pack64nn === 1'b0)) || second_data_transfer) ) begin
dataout = (data_words);
dataout_63to32 = (data_words_63to32);
second_data_transfer = `false;
end else if ( bus_64 && (INP.pdevselnn === 1'b0) && (INP.pack64nn === 1'b1) ) begin
dataout = (data_words_63to32);
second_data_transfer = `true;
end // if
if ( transfer_cnt === transfer_limit && !(bus_64 && (INP.pdevselnn === 1'b0) && (INP.pack64nn === 1'b1)) ) begin
last_data = 1'b1; // last_data high causes comp high and thus frame => '1'
end else begin
last_data = 1'b0;
end // if
ready = 1'b1;
end else begin // for burst write cycle delays
if ( !(disconnect_b) ) begin
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" delays is > 0 , ready => '0' after time_unit");
$display("\"");
end
ready = 1'b0; // frame to '0' and irdy to '1'
end // if
if ( !(bus_64) ) begin
dataout = (32'h00000000);
end else if ( bus_64 && (((INP.pdevselnn === 1'b0) && (INP.pack64nn === 1'b0)) || second_data_transfer) ) begin
dataout = (32'h00000000);
dataout_63to32 = (32'h00000000);
second_data_transfer = `false;
end else if ( bus_64 && (INP.pdevselnn === 1'b0) && (INP.pack64nn === 1'b1) ) begin
dataout = (32'h00000000);
second_data_transfer = `true;
end // if
delay_cnt = delays;
cstate = ddelay;
cstate_rw = `false;
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" cstate changes from data_wr to delay ");
$display("\"");
end
end // if
end else begin // transfer_cnt = transfer_limit
if ( !(bus_64) ) begin
ready = 1'b0;
dataout = (32'h00000000);
byte_en = 4'b0000;
last_data = 1'b0;
get_nxt_cmd;
read_write_cmd;
end else if ( bus_64 && (((INP.pdevselnn === 1'b0) && (INP.pack64nn === 1'b0)) || second_data_transfer) ) begin
ready = 1'b0;
dataout = (32'h00000000);
dataout_63to32 = (32'h00000000);
byte_en = 4'b0000;
byte_en_7to4 = 4'b0000;
last_data = 1'b0;
get_nxt_cmd;
read_write_cmd;
second_data_transfer = `false;
end else if ( bus_64 && (INP.pdevselnn === 1'b0) && (INP.pack64nn === 1'b1) ) begin
dataout = (data_words_63to32);
byte_en = byte_enables_7to4;
last_data = 1'b1; // set frame to '1'
second_data_transfer = `true;
if ( (delays > 0) ) begin
ready = 1'b0; // set irdy to '1'
byte_en = byte_enables_7to4; // send pbenn to pcxbenn
dataout = (32'h00000000);
delay_cnt = delays;
cstate = ddelay;
cstate_rw = `false;
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" cstate delays from data_wr ");
$display("\"");
end
end // if
end // if
end // if
end // if
end
data_rd : begin
if ( INP.ptrdynn === 1'b0 && data_phase === 1'b1 && master_abort === 1'b0) begin
increment_address;
if ( transfer_cnt === transfer_limit ) begin
if ( !(bus_64) ) begin
return_data_addrv(addr,INP.pad);
byte_en = 4'b0000;
ready = 1'b0;
last_data = 1'b0;
gnc = `true;
cstate = disabled; // added on 4/5/94 to prevent req -> 0 at end of read because of cmd_in_progress still be 1
cstate_rw = `false;
get_nxt_cmd;
end else if ( bus_64 && (((INP.pdevselnn === 1'b0) && (INP.pack64nn === 1'b0)) || second_data_transfer) ) begin
if ( (INP.pdevselnn === 1'b0) && (INP.pack64nn === 1'b0) ) begin
return_data_addrv(addr,{INP.pd, INP.pad});
end else begin
return_data_addrv(addr,{first_data, INP.pad});
end // if
byte_en = 4'b0000;
byte_en_7to4 = 4'b0000;
ready = 1'b0;
last_data = 1'b0;
gnc = `true;
second_data_transfer = `false;
cstate = disabled; // added on 4/5/94 to prevent req -> 0 at end of read because of cmd_in_progress still be 1
cstate_rw = `false;
get_nxt_cmd;
end else if ( bus_64 && (INP.pdevselnn === 1'b0) && (INP.pack64nn === 1'b1) ) begin
return_data_addrv(addr,INP.pad);
first_data = INP.pad;
byte_en = byte_enables_7to4;
last_data = 1'b1; // set frame to '1'
second_data_transfer = `true;
if ( (delays > 0) ) begin
ready = 1'b0; // set irdy to '1'
byte_en = byte_enables_7to4; // send pbenn to pcxbenn
dataout = (32'h00000000);
delay_cnt = delays;
cstate = ddelay;
cstate_rw = `false;
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" cstate delays from data_wr ");
$display("\"");
end
end // if
end // if
end else begin
if ( !(bus_64) ) begin
return_data_addrv(addr,INP.pad);
gnc = `true;
get_nxt_cmd;
end else if ( bus_64 && (((INP.pdevselnn === 1'b0) && (INP.pack64nn === 1'b0)) || second_data_transfer) ) begin
if ( (INP.pdevselnn === 1'b0) && (INP.pack64nn === 1'b0) ) begin
return_data_addrv(addr,{INP.pd, INP.pad});
end else begin
return_data_addrv(addr,{first_data, INP.pad});
end // if
gnc = `true;
second_data_transfer = `false;
get_nxt_cmd;
end else if ( bus_64 && (INP.pdevselnn === 1'b0) && (INP.pack64nn === 1'b1) ) begin
return_data_addrv(addr,INP.pad);
byte_en = byte_enables_7to4;
second_data_transfer = `true;
if ( (delays > 0) ) begin
ready = 1'b0; // set irdy to '1'
byte_en = byte_enables_7to4; // send pbenn to pcxbenn
dataout = (32'h00000000);
delay_cnt = delays;
cstate = ddelay;
cstate_rw = `false;
if (!((msg_level<`debug_3))) begin
$display("NOTE at %0t from %m",$time);
$write(" \" cstate delays from data_wr ");
$display("\"");
end
end // if
end // if
end // if
addr = hexaddress;
end // if
end
ddelay : begin
if ( (delay_cnt > 0) ) begin
delay_cnt = delay_cnt - 1;
end // if
if ( bus_64 && (transfer_limit === transfer_limit) ) begin // for 64-bit single data transfer
last_data = 1'b0; // frame needs to wait for single data phase with 64-bit transfer
wait_devsel_delay = `true; // delay until frame signal being resolved by devsel and ack64
end // if
if ( wait_devsel_delay && (INP.pdevselnn === 1'b0) ) begin
wait_devsel_delay = `false;
end // if
if ( (delay_cnt === 0) && !(wait_devsel_delay) ) begin
ready = 1'b1;
if ( transfer_cnt === transfer_limit ) begin
if ( bus_64 && (INP.pdevselnn === 1'b0) && (INP.pack64nn !== 1'b0) && !(second_data_transfer) ) begin
last_data = 1'b0; // frame stay '0' for 64-bit single data transfer when ack64 is not low
end else begin
last_data = 1'b1;
end // if
end else begin
last_data = 1'b0; // frame stay '0' for burst cycle
end // if
case ( command )
read : begin
cstate = data_rd;
| This page: |
Created: | Thu Aug 19 11:57:17 1999 |
| From: |
../../../sparc_v8/system/lmc/rtl/pcimaster_fm.v
|