//
// Copyright Notice and Proprietary Information
//
// Copyright (C) 1992 - 1995 Synopsys, Inc. All rights reserved. This Software
// and manual are owned by Synopsys, Inc., and may be used only as authorized
// in the license agreement controlling such use. No part of this publication
// may be reproduced, transmitted, or translated, in any form or by any means,
// electronic, mechanical, manual, optical, or otherwise, without prior written
// permission of Synopsys, Inc., or as expressly provided by the license agreement.
//
// Destination Control Statement
//
// All technical data contained in this publication is subject to the export
// control laws of the United States of America. Disclosure to nationals of other
// countries contrary to United States law is prohibited. It is the reader's
// responsibility to determine the applicable regulations and to comply with them.
//
// Disclaimer
//
// Synopsys, Inc., makes no warranty of any kind, express or implied, with regard
// to this material, including, but not limited to, the implied warranties of
// merchantability and fitness for a particular purpose.
//
// Synopsys, Inc., reserves the right to make changes without further notice to
// the products described herein. Synopsys, Inc. does not assume any liability
// arising out of the application or use of any product or circuit described
// herein. The Synopsys products described herein are not authorized for use as
// components in life-support devices.
//
// library ssi
`lmv_timescale
`define GNT_ASSERTED_CLKS 1 // numberof clocks gnt is asserted for MS16
//--- VER_GEN Version 7.0 ---
module pcimonitor_times
;
integer tcy_min_clk
; initial tcy_min_clk
= 0;
integer tcy_max_clk
; initial tcy_max_clk
= 0;
integer tpwh_min_clk
; initial tpwh_min_clk
= 0;
integer tpwh_max_clk
; initial tpwh_max_clk
= 0;
integer tpwl_min_clk
; initial tpwl_min_clk
= 0;
integer tpwl_max_clk
; initial tpwl_max_clk
= 0;
integer twd_clk
; initial twd_clk
= 0;
integer tcy_min_rstnn
; initial tcy_min_rstnn
= 0;
integer tcy_max_rstnn
; initial tcy_max_rstnn
= 0;
integer tpwh_min_rstnn
; initial tpwh_min_rstnn
= 0;
integer tpwh_max_rstnn
; initial tpwh_max_rstnn
= 0;
integer tpwl_min_rstnn
; initial tpwl_min_rstnn
= 0;
integer tpwl_max_rstnn
; initial tpwl_max_rstnn
= 0;
integer twd_rstnn
; initial twd_rstnn
= 0;
integer trs_ad_clk
; initial trs_ad_clk
= 0;
integer trh_ad_clk
; initial trh_ad_clk
= 0;
integer twd_ad
[63:0];
initial begin
twd_ad[63] = 0;
twd_ad[62] = 0;
twd_ad[61] = 0;
twd_ad[60] = 0;
twd_ad[59] = 0;
twd_ad[58] = 0;
twd_ad[57] = 0;
twd_ad[56] = 0;
twd_ad[55] = 0;
twd_ad[54] = 0;
twd_ad[53] = 0;
twd_ad[52] = 0;
twd_ad[51] = 0;
twd_ad[50] = 0;
twd_ad[49] = 0;
twd_ad[48] = 0;
twd_ad[47] = 0;
twd_ad[46] = 0;
twd_ad[45] = 0;
twd_ad[44] = 0;
twd_ad[43] = 0;
twd_ad[42] = 0;
twd_ad[41] = 0;
twd_ad[40] = 0;
twd_ad[39] = 0;
twd_ad[38] = 0;
twd_ad[37] = 0;
twd_ad[36] = 0;
twd_ad[35] = 0;
twd_ad[34] = 0;
twd_ad[33] = 0;
twd_ad[32] = 0;
twd_ad[31] = 0;
twd_ad[30] = 0;
twd_ad[29] = 0;
twd_ad[28] = 0;
twd_ad[27] = 0;
twd_ad[26] = 0;
twd_ad[25] = 0;
twd_ad[24] = 0;
twd_ad[23] = 0;
twd_ad[22] = 0;
twd_ad[21] = 0;
twd_ad[20] = 0;
twd_ad[19] = 0;
twd_ad[18] = 0;
twd_ad[17] = 0;
twd_ad[16] = 0;
twd_ad[15] = 0;
twd_ad[14] = 0;
twd_ad[13] = 0;
twd_ad[12] = 0;
twd_ad[11] = 0;
twd_ad[10] = 0;
twd_ad[9] = 0;
twd_ad[8] = 0;
twd_ad[7] = 0;
twd_ad[6] = 0;
twd_ad[5] = 0;
twd_ad[4] = 0;
twd_ad[3] = 0;
twd_ad[2] = 0;
twd_ad[1] = 0;
twd_ad[0] = 0;
end
reg [127:0] tpr_clk_ad
;
initial begin
tpr_clk_ad = 128'b0;
end
integer tld_ad
[63:0];
initial begin
tld_ad[63] = 0;
tld_ad[62] = 0;
tld_ad[61] = 0;
tld_ad[60] = 0;
tld_ad[59] = 0;
tld_ad[58] = 0;
tld_ad[57] = 0;
tld_ad[56] = 0;
tld_ad[55] = 0;
tld_ad[54] = 0;
tld_ad[53] = 0;
tld_ad[52] = 0;
tld_ad[51] = 0;
tld_ad[50] = 0;
tld_ad[49] = 0;
tld_ad[48] = 0;
tld_ad[47] = 0;
tld_ad[46] = 0;
tld_ad[45] = 0;
tld_ad[44] = 0;
tld_ad[43] = 0;
tld_ad[42] = 0;
tld_ad[41] = 0;
tld_ad[40] = 0;
tld_ad[39] = 0;
tld_ad[38] = 0;
tld_ad[37] = 0;
tld_ad[36] = 0;
tld_ad[35] = 0;
tld_ad[34] = 0;
tld_ad[33] = 0;
tld_ad[32] = 0;
tld_ad[31] = 0;
tld_ad[30] = 0;
tld_ad[29] = 0;
tld_ad[28] = 0;
tld_ad[27] = 0;
tld_ad[26] = 0;
tld_ad[25] = 0;
tld_ad[24] = 0;
tld_ad[23] = 0;
tld_ad[22] = 0;
tld_ad[21] = 0;
tld_ad[20] = 0;
tld_ad[19] = 0;
tld_ad[18] = 0;
tld_ad[17] = 0;
tld_ad[16] = 0;
tld_ad[15] = 0;
tld_ad[14] = 0;
tld_ad[13] = 0;
tld_ad[12] = 0;
tld_ad[11] = 0;
tld_ad[10] = 0;
tld_ad[9] = 0;
tld_ad[8] = 0;
tld_ad[7] = 0;
tld_ad[6] = 0;
tld_ad[5] = 0;
tld_ad[4] = 0;
tld_ad[3] = 0;
tld_ad[2] = 0;
tld_ad[1] = 0;
tld_ad[0] = 0;
end
integer trs_cxbenn_clk
; initial trs_cxbenn_clk
= 0;
integer trh_cxbenn_clk
; initial trh_cxbenn_clk
= 0;
integer twd_cxbenn
[7:0];
initial begin
twd_cxbenn[7] = 0;
twd_cxbenn[6] = 0;
twd_cxbenn[5] = 0;
twd_cxbenn[4] = 0;
twd_cxbenn[3] = 0;
twd_cxbenn[2] = 0;
twd_cxbenn[1] = 0;
twd_cxbenn[0] = 0;
end
reg [127:0] tpr_clk_cxbenn
;
initial begin
tpr_clk_cxbenn = 128'b0;
end
integer tld_cxbenn
[7:0];
initial begin
tld_cxbenn[7] = 0;
tld_cxbenn[6] = 0;
tld_cxbenn[5] = 0;
tld_cxbenn[4] = 0;
tld_cxbenn[3] = 0;
tld_cxbenn[2] = 0;
tld_cxbenn[1] = 0;
tld_cxbenn[0] = 0;
end
integer trs_par_clk
; initial trs_par_clk
= 0;
integer trh_par_clk
; initial trh_par_clk
= 0;
integer twd_par
; initial twd_par
= 0;
reg [127:0] tpr_clk_par
;
initial begin
tpr_clk_par = 128'b0;
end
integer tld_par
; initial tld_par
= 0;
integer trs_framenn_clk
; initial trs_framenn_clk
= 0;
integer trh_framenn_clk
; initial trh_framenn_clk
= 0;
integer twd_framenn
; initial twd_framenn
= 0;
integer trs_trdynn_clk
; initial trs_trdynn_clk
= 0;
integer trh_trdynn_clk
; initial trh_trdynn_clk
= 0;
integer twd_trdynn
; initial twd_trdynn
= 0;
integer trs_irdynn_clk
; initial trs_irdynn_clk
= 0;
integer trh_irdynn_clk
; initial trh_irdynn_clk
= 0;
integer twd_irdynn
; initial twd_irdynn
= 0;
integer trs_stopnn_clk
; initial trs_stopnn_clk
= 0;
integer trh_stopnn_clk
; initial trh_stopnn_clk
= 0;
integer twd_stopnn
; initial twd_stopnn
= 0;
integer trs_devselnn_clk
; initial trs_devselnn_clk
= 0;
integer trh_devselnn_clk
; initial trh_devselnn_clk
= 0;
integer twd_devselnn
; initial twd_devselnn
= 0;
integer trs_idsel_clk
; initial trs_idsel_clk
= 0;
integer trh_idsel_clk
; initial trh_idsel_clk
= 0;
integer twd_idsel
[7:0];
initial begin
twd_idsel[7] = 0;
twd_idsel[6] = 0;
twd_idsel[5] = 0;
twd_idsel[4] = 0;
twd_idsel[3] = 0;
twd_idsel[2] = 0;
twd_idsel[1] = 0;
twd_idsel[0] = 0;
end
integer trs_perrnn_clk
; initial trs_perrnn_clk
= 0;
integer trh_perrnn_clk
; initial trh_perrnn_clk
= 0;
integer twd_perrnn
; initial twd_perrnn
= 0;
integer trs_serrnn_clk
; initial trs_serrnn_clk
= 0;
integer trh_serrnn_clk
; initial trh_serrnn_clk
= 0;
integer twd_serrnn
; initial twd_serrnn
= 0;
integer trs_reqnn_clk
; initial trs_reqnn_clk
= 0;
integer trh_reqnn_clk
; initial trh_reqnn_clk
= 0;
integer twd_reqnn
[7:0];
initial begin
twd_reqnn[7] = 0;
twd_reqnn[6] = 0;
twd_reqnn[5] = 0;
twd_reqnn[4] = 0;
twd_reqnn[3] = 0;
twd_reqnn[2] = 0;
twd_reqnn[1] = 0;
twd_reqnn[0] = 0;
end
integer trs_gntnn_clk
; initial trs_gntnn_clk
= 0;
integer trh_gntnn_clk
; initial trh_gntnn_clk
= 0;
integer twd_gntnn
[7:0];
initial begin
twd_gntnn[7] = 0;
twd_gntnn[6] = 0;
twd_gntnn[5] = 0;
twd_gntnn[4] = 0;
twd_gntnn[3] = 0;
twd_gntnn[2] = 0;
twd_gntnn[1] = 0;
twd_gntnn[0] = 0;
end
reg [127:0] tpr_clk_gntnn
;
initial begin
tpr_clk_gntnn = 128'b0;
end
integer tld_gntnn
[7:0];
initial begin
tld_gntnn[7] = 0;
tld_gntnn[6] = 0;
tld_gntnn[5] = 0;
tld_gntnn[4] = 0;
tld_gntnn[3] = 0;
tld_gntnn[2] = 0;
tld_gntnn[1] = 0;
tld_gntnn[0] = 0;
end
integer trs_locknn_clk
; initial trs_locknn_clk
= 0;
integer trh_locknn_clk
; initial trh_locknn_clk
= 0;
integer twd_locknn
; initial twd_locknn
= 0;
integer trs_par64_clk
; initial trs_par64_clk
= 0;
integer trh_par64_clk
; initial trh_par64_clk
= 0;
integer twd_par64
; initial twd_par64
= 0;
integer trs_req64nn_clk
; initial trs_req64nn_clk
= 0;
integer trh_req64nn_clk
; initial trh_req64nn_clk
= 0;
integer twd_req64nn
; initial twd_req64nn
= 0;
integer trs_ack64nn_clk
; initial trs_ack64nn_clk
= 0;
integer trh_ack64nn_clk
; initial trh_ack64nn_clk
= 0;
integer twd_ack64nn
; initial twd_ack64nn
= 0;
integer trs_sbonn_clk
; initial trs_sbonn_clk
= 0;
integer trh_sbonn_clk
; initial trh_sbonn_clk
= 0;
integer twd_sbonn
; initial twd_sbonn
= 0;
integer trs_sdone_clk
; initial trs_sdone_clk
= 0;
integer trh_sdone_clk
; initial trh_sdone_clk
= 0;
integer twd_sdone
; initial twd_sdone
= 0;
integer trs_intann_clk
; initial trs_intann_clk
= 0;
integer trh_intann_clk
; initial trh_intann_clk
= 0;
integer twd_intann
; initial twd_intann
= 0;
integer trs_intbnn_clk
; initial trs_intbnn_clk
= 0;
integer trh_intbnn_clk
; initial trh_intbnn_clk
= 0;
integer twd_intbnn
; initial twd_intbnn
= 0;
integer trs_intcnn_clk
; initial trs_intcnn_clk
= 0;
integer trh_intcnn_clk
; initial trh_intcnn_clk
= 0;
integer twd_intcnn
; initial twd_intcnn
= 0;
integer trs_intdnn_clk
; initial trs_intdnn_clk
= 0;
integer trh_intdnn_clk
; initial trh_intdnn_clk
= 0;
integer twd_intdnn
; initial twd_intdnn
= 0;
endmodule // pcimonitor_times
module pcimonitor_flags
;
integer option
;
reg time_check
, x_check
, annotated
;
integer debug_level
, vlt
, tmp
, DF
;
endmodule // pcimonitor_flags
module pcimonitor_fm_cntrl
;
reg clk
;
reg ck_clk
;
reg rstnn
;
reg ck_rstnn
;
reg ad
;
reg ad_in
;
reg r_ad_clk
;
reg cxbenn
;
reg cxbenn_in
;
reg r_cxbenn_clk
;
reg par
;
reg par_in
;
reg r_par_clk
;
reg framenn
;
reg r_framenn_clk
;
reg trdynn
;
reg r_trdynn_clk
;
reg irdynn
;
reg r_irdynn_clk
;
reg stopnn
;
reg r_stopnn_clk
;
reg devselnn
;
reg r_devselnn_clk
;
reg idsel
;
reg r_idsel_clk
;
reg perrnn
;
reg r_perrnn_clk
;
reg serrnn
;
reg r_serrnn_clk
;
reg reqnn
;
reg r_reqnn_clk
;
reg gntnn
;
reg gntnn_in
;
reg r_gntnn_clk
;
reg locknn
;
reg r_locknn_clk
;
reg par64
;
reg r_par64_clk
;
reg req64nn
;
reg r_req64nn_clk
;
reg ack64nn
;
reg r_ack64nn_clk
;
reg sbonn
;
reg r_sbonn_clk
;
reg sdone
;
reg r_sdone_clk
;
reg intann
;
reg r_intann_clk
;
reg intbnn
;
reg r_intbnn_clk
;
reg intcnn
;
reg r_intcnn_clk
;
reg intdnn
;
reg r_intdnn_clk
;
integer tm_event
;
endmodule // pcimonitor_fm_cntrl
module pcimonitor_fm_input
;
reg clk
, clk_old
;
reg clk_event
;
integer clk_event_time
; initial clk_event_time
= -500*`time_scale_multiplier;
integer clk_last_event
;
always @(clk) begin
clk_event = `true;
clk_event <= #(0) `false;
clk_event_time = $time;
end
reg rstnn
, rstnn_old
;
reg rstnn_event
;
integer rstnn_event_time
; initial rstnn_event_time
= -500*`time_scale_multiplier;
integer rstnn_last_event
;
always @(rstnn) begin
rstnn_event = `true;
rstnn_event <= #(0) `false;
rstnn_event_time = $time;
end
reg [63:0] ad
, ad_old
;
reg ad_63
,ad_62
,ad_61
,ad_60
,ad_59
,ad_58
,ad_57
,ad_56
,ad_55
,ad_54
,ad_53
,ad_52
,ad_51
,ad_50
,ad_49
,ad_48
,ad_47
,ad_46
,ad_45
,ad_44
,ad_43
,ad_42
,ad_41
,ad_40
,ad_39
,ad_38
,ad_37
,ad_36
,ad_35
,ad_34
,ad_33
,ad_32
,ad_31
,ad_30
,ad_29
,ad_28
,ad_27
,ad_26
,ad_25
,ad_24
,ad_23
,ad_22
,ad_21
,ad_20
,ad_19
,ad_18
,ad_17
,ad_16
,ad_15
,ad_14
,ad_13
,ad_12
,ad_11
,ad_10
,ad_9
,ad_8
,ad_7
,ad_6
,ad_5
,ad_4
,ad_3
,ad_2
,ad_1
,ad_0
;
reg ad_event
;
integer ad_event_time
; initial ad_event_time
= -500*`time_scale_multiplier;
integer ad_last_event
;
always @(ad_63 or ad_62 or ad_61 or ad_60 or ad_59 or ad_58 or ad_57 or ad_56 or ad_55 or ad_54 or ad_53 or ad_52 or ad_51 or ad_50 or ad_49 or ad_48 or ad_47 or ad_46 or ad_45 or ad_44 or ad_43 or ad_42 or ad_41 or ad_40 or ad_39 or ad_38 or ad_37 or ad_36 or ad_35 or ad_34 or ad_33 or ad_32 or ad_31 or ad_30 or ad_29 or ad_28 or ad_27 or ad_26 or ad_25 or ad_24 or ad_23 or ad_22 or ad_21 or ad_20 or ad_19 or ad_18 or ad_17 or ad_16 or ad_15 or ad_14 or ad_13 or ad_12 or ad_11 or ad_10 or ad_9 or ad_8 or ad_7 or ad_6 or ad_5 or ad_4 or ad_3 or ad_2 or ad_1 or ad_0) begin
ad[63] = ad_63;
ad[62] = ad_62;
ad[61] = ad_61;
ad[60] = ad_60;
ad[59] = ad_59;
ad[58] = ad_58;
ad[57] = ad_57;
ad[56] = ad_56;
ad[55] = ad_55;
ad[54] = ad_54;
ad[53] = ad_53;
ad[52] = ad_52;
ad[51] = ad_51;
ad[50] = ad_50;
ad[49] = ad_49;
ad[48] = ad_48;
ad[47] = ad_47;
ad[46] = ad_46;
ad[45] = ad_45;
ad[44] = ad_44;
ad[43] = ad_43;
ad[42] = ad_42;
ad[41] = ad_41;
ad[40] = ad_40;
ad[39] = ad_39;
ad[38] = ad_38;
ad[37] = ad_37;
ad[36] = ad_36;
ad[35] = ad_35;
ad[34] = ad_34;
ad[33] = ad_33;
ad[32] = ad_32;
ad[31] = ad_31;
ad[30] = ad_30;
ad[29] = ad_29;
ad[28] = ad_28;
ad[27] = ad_27;
ad[26] = ad_26;
ad[25] = ad_25;
ad[24] = ad_24;
ad[23] = ad_23;
ad[22] = ad_22;
ad[21] = ad_21;
ad[20] = ad_20;
ad[19] = ad_19;
ad[18] = ad_18;
ad[17] = ad_17;
ad[16] = ad_16;
ad[15] = ad_15;
ad[14] = ad_14;
ad[13] = ad_13;
ad[12] = ad_12;
ad[11] = ad_11;
ad[10] = ad_10;
ad[9] = ad_9;
ad[8] = ad_8;
ad[7] = ad_7;
ad[6] = ad_6;
ad[5] = ad_5;
ad[4] = ad_4;
ad[3] = ad_3;
ad[2] = ad_2;
ad[1] = ad_1;
ad[0] = ad_0;
ad_event = `true;
ad_event <= #(0) `false;
ad_event_time = $time;
end
reg [7:0] cxbenn
, cxbenn_old
;
reg cxbenn_7
,cxbenn_6
,cxbenn_5
,cxbenn_4
,cxbenn_3
,cxbenn_2
,cxbenn_1
,cxbenn_0
;
reg cxbenn_event
;
integer cxbenn_event_time
; initial cxbenn_event_time
= -500*`time_scale_multiplier;
integer cxbenn_last_event
;
always @(cxbenn_7 or cxbenn_6 or cxbenn_5 or cxbenn_4 or cxbenn_3 or cxbenn_2 or cxbenn_1 or cxbenn_0) begin
cxbenn[7] = cxbenn_7;
cxbenn[6] = cxbenn_6;
cxbenn[5] = cxbenn_5;
cxbenn[4] = cxbenn_4;
cxbenn[3] = cxbenn_3;
cxbenn[2] = cxbenn_2;
cxbenn[1] = cxbenn_1;
cxbenn[0] = cxbenn_0;
cxbenn_event = `true;
cxbenn_event <= #(0) `false;
cxbenn_event_time = $time;
end
reg par
, par_old
;
reg par_event
;
integer par_event_time
; initial par_event_time
= -500*`time_scale_multiplier;
integer par_last_event
;
always @(par) begin
par_event = `true;
par_event <= #(0) `false;
par_event_time = $time;
end
reg framenn
, framenn_old
;
reg framenn_event
;
integer framenn_event_time
; initial framenn_event_time
= -500*`time_scale_multiplier;
integer framenn_last_event
;
always @(framenn) begin
framenn_event = `true;
framenn_event <= #(0) `false;
framenn_event_time = $time;
end
reg trdynn
, trdynn_old
;
reg trdynn_event
;
integer trdynn_event_time
; initial trdynn_event_time
= -500*`time_scale_multiplier;
integer trdynn_last_event
;
always @(trdynn) begin
trdynn_event = `true;
trdynn_event <= #(0) `false;
trdynn_event_time = $time;
end
reg irdynn
, irdynn_old
;
reg irdynn_event
;
integer irdynn_event_time
; initial irdynn_event_time
= -500*`time_scale_multiplier;
integer irdynn_last_event
;
always @(irdynn) begin
irdynn_event = `true;
irdynn_event <= #(0) `false;
irdynn_event_time = $time;
end
reg stopnn
, stopnn_old
;
reg stopnn_event
;
integer stopnn_event_time
; initial stopnn_event_time
= -500*`time_scale_multiplier;
integer stopnn_last_event
;
always @(stopnn) begin
stopnn_event = `true;
stopnn_event <= #(0) `false;
stopnn_event_time = $time;
end
reg devselnn
, devselnn_old
;
reg devselnn_event
;
integer devselnn_event_time
; initial devselnn_event_time
= -500*`time_scale_multiplier;
integer devselnn_last_event
;
always @(devselnn) begin
devselnn_event = `true;
devselnn_event <= #(0) `false;
devselnn_event_time = $time;
end
reg [7:0] idsel
, idsel_old
;
reg idsel_7
,idsel_6
,idsel_5
,idsel_4
,idsel_3
,idsel_2
,idsel_1
,idsel_0
;
reg idsel_event
;
integer idsel_event_time
; initial idsel_event_time
= -500*`time_scale_multiplier;
integer idsel_last_event
;
always @(idsel_7 or idsel_6 or idsel_5 or idsel_4 or idsel_3 or idsel_2 or idsel_1 or idsel_0) begin
idsel[7] = idsel_7;
idsel[6] = idsel_6;
idsel[5] = idsel_5;
idsel[4] = idsel_4;
idsel[3] = idsel_3;
idsel[2] = idsel_2;
idsel[1] = idsel_1;
idsel[0] = idsel_0;
idsel_event = `true;
idsel_event <= #(0) `false;
idsel_event_time = $time;
end
reg perrnn
, perrnn_old
;
reg perrnn_event
;
integer perrnn_event_time
; initial perrnn_event_time
= -500*`time_scale_multiplier;
integer perrnn_last_event
;
always @(perrnn) begin
perrnn_event = `true;
perrnn_event <= #(0) `false;
perrnn_event_time = $time;
end
reg serrnn
, serrnn_old
;
reg serrnn_event
;
integer serrnn_event_time
; initial serrnn_event_time
= -500*`time_scale_multiplier;
integer serrnn_last_event
;
always @(serrnn) begin
serrnn_event = `true;
serrnn_event <= #(0) `false;
serrnn_event_time = $time;
end
reg [7:0] reqnn
, reqnn_old
;
reg reqnn_7
,reqnn_6
,reqnn_5
,reqnn_4
,reqnn_3
,reqnn_2
,reqnn_1
,reqnn_0
;
reg reqnn_event
;
integer reqnn_event_time
; initial reqnn_event_time
= -500*`time_scale_multiplier;
integer reqnn_last_event
;
always @(reqnn_7 or reqnn_6 or reqnn_5 or reqnn_4 or reqnn_3 or reqnn_2 or reqnn_1 or reqnn_0) begin
reqnn[7] = reqnn_7;
reqnn[6] = reqnn_6;
reqnn[5] = reqnn_5;
reqnn[4] = reqnn_4;
reqnn[3] = reqnn_3;
reqnn[2] = reqnn_2;
reqnn[1] = reqnn_1;
reqnn[0] = reqnn_0;
reqnn_event = `true;
reqnn_event <= #(0) `false;
reqnn_event_time = $time;
end
reg [7:0] gntnn
, gntnn_old
;
reg gntnn_7
,gntnn_6
,gntnn_5
,gntnn_4
,gntnn_3
,gntnn_2
,gntnn_1
,gntnn_0
;
reg gntnn_event
;
integer gntnn_event_time
; initial gntnn_event_time
= -500*`time_scale_multiplier;
integer gntnn_last_event
;
always @(gntnn_7 or gntnn_6 or gntnn_5 or gntnn_4 or gntnn_3 or gntnn_2 or gntnn_1 or gntnn_0) begin
gntnn[7] = gntnn_7;
gntnn[6] = gntnn_6;
gntnn[5] = gntnn_5;
gntnn[4] = gntnn_4;
gntnn[3] = gntnn_3;
gntnn[2] = gntnn_2;
gntnn[1] = gntnn_1;
gntnn[0] = gntnn_0;
gntnn_event = `true;
gntnn_event <= #(0) `false;
gntnn_event_time = $time;
end
reg locknn
, locknn_old
;
reg locknn_event
;
integer locknn_event_time
; initial locknn_event_time
= -500*`time_scale_multiplier;
integer locknn_last_event
;
always @(locknn) begin
locknn_event = `true;
locknn_event <= #(0) `false;
locknn_event_time = $time;
end
reg par64
, par64_old
;
reg par64_event
;
integer par64_event_time
; initial par64_event_time
= -500*`time_scale_multiplier;
integer par64_last_event
;
always @(par64) begin
par64_event = `true;
par64_event <= #(0) `false;
par64_event_time = $time;
end
reg req64nn
, req64nn_old
;
reg req64nn_event
;
integer req64nn_event_time
; initial req64nn_event_time
= -500*`time_scale_multiplier;
integer req64nn_last_event
;
always @(req64nn) begin
req64nn_event = `true;
req64nn_event <= #(0) `false;
req64nn_event_time = $time;
end
reg ack64nn
, ack64nn_old
;
reg ack64nn_event
;
integer ack64nn_event_time
; initial ack64nn_event_time
= -500*`time_scale_multiplier;
integer ack64nn_last_event
;
always @(ack64nn) begin
ack64nn_event = `true;
ack64nn_event <= #(0) `false;
ack64nn_event_time = $time;
end
reg sbonn
, sbonn_old
;
reg sbonn_event
;
integer sbonn_event_time
; initial sbonn_event_time
= -500*`time_scale_multiplier;
integer sbonn_last_event
;
always @(sbonn) begin
sbonn_event = `true;
sbonn_event <= #(0) `false;
sbonn_event_time = $time;
end
reg sdone
, sdone_old
;
reg sdone_event
;
integer sdone_event_time
; initial sdone_event_time
= -500*`time_scale_multiplier;
integer sdone_last_event
;
always @(sdone) begin
sdone_event = `true;
sdone_event <= #(0) `false;
sdone_event_time = $time;
end
reg intann
, intann_old
;
reg intann_event
;
integer intann_event_time
; initial intann_event_time
= -500*`time_scale_multiplier;
integer intann_last_event
;
always @(intann) begin
intann_event = `true;
intann_event <= #(0) `false;
intann_event_time = $time;
end
reg intbnn
, intbnn_old
;
reg intbnn_event
;
integer intbnn_event_time
; initial intbnn_event_time
= -500*`time_scale_multiplier;
integer intbnn_last_event
;
always @(intbnn) begin
intbnn_event = `true;
intbnn_event <= #(0) `false;
intbnn_event_time = $time;
end
reg intcnn
, intcnn_old
;
reg intcnn_event
;
integer intcnn_event_time
; initial intcnn_event_time
= -500*`time_scale_multiplier;
integer intcnn_last_event
;
always @(intcnn) begin
intcnn_event = `true;
intcnn_event <= #(0) `false;
intcnn_event_time = $time;
end
reg intdnn
, intdnn_old
;
reg intdnn_event
;
integer intdnn_event_time
; initial intdnn_event_time
= -500*`time_scale_multiplier;
integer intdnn_last_event
;
always @(intdnn) begin
intdnn_event = `true;
intdnn_event <= #(0) `false;
intdnn_event_time = $time;
end
integer fm_event
;
endmodule // pcimonitor_fm_input
module pcimonitor_timing
;
function [31:0] calc_curve;
input [31:0] x, c2, c1, c0;
begin
calc_curve = c2*(lmcver.power(x,2))/100 + c1*x + c0;
end
endfunction
task get_timing;
inout [31:0] local_times_tcy_min_clk;
inout [31:0] local_times_tcy_max_clk;
inout [31:0] local_times_tpwh_min_clk;
inout [31:0] local_times_tpwh_max_clk;
inout [31:0] local_times_tpwl_min_clk;
inout [31:0] local_times_tpwl_max_clk;
inout [31:0] local_times_twd_clk;
inout [31:0] local_times_tcy_min_rstnn;
inout [31:0] local_times_tcy_max_rstnn;
inout [31:0] local_times_tpwh_min_rstnn;
inout [31:0] local_times_tpwh_max_rstnn;
inout [31:0] local_times_tpwl_min_rstnn;
inout [31:0] local_times_tpwl_max_rstnn;
inout [31:0] local_times_twd_rstnn;
inout [31:0] local_times_trs_ad_clk;
inout [31:0] local_times_trh_ad_clk;
inout [31:0] local_times_twd_ad_63;
inout [31:0] local_times_twd_ad_62;
inout [31:0] local_times_twd_ad_61;
inout [31:0] local_times_twd_ad_60;
inout [31:0] local_times_twd_ad_59;
inout [31:0] local_times_twd_ad_58;
inout [31:0] local_times_twd_ad_57;
inout [31:0] local_times_twd_ad_56;
inout [31:0] local_times_twd_ad_55;
inout [31:0] local_times_twd_ad_54;
inout [31:0] local_times_twd_ad_53;
inout [31:0] local_times_twd_ad_52;
inout [31:0] local_times_twd_ad_51;
inout [31:0] local_times_twd_ad_50;
inout [31:0] local_times_twd_ad_49;
inout [31:0] local_times_twd_ad_48;
inout [31:0] local_times_twd_ad_47;
inout [31:0] local_times_twd_ad_46;
inout [31:0] local_times_twd_ad_45;
inout [31:0] local_times_twd_ad_44;
inout [31:0] local_times_twd_ad_43;
inout [31:0] local_times_twd_ad_42;
inout [31:0] local_times_twd_ad_41;
inout [31:0] local_times_twd_ad_40;
inout [31:0] local_times_twd_ad_39;
inout [31:0] local_times_twd_ad_38;
inout [31:0] local_times_twd_ad_37;
inout [31:0] local_times_twd_ad_36;
inout [31:0] local_times_twd_ad_35;
inout [31:0] local_times_twd_ad_34;
inout [31:0] local_times_twd_ad_33;
inout [31:0] local_times_twd_ad_32;
inout [31:0] local_times_twd_ad_31;
inout [31:0] local_times_twd_ad_30;
inout [31:0] local_times_twd_ad_29;
inout [31:0] local_times_twd_ad_28;
inout [31:0] local_times_twd_ad_27;
inout [31:0] local_times_twd_ad_26;
inout [31:0] local_times_twd_ad_25;
inout [31:0] local_times_twd_ad_24;
inout [31:0] local_times_twd_ad_23;
inout [31:0] local_times_twd_ad_22;
inout [31:0] local_times_twd_ad_21;
inout [31:0] local_times_twd_ad_20;
inout [31:0] local_times_twd_ad_19;
inout [31:0] local_times_twd_ad_18;
inout [31:0] local_times_twd_ad_17;
inout [31:0] local_times_twd_ad_16;
inout [31:0] local_times_twd_ad_15;
inout [31:0] local_times_twd_ad_14;
inout [31:0] local_times_twd_ad_13;
inout [31:0] local_times_twd_ad_12;
inout [31:0] local_times_twd_ad_11;
inout [31:0] local_times_twd_ad_10;
inout [31:0] local_times_twd_ad_9;
inout [31:0] local_times_twd_ad_8;
inout [31:0] local_times_twd_ad_7;
inout [31:0] local_times_twd_ad_6;
inout [31:0] local_times_twd_ad_5;
inout [31:0] local_times_twd_ad_4;
inout [31:0] local_times_twd_ad_3;
inout [31:0] local_times_twd_ad_2;
inout [31:0] local_times_twd_ad_1;
inout [31:0] local_times_twd_ad_0;
inout [31:0] local_times_tpr_clk_ad_0;
inout [31:0] local_times_tpr_clk_ad_1;
inout [31:0] local_times_tpr_clk_ad_x;
inout [31:0] local_times_tpr_clk_ad_z;
inout [31:0] local_times_tld_ad_63;
inout [31:0] local_times_tld_ad_62;
inout [31:0] local_times_tld_ad_61;
inout [31:0] local_times_tld_ad_60;
inout [31:0] local_times_tld_ad_59;
inout [31:0] local_times_tld_ad_58;
inout [31:0] local_times_tld_ad_57;
inout [31:0] local_times_tld_ad_56;
inout [31:0] local_times_tld_ad_55;
inout [31:0] local_times_tld_ad_54;
inout [31:0] local_times_tld_ad_53;
inout [31:0] local_times_tld_ad_52;
inout [31:0] local_times_tld_ad_51;
inout [31:0] local_times_tld_ad_50;
inout [31:0] local_times_tld_ad_49;
inout [31:0] local_times_tld_ad_48;
inout [31:0] local_times_tld_ad_47;
inout [31:0] local_times_tld_ad_46;
inout [31:0] local_times_tld_ad_45;
inout [31:0] local_times_tld_ad_44;
inout [31:0] local_times_tld_ad_43;
inout [31:0] local_times_tld_ad_42;
inout [31:0] local_times_tld_ad_41;
inout [31:0] local_times_tld_ad_40;
inout [31:0] local_times_tld_ad_39;
inout [31:0] local_times_tld_ad_38;
inout [31:0] local_times_tld_ad_37;
inout [31:0] local_times_tld_ad_36;
inout [31:0] local_times_tld_ad_35;
inout [31:0] local_times_tld_ad_34;
inout [31:0] local_times_tld_ad_33;
inout [31:0] local_times_tld_ad_32;
inout [31:0] local_times_tld_ad_31;
inout [31:0] local_times_tld_ad_30;
inout [31:0] local_times_tld_ad_29;
inout [31:0] local_times_tld_ad_28;
inout [31:0] local_times_tld_ad_27;
inout [31:0] local_times_tld_ad_26;
inout [31:0] local_times_tld_ad_25;
inout [31:0] local_times_tld_ad_24;
inout [31:0] local_times_tld_ad_23;
inout [31:0] local_times_tld_ad_22;
inout [31:0] local_times_tld_ad_21;
inout [31:0] local_times_tld_ad_20;
inout [31:0] local_times_tld_ad_19;
inout [31:0] local_times_tld_ad_18;
inout [31:0] local_times_tld_ad_17;
inout [31:0] local_times_tld_ad_16;
inout [31:0] local_times_tld_ad_15;
inout [31:0] local_times_tld_ad_14;
inout [31:0] local_times_tld_ad_13;
inout [31:0] local_times_tld_ad_12;
inout [31:0] local_times_tld_ad_11;
inout [31:0] local_times_tld_ad_10;
inout [31:0] local_times_tld_ad_9;
inout [31:0] local_times_tld_ad_8;
inout [31:0] local_times_tld_ad_7;
inout [31:0] local_times_tld_ad_6;
inout [31:0] local_times_tld_ad_5;
inout [31:0] local_times_tld_ad_4;
inout [31:0] local_times_tld_ad_3;
inout [31:0] local_times_tld_ad_2;
inout [31:0] local_times_tld_ad_1;
inout [31:0] local_times_tld_ad_0;
inout [31:0] local_times_trs_cxbenn_clk;
inout [31:0] local_times_trh_cxbenn_clk;
inout [31:0] local_times_twd_cxbenn_7;
inout [31:0] local_times_twd_cxbenn_6;
inout [31:0] local_times_twd_cxbenn_5;
inout [31:0] local_times_twd_cxbenn_4;
inout [31:0] local_times_twd_cxbenn_3;
inout [31:0] local_times_twd_cxbenn_2;
inout [31:0] local_times_twd_cxbenn_1;
inout [31:0] local_times_twd_cxbenn_0;
inout [31:0] local_times_tpr_clk_cxbenn_0;
inout [31:0] local_times_tpr_clk_cxbenn_1;
inout [31:0] local_times_tpr_clk_cxbenn_x;
inout [31:0] local_times_tpr_clk_cxbenn_z;
inout [31:0] local_times_tld_cxbenn_7;
inout [31:0] local_times_tld_cxbenn_6;
inout [31:0] local_times_tld_cxbenn_5;
inout [31:0] local_times_tld_cxbenn_4;
inout [31:0] local_times_tld_cxbenn_3;
inout [31:0] local_times_tld_cxbenn_2;
inout [31:0] local_times_tld_cxbenn_1;
inout [31:0] local_times_tld_cxbenn_0;
inout [31:0] local_times_trs_par_clk;
inout [31:0] local_times_trh_par_clk;
inout [31:0] local_times_twd_par;
inout [31:0] local_times_tpr_clk_par_0;
inout [31:0] local_times_tpr_clk_par_1;
inout [31:0] local_times_tpr_clk_par_x;
inout [31:0] local_times_tpr_clk_par_z;
inout [31:0] local_times_tld_par;
inout [31:0] local_times_trs_framenn_clk;
inout [31:0] local_times_trh_framenn_clk;
inout [31:0] local_times_twd_framenn;
inout [31:0] local_times_trs_trdynn_clk;
inout [31:0] local_times_trh_trdynn_clk;
inout [31:0] local_times_twd_trdynn;
inout [31:0] local_times_trs_irdynn_clk;
inout [31:0] local_times_trh_irdynn_clk;
inout [31:0] local_times_twd_irdynn;
inout [31:0] local_times_trs_stopnn_clk;
inout [31:0] local_times_trh_stopnn_clk;
inout [31:0] local_times_twd_stopnn;
inout [31:0] local_times_trs_devselnn_clk;
inout [31:0] local_times_trh_devselnn_clk;
inout [31:0] local_times_twd_devselnn;
inout [31:0] local_times_trs_idsel_clk;
inout [31:0] local_times_trh_idsel_clk;
inout [31:0] local_times_twd_idsel_7;
inout [31:0] local_times_twd_idsel_6;
inout [31:0] local_times_twd_idsel_5;
inout [31:0] local_times_twd_idsel_4;
inout [31:0] local_times_twd_idsel_3;
inout [31:0] local_times_twd_idsel_2;
inout [31:0] local_times_twd_idsel_1;
inout [31:0] local_times_twd_idsel_0;
inout [31:0] local_times_trs_perrnn_clk;
inout [31:0] local_times_trh_perrnn_clk;
inout [31:0] local_times_twd_perrnn;
inout [31:0] local_times_trs_serrnn_clk;
inout [31:0] local_times_trh_serrnn_clk;
inout [31:0] local_times_twd_serrnn;
inout [31:0] local_times_trs_reqnn_clk;
inout [31:0] local_times_trh_reqnn_clk;
inout [31:0] local_times_twd_reqnn_7;
inout [31:0] local_times_twd_reqnn_6;
inout [31:0] local_times_twd_reqnn_5;
inout [31:0] local_times_twd_reqnn_4;
inout [31:0] local_times_twd_reqnn_3;
inout [31:0] local_times_twd_reqnn_2;
inout [31:0] local_times_twd_reqnn_1;
inout [31:0] local_times_twd_reqnn_0;
inout [31:0] local_times_trs_gntnn_clk;
inout [31:0] local_times_trh_gntnn_clk;
inout [31:0] local_times_twd_gntnn_7;
inout [31:0] local_times_twd_gntnn_6;
inout [31:0] local_times_twd_gntnn_5;
inout [31:0] local_times_twd_gntnn_4;
inout [31:0] local_times_twd_gntnn_3;
inout [31:0] local_times_twd_gntnn_2;
inout [31:0] local_times_twd_gntnn_1;
inout [31:0] local_times_twd_gntnn_0;
inout [31:0] local_times_tpr_clk_gntnn_0;
inout [31:0] local_times_tpr_clk_gntnn_1;
inout [31:0] local_times_tpr_clk_gntnn_x;
This page: |
Created: | Thu Aug 19 11:57:37 1999 |
| From: |
../../../sparc_v8/system/lmc/rtl/pcimonitor_timing.v
|