//
// Copyright Notice and Proprietary Information
//
// Copyright (C) 1992 - 1995 Synopsys, Inc. All rights reserved. This Software
// and manual are owned by Synopsys, Inc., and may be used only as authorized
// in the license agreement controlling such use. No part of this publication
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// electronic, mechanical, manual, optical, or otherwise, without prior written
// permission of Synopsys, Inc., or as expressly provided by the license agreement.
//
// Destination Control Statement
//
// All technical data contained in this publication is subject to the export
// control laws of the United States of America. Disclosure to nationals of other
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// responsibility to determine the applicable regulations and to comply with them.
//
// Disclaimer
//
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// to this material, including, but not limited to, the implied warranties of
// merchantability and fitness for a particular purpose.
//
// Synopsys, Inc., reserves the right to make changes without further notice to
// the products described herein. Synopsys, Inc. does not assume any liability
// arising out of the application or use of any product or circuit described
// herein. The Synopsys products described herein are not authorized for use as
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//
`lmv_timescale
`define max_delay_index 256 // Maximum index used by set_delay
//--- VERGEN Version 8.0 ---
![[Up: pcislave_fm model_times]](v2html-up.gif)
module pcislave_times
;
integer trs_pad_pclk; initial trs_pad_pclk = 0;
integer trh_pad_pclk; initial trh_pad_pclk = 0;
integer twd_pad[31:0];
initial begin
twd_pad[31] = 0;
twd_pad[30] = 0;
twd_pad[29] = 0;
twd_pad[28] = 0;
twd_pad[27] = 0;
twd_pad[26] = 0;
twd_pad[25] = 0;
twd_pad[24] = 0;
twd_pad[23] = 0;
twd_pad[22] = 0;
twd_pad[21] = 0;
twd_pad[20] = 0;
twd_pad[19] = 0;
twd_pad[18] = 0;
twd_pad[17] = 0;
twd_pad[16] = 0;
twd_pad[15] = 0;
twd_pad[14] = 0;
twd_pad[13] = 0;
twd_pad[12] = 0;
twd_pad[11] = 0;
twd_pad[10] = 0;
twd_pad[9] = 0;
twd_pad[8] = 0;
twd_pad[7] = 0;
twd_pad[6] = 0;
twd_pad[5] = 0;
twd_pad[4] = 0;
twd_pad[3] = 0;
twd_pad[2] = 0;
twd_pad[1] = 0;
twd_pad[0] = 0;
end
reg [127:0] tpr_pclk_pad;
initial begin
tpr_pclk_pad = 128'b0;
end
integer tld_pad[31:0];
initial begin
tld_pad[31] = 0;
tld_pad[30] = 0;
tld_pad[29] = 0;
tld_pad[28] = 0;
tld_pad[27] = 0;
tld_pad[26] = 0;
tld_pad[25] = 0;
tld_pad[24] = 0;
tld_pad[23] = 0;
tld_pad[22] = 0;
tld_pad[21] = 0;
tld_pad[20] = 0;
tld_pad[19] = 0;
tld_pad[18] = 0;
tld_pad[17] = 0;
tld_pad[16] = 0;
tld_pad[15] = 0;
tld_pad[14] = 0;
tld_pad[13] = 0;
tld_pad[12] = 0;
tld_pad[11] = 0;
tld_pad[10] = 0;
tld_pad[9] = 0;
tld_pad[8] = 0;
tld_pad[7] = 0;
tld_pad[6] = 0;
tld_pad[5] = 0;
tld_pad[4] = 0;
tld_pad[3] = 0;
tld_pad[2] = 0;
tld_pad[1] = 0;
tld_pad[0] = 0;
end
integer trs_pcxbenn_pclk; initial trs_pcxbenn_pclk = 0;
integer trh_pcxbenn_pclk; initial trh_pcxbenn_pclk = 0;
integer twd_pcxbenn[3:0];
initial begin
twd_pcxbenn[3] = 0;
twd_pcxbenn[2] = 0;
twd_pcxbenn[1] = 0;
twd_pcxbenn[0] = 0;
end
integer trs_ppar_pclk; initial trs_ppar_pclk = 0;
integer trh_ppar_pclk; initial trh_ppar_pclk = 0;
integer twd_ppar; initial twd_ppar = 0;
reg [127:0] tpr_pclk_ppar;
initial begin
tpr_pclk_ppar = 128'b0;
end
integer tld_ppar; initial tld_ppar = 0;
integer trs_pframenn_pclk; initial trs_pframenn_pclk = 0;
integer trh_pframenn_pclk; initial trh_pframenn_pclk = 0;
integer twd_pframenn; initial twd_pframenn = 0;
integer trs_ptrdynn_pclk; initial trs_ptrdynn_pclk = 0;
integer trh_ptrdynn_pclk; initial trh_ptrdynn_pclk = 0;
integer twd_ptrdynn; initial twd_ptrdynn = 0;
reg [127:0] tpr_pclk_ptrdynn;
initial begin
tpr_pclk_ptrdynn = 128'b0;
end
integer tld_ptrdynn; initial tld_ptrdynn = 0;
integer trs_pirdynn_pclk; initial trs_pirdynn_pclk = 0;
integer trh_pirdynn_pclk; initial trh_pirdynn_pclk = 0;
integer twd_pirdynn; initial twd_pirdynn = 0;
integer trs_pstopnn_pclk; initial trs_pstopnn_pclk = 0;
integer trh_pstopnn_pclk; initial trh_pstopnn_pclk = 0;
integer twd_pstopnn; initial twd_pstopnn = 0;
reg [127:0] tpr_pclk_pstopnn;
initial begin
tpr_pclk_pstopnn = 128'b0;
end
integer tld_pstopnn; initial tld_pstopnn = 0;
reg [127:0] tpr_pclk_pdevselnn;
initial begin
tpr_pclk_pdevselnn = 128'b0;
end
integer tld_pdevselnn; initial tld_pdevselnn = 0;
integer trs_pidsel_pclk; initial trs_pidsel_pclk = 0;
integer trh_pidsel_pclk; initial trh_pidsel_pclk = 0;
integer twd_pidsel; initial twd_pidsel = 0;
integer trs_psbonn_pclk; initial trs_psbonn_pclk = 0;
integer trh_psbonn_pclk; initial trh_psbonn_pclk = 0;
integer twd_psbonn; initial twd_psbonn = 0;
integer trs_psdone_pclk; initial trs_psdone_pclk = 0;
integer trh_psdone_pclk; initial trh_psdone_pclk = 0;
integer twd_psdone; initial twd_psdone = 0;
integer tcy_min_pclk; initial tcy_min_pclk = 0;
integer tcy_max_pclk; initial tcy_max_pclk = 0;
integer tpwh_min_pclk; initial tpwh_min_pclk = 0;
integer tpwh_max_pclk; initial tpwh_max_pclk = 0;
integer tpwl_min_pclk; initial tpwl_min_pclk = 0;
integer tpwl_max_pclk; initial tpwl_max_pclk = 0;
integer twd_pclk; initial twd_pclk = 0;
integer tcy_min_prstnn; initial tcy_min_prstnn = 0;
integer tcy_max_prstnn; initial tcy_max_prstnn = 0;
integer tpwh_min_prstnn; initial tpwh_min_prstnn = 0;
integer tpwh_max_prstnn; initial tpwh_max_prstnn = 0;
integer tpwl_min_prstnn; initial tpwl_min_prstnn = 0;
integer tpwl_max_prstnn; initial tpwl_max_prstnn = 0;
integer twd_prstnn; initial twd_prstnn = 0;
integer trs_pd_pclk; initial trs_pd_pclk = 0;
integer trh_pd_pclk; initial trh_pd_pclk = 0;
integer twd_pd[63:32];
initial begin
twd_pd[63] = 0;
twd_pd[62] = 0;
twd_pd[61] = 0;
twd_pd[60] = 0;
twd_pd[59] = 0;
twd_pd[58] = 0;
twd_pd[57] = 0;
twd_pd[56] = 0;
twd_pd[55] = 0;
twd_pd[54] = 0;
twd_pd[53] = 0;
twd_pd[52] = 0;
twd_pd[51] = 0;
twd_pd[50] = 0;
twd_pd[49] = 0;
twd_pd[48] = 0;
twd_pd[47] = 0;
twd_pd[46] = 0;
twd_pd[45] = 0;
twd_pd[44] = 0;
twd_pd[43] = 0;
twd_pd[42] = 0;
twd_pd[41] = 0;
twd_pd[40] = 0;
twd_pd[39] = 0;
twd_pd[38] = 0;
twd_pd[37] = 0;
twd_pd[36] = 0;
twd_pd[35] = 0;
twd_pd[34] = 0;
twd_pd[33] = 0;
twd_pd[32] = 0;
end
reg [127:0] tpr_pclk_pd;
initial begin
tpr_pclk_pd = 128'b0;
end
integer tld_pd[63:32];
initial begin
tld_pd[63] = 0;
tld_pd[62] = 0;
tld_pd[61] = 0;
tld_pd[60] = 0;
tld_pd[59] = 0;
tld_pd[58] = 0;
tld_pd[57] = 0;
tld_pd[56] = 0;
tld_pd[55] = 0;
tld_pd[54] = 0;
tld_pd[53] = 0;
tld_pd[52] = 0;
tld_pd[51] = 0;
tld_pd[50] = 0;
tld_pd[49] = 0;
tld_pd[48] = 0;
tld_pd[47] = 0;
tld_pd[46] = 0;
tld_pd[45] = 0;
tld_pd[44] = 0;
tld_pd[43] = 0;
tld_pd[42] = 0;
tld_pd[41] = 0;
tld_pd[40] = 0;
tld_pd[39] = 0;
tld_pd[38] = 0;
tld_pd[37] = 0;
tld_pd[36] = 0;
tld_pd[35] = 0;
tld_pd[34] = 0;
tld_pd[33] = 0;
tld_pd[32] = 0;
end
integer trs_pbenn_pclk; initial trs_pbenn_pclk = 0;
integer trh_pbenn_pclk; initial trh_pbenn_pclk = 0;
integer twd_pbenn[7:4];
initial begin
twd_pbenn[7] = 0;
twd_pbenn[6] = 0;
twd_pbenn[5] = 0;
twd_pbenn[4] = 0;
end
integer trs_ppar64_pclk; initial trs_ppar64_pclk = 0;
integer trh_ppar64_pclk; initial trh_ppar64_pclk = 0;
integer twd_ppar64; initial twd_ppar64 = 0;
reg [127:0] tpr_pclk_ppar64;
initial begin
tpr_pclk_ppar64 = 128'b0;
end
integer tld_ppar64; initial tld_ppar64 = 0;
integer trs_preq64nn_pclk; initial trs_preq64nn_pclk = 0;
integer trh_preq64nn_pclk; initial trh_preq64nn_pclk = 0;
integer twd_preq64nn; initial twd_preq64nn = 0;
reg [127:0] tpr_pclk_pack64nn;
initial begin
tpr_pclk_pack64nn = 128'b0;
end
integer tld_pack64nn; initial tld_pack64nn = 0;
integer trs_plocknn_pclk; initial trs_plocknn_pclk = 0;
integer trh_plocknn_pclk; initial trh_plocknn_pclk = 0;
integer twd_plocknn; initial twd_plocknn = 0;
reg [127:0] tpr_pclk_pperrnn;
initial begin
tpr_pclk_pperrnn = 128'b0;
end
integer tld_pperrnn; initial tld_pperrnn = 0;
reg [127:0] tpr_pclk_pserrnn;
initial begin
tpr_pclk_pserrnn = 128'b0;
end
integer tld_pserrnn; initial tld_pserrnn = 0;
reg [127:0] tpd_prstnn_pad;
initial begin
tpd_prstnn_pad = 128'b0;
end
reg [127:0] tpd_prstnn_ppar;
initial begin
tpd_prstnn_ppar = 128'b0;
end
reg [127:0] tpd_prstnn_ptrdynn;
initial begin
tpd_prstnn_ptrdynn = 128'b0;
end
reg [127:0] tpd_prstnn_pstopnn;
initial begin
tpd_prstnn_pstopnn = 128'b0;
end
reg [127:0] tpd_prstnn_pdevselnn;
initial begin
tpd_prstnn_pdevselnn = 128'b0;
end
reg [127:0] tpd_prstnn_pd;
initial begin
tpd_prstnn_pd = 128'b0;
end
reg [127:0] tpd_prstnn_ppar64;
initial begin
tpd_prstnn_ppar64 = 128'b0;
end
reg [127:0] tpd_prstnn_pack64nn;
initial begin
tpd_prstnn_pack64nn = 128'b0;
end
reg [127:0] tpd_prstnn_pperrnn;
initial begin
tpd_prstnn_pperrnn = 128'b0;
end
reg [127:0] tpd_prstnn_pserrnn;
initial begin
tpd_prstnn_pserrnn = 128'b0;
end
endmodule // pcislave_times
module pcislave_flags;
integer option;
reg time_check, x_check, annotated;
integer debug_level, vlt, tmp, DF;
endmodule // pcislave_flags
module pcislave_fm_cntrl;
reg pad;
reg pad_in;
reg r_pad_pclk;
reg pcxbenn;
reg r_pcxbenn_pclk;
reg ppar;
reg ppar_in;
reg r_ppar_pclk;
reg pframenn;
reg r_pframenn_pclk;
reg ptrdynn;
reg ptrdynn_in;
reg r_ptrdynn_pclk;
reg pirdynn;
reg r_pirdynn_pclk;
reg pstopnn;
reg pstopnn_in;
reg r_pstopnn_pclk;
reg pdevselnn;
reg pidsel;
reg r_pidsel_pclk;
reg psbonn;
reg r_psbonn_pclk;
reg psdone;
reg r_psdone_pclk;
reg pclk;
reg ck_pclk;
reg prstnn;
reg ck_prstnn;
reg pd;
reg pd_in;
reg r_pd_pclk;
reg pbenn;
reg r_pbenn_pclk;
reg ppar64;
reg ppar64_in;
reg r_ppar64_pclk;
reg preq64nn;
reg r_preq64nn_pclk;
reg pack64nn;
reg plocknn;
reg r_plocknn_pclk;
reg pperrnn;
reg pserrnn;
integer tm_event;
endmodule // pcislave_fm_cntrl
module pcislave_fm_input;
reg [31:0] pad, pad_old;
reg pad_31,pad_30,pad_29,pad_28,pad_27,pad_26,pad_25,pad_24,pad_23,pad_22,pad_21,pad_20,pad_19,pad_18,pad_17,pad_16,pad_15,pad_14,pad_13,pad_12,pad_11,pad_10,pad_9,pad_8,pad_7,pad_6,pad_5,pad_4,pad_3,pad_2,pad_1,pad_0;
reg pad_event;
integer pad_event_time; initial pad_event_time = -500*`time_scale_multiplier;
integer pad_last_event;
always @(pad_31 or pad_30 or pad_29 or pad_28 or pad_27 or pad_26 or pad_25 or pad_24 or pad_23 or pad_22 or pad_21 or pad_20 or pad_19 or pad_18 or pad_17 or pad_16 or pad_15 or pad_14 or pad_13 or pad_12 or pad_11 or pad_10 or pad_9 or pad_8 or pad_7 or pad_6 or pad_5 or pad_4 or pad_3 or pad_2 or pad_1 or pad_0) begin
pad[31] = pad_31;
pad[30] = pad_30;
pad[29] = pad_29;
pad[28] = pad_28;
pad[27] = pad_27;
pad[26] = pad_26;
pad[25] = pad_25;
pad[24] = pad_24;
pad[23] = pad_23;
pad[22] = pad_22;
pad[21] = pad_21;
pad[20] = pad_20;
pad[19] = pad_19;
pad[18] = pad_18;
pad[17] = pad_17;
pad[16] = pad_16;
pad[15] = pad_15;
pad[14] = pad_14;
pad[13] = pad_13;
pad[12] = pad_12;
pad[11] = pad_11;
pad[10] = pad_10;
pad[9] = pad_9;
pad[8] = pad_8;
pad[7] = pad_7;
pad[6] = pad_6;
pad[5] = pad_5;
pad[4] = pad_4;
pad[3] = pad_3;
pad[2] = pad_2;
pad[1] = pad_1;
pad[0] = pad_0;
pad_event = `true;
pad_event <= #(0) `false;
pad_event_time = $time;
end
reg [3:0] pcxbenn, pcxbenn_old;
reg pcxbenn_3,pcxbenn_2,pcxbenn_1,pcxbenn_0;
reg pcxbenn_event;
integer pcxbenn_event_time; initial pcxbenn_event_time = -500*`time_scale_multiplier;
integer pcxbenn_last_event;
always @(pcxbenn_3 or pcxbenn_2 or pcxbenn_1 or pcxbenn_0) begin
pcxbenn[3] = pcxbenn_3;
pcxbenn[2] = pcxbenn_2;
pcxbenn[1] = pcxbenn_1;
pcxbenn[0] = pcxbenn_0;
pcxbenn_event = `true;
pcxbenn_event <= #(0) `false;
pcxbenn_event_time = $time;
end
reg ppar, ppar_old;
reg ppar_event;
integer ppar_event_time; initial ppar_event_time = -500*`time_scale_multiplier;
integer ppar_last_event;
always @(ppar) begin
ppar_event = `true;
ppar_event <= #(0) `false;
ppar_event_time = $time;
end
reg pframenn, pframenn_old;
reg pframenn_event;
integer pframenn_event_time; initial pframenn_event_time = -500*`time_scale_multiplier;
integer pframenn_last_event;
always @(pframenn) begin
pframenn_event = `true;
pframenn_event <= #(0) `false;
pframenn_event_time = $time;
end
reg ptrdynn, ptrdynn_old;
reg ptrdynn_event;
integer ptrdynn_event_time; initial ptrdynn_event_time = -500*`time_scale_multiplier;
integer ptrdynn_last_event;
always @(ptrdynn) begin
ptrdynn_event = `true;
ptrdynn_event <= #(0) `false;
ptrdynn_event_time = $time;
end
reg pirdynn, pirdynn_old;
reg pirdynn_event;
integer pirdynn_event_time; initial pirdynn_event_time = -500*`time_scale_multiplier;
integer pirdynn_last_event;
always @(pirdynn) begin
pirdynn_event = `true;
pirdynn_event <= #(0) `false;
pirdynn_event_time = $time;
end
reg pstopnn, pstopnn_old;
reg pstopnn_event;
integer pstopnn_event_time; initial pstopnn_event_time = -500*`time_scale_multiplier;
integer pstopnn_last_event;
always @(pstopnn) begin
pstopnn_event = `true;
pstopnn_event <= #(0) `false;
pstopnn_event_time = $time;
end
reg pidsel, pidsel_old;
reg pidsel_event;
integer pidsel_event_time; initial pidsel_event_time = -500*`time_scale_multiplier;
integer pidsel_last_event;
always @(pidsel) begin
pidsel_event = `true;
pidsel_event <= #(0) `false;
pidsel_event_time = $time;
end
reg psbonn, psbonn_old;
reg psbonn_event;
integer psbonn_event_time; initial psbonn_event_time = -500*`time_scale_multiplier;
integer psbonn_last_event;
always @(psbonn) begin
psbonn_event = `true;
psbonn_event <= #(0) `false;
psbonn_event_time = $time;
end
reg psdone, psdone_old;
reg psdone_event;
integer psdone_event_time; initial psdone_event_time = -500*`time_scale_multiplier;
integer psdone_last_event;
always @(psdone) begin
psdone_event = `true;
psdone_event <= #(0) `false;
psdone_event_time = $time;
end
reg pclk, pclk_old;
reg pclk_event;
integer pclk_event_time; initial pclk_event_time = -500*`time_scale_multiplier;
integer pclk_last_event;
always @(pclk) begin
pclk_event = `true;
pclk_event <= #(0) `false;
pclk_event_time = $time;
end
reg prstnn, prstnn_old;
reg prstnn_event;
integer prstnn_event_time; initial prstnn_event_time = -500*`time_scale_multiplier;
integer prstnn_last_event;
always @(prstnn) begin
prstnn_event = `true;
prstnn_event <= #(0) `false;
prstnn_event_time = $time;
end
reg [63:32] pd, pd_old;
reg pd_63,pd_62,pd_61,pd_60,pd_59,pd_58,pd_57,pd_56,pd_55,pd_54,pd_53,pd_52,pd_51,pd_50,pd_49,pd_48,pd_47,pd_46,pd_45,pd_44,pd_43,pd_42,pd_41,pd_40,pd_39,pd_38,pd_37,pd_36,pd_35,pd_34,pd_33,pd_32;
reg pd_event;
integer pd_event_time; initial pd_event_time = -500*`time_scale_multiplier;
integer pd_last_event;
always @(pd_63 or pd_62 or pd_61 or pd_60 or pd_59 or pd_58 or pd_57 or pd_56 or pd_55 or pd_54 or pd_53 or pd_52 or pd_51 or pd_50 or pd_49 or pd_48 or pd_47 or pd_46 or pd_45 or pd_44 or pd_43 or pd_42 or pd_41 or pd_40 or pd_39 or pd_38 or pd_37 or pd_36 or pd_35 or pd_34 or pd_33 or pd_32) begin
pd[63] = pd_63;
pd[62] = pd_62;
pd[61] = pd_61;
pd[60] = pd_60;
pd[59] = pd_59;
pd[58] = pd_58;
pd[57] = pd_57;
pd[56] = pd_56;
pd[55] = pd_55;
pd[54] = pd_54;
pd[53] = pd_53;
pd[52] = pd_52;
pd[51] = pd_51;
pd[50] = pd_50;
pd[49] = pd_49;
pd[48] = pd_48;
pd[47] = pd_47;
pd[46] = pd_46;
pd[45] = pd_45;
pd[44] = pd_44;
pd[43] = pd_43;
pd[42] = pd_42;
pd[41] = pd_41;
pd[40] = pd_40;
pd[39] = pd_39;
pd[38] = pd_38;
pd[37] = pd_37;
pd[36] = pd_36;
pd[35] = pd_35;
pd[34] = pd_34;
pd[33] = pd_33;
pd[32] = pd_32;
pd_event = `true;
pd_event <= #(0) `false;
pd_event_time = $time;
end
reg [7:4] pbenn, pbenn_old;
reg pbenn_7,pbenn_6,pbenn_5,pbenn_4;
reg pbenn_event;
integer pbenn_event_time; initial pbenn_event_time = -500*`time_scale_multiplier;
integer pbenn_last_event;
always @(pbenn_7 or pbenn_6 or pbenn_5 or pbenn_4) begin
pbenn[7] = pbenn_7;
pbenn[6] = pbenn_6;
pbenn[5] = pbenn_5;
pbenn[4] = pbenn_4;
pbenn_event = `true;
pbenn_event <= #(0) `false;
pbenn_event_time = $time;
end
reg ppar64, ppar64_old;
reg ppar64_event;
integer ppar64_event_time; initial ppar64_event_time = -500*`time_scale_multiplier;
integer ppar64_last_event;
always @(ppar64) begin
ppar64_event = `true;
ppar64_event <= #(0) `false;
ppar64_event_time = $time;
end
reg preq64nn, preq64nn_old;
reg preq64nn_event;
integer preq64nn_event_time; initial preq64nn_event_time = -500*`time_scale_multiplier;
integer preq64nn_last_event;
always @(preq64nn) begin
preq64nn_event = `true;
preq64nn_event <= #(0) `false;
preq64nn_event_time = $time;
end
reg plocknn, plocknn_old;
reg plocknn_event;
integer plocknn_event_time; initial plocknn_event_time = -500*`time_scale_multiplier;
integer plocknn_last_event;
always @(plocknn) begin
plocknn_event = `true;
plocknn_event <= #(0) `false;
plocknn_event_time = $time;
end
integer fm_event;
endmodule // pcislave_fm_input
module pcislave_fm_data_out;
reg strobe;
reg ready;
endmodule
//**--**--**--**--**--**--**--**-- MODELER DECLARATION BEGIN
`define set_addr_cmd 15
`define get_addr_cmd 16
//**--**--**--**--**--**--**--**-- MODELER DECLARATION END
//--**--**--**--**--**--**--**--**-- RELEASE-DEPENDENT CODE BEGIN
//-- Code Release Number: 8 // Do not delete this line!
//--**--**--**--**--**--**--**--**-- RELEASE-DEPENDENT CODE END
module pcislave_timing;
parameter fm_data_in1 = 1;
parameter fm_data_in2 = 6118;
parameter incode1 = 1;
parameter incode2 = 32;
parameter instrobe = 33;
parameter inctype1 = 34;
parameter inctype2 = 65;
parameter invalue_vector1 = 66;
parameter invalue_vector2 = 129;
parameter invalue_boolean = 130;
parameter invalue1 = 131;
parameter invalue2 = 162;
parameter indelay_index1 = 163;
parameter indelay_index2 = 194;
parameter indelay1 = 195;
parameter indelay2 = 226;
parameter inrequest_limit1 = 227;
parameter inrequest_limit2 = 258;
parameter indecode1 = 259;
parameter indecode2 = 290;
parameter incycles1 = 291;
parameter incycles2 = 322;
parameter intvalue1 = 323;
parameter intvalue2 = 354;
parameter inmessage1 = 355;
parameter inmessage2 = 1378;
parameter inmlevel1 = 1379;
parameter inmlevel2 = 1410;
parameter infunction_name1 = 1411;
parameter infunction_name2 = 2434;
parameter instype1 = 2435;
parameter instype2 = 2466;
parameter inobject_name1 = 2467;
parameter inobject_name2 = 2498;
parameter inobject_value1 = 2499;
parameter inobject_value2 = 2562;
parameter indelay_val1 = 2563;
parameter indelay_val2 = 2594;
parameter inmtype1 = 2595;
parameter inmtype2 = 2626;
parameter insaddr1 = 2627;
parameter insaddr2 = 2690;
parameter inexpected_data1 = 2691;
parameter inexpected_data2 = 2754;
parameter indfile1 = 2755;
parameter indfile2 = 3778;
parameter inflush_f = 3779;
parameter instart_addr1 = 3780;
parameter instart_addr2 = 3843;
parameter inend_addr1 = 3844;
parameter inend_addr2 = 3907;
parameter intarget_id1 = 3908;
parameter intarget_id2 = 3939;
parameter inmsg1 = 3940;
parameter inmsg2 = 4963;
parameter inbuffer_f = 4964;
parameter innotify_f = 4965;
parameter inreturn_data_f = 4966;
parameter innode_name1 = 4967;
parameter innode_name2 = 5990;
parameter innode_value1 = 5991;
parameter innode_value2 = 6054;
parameter innode_mask1 = 6055;
parameter innode_mask2 = 6118;
//type set_types is
parameter mpin = 0;
parameter mbus = 1;
parameter mregister = 2;
//type object_name_types is
parameter pad_bus = 3;
parameter pad_0 = 4;
parameter pad_1 = 5;
parameter pad_2 = 6;
parameter pad_3 = 7;
parameter pad_4 = 8;
parameter pad_5 = 9;
parameter pad_6 = 10;
parameter pad_7 = 11;
parameter pad_8 = 12;
parameter pad_9 = 13;
parameter pad_10 = 14;
parameter pad_11 = 15;
parameter pad_12 = 16;
parameter pad_13 = 17;
parameter pad_14 = 18;
parameter pad_15 = 19;
parameter pad_16 = 20;
parameter pad_17 = 21;
parameter pad_18 = 22;
parameter pad_19 = 23;
parameter pad_20 = 24;
parameter pad_21 = 25;
parameter pad_22 = 26;
parameter pad_23 = 27;
parameter pad_24 = 28;
parameter pad_25 = 29;
parameter pad_26 = 30;
parameter pad_27 = 31;
parameter pad_28 = 32;
parameter pad_29 = 33;
parameter pad_30 = 34;
parameter pad_31 = 35;
parameter pcxbenn_bus = 36;
parameter pcxbenn_0 = 37;
parameter pcxbenn_1 = 38;
parameter pcxbenn_2 = 39;
parameter pcxbenn_3 = 40;
parameter ppar_pin = 41;
parameter pframenn_pin = 42;
parameter ptrdynn_pin = 43;
parameter pirdynn_pin = 44;
parameter pstopnn_pin = 45;
parameter pdevselnn_pin = 46;
parameter pidsel_pin = 47;
parameter psbonn_pin = 48;
parameter psdone_pin = 49;
parameter pclk_pin = 50;
parameter prstnn_pin = 51;
parameter pd_bus = 52;
parameter pd_32 = 53;
parameter pd_33 = 54;
parameter pd_34 = 55;
parameter pd_35 = 56;
parameter pd_36 = 57;
parameter pd_37 = 58;
parameter pd_38 = 59;
parameter pd_39 = 60;
parameter pd_40 = 61;
parameter pd_41 = 62;
parameter pd_42 = 63;
parameter pd_43 = 64;
parameter pd_44 = 65;
parameter pd_45 = 66;
parameter pd_46 = 67;
parameter pd_47 = 68;
parameter pd_48 = 69;
parameter pd_49 = 70;
parameter pd_50 = 71;
parameter pd_51 = 72;
parameter pd_52 = 73;
parameter pd_53 = 74;
parameter pd_54 = 75;
parameter pd_55 = 76;
parameter pd_56 = 77;
parameter pd_57 = 78;
parameter pd_58 = 79;
parameter pd_59 = 80;
parameter pd_60 = 81;
parameter pd_61 = 82;
parameter pd_62 = 83;
parameter pd_63 = 84;
parameter pbenn_bus = 85;
parameter pbenn_4 = 86;
parameter pbenn_5 = 87;
parameter pbenn_6 = 88;
parameter pbenn_7 = 89;
parameter ppar64_pin = 90;
parameter preq64nn_pin = 91;
parameter pack64nn_pin = 92;
parameter plocknn_pin = 93;
parameter pperrnn_pin = 94;
parameter pserrnn_pin = 95;
//type config_types is
parameter transfer_limit = 96;
parameter abort_limit = 97;
parameter termination_style = 98;
parameter pci_error = 99;
parameter decode = 100;
parameter delays = 101;
parameter dev_id = 102;
parameter ven_id = 103;
parameter rev_id = 104;
parameter h_type = 105;
parameter cls_code = 106;
parameter mem_l_0 = 107;
parameter mem_u_0 = 108;
parameter mem_l_1 = 109;
parameter mem_u_1 = 110;
parameter mem_l_2 = 111;
parameter mem_u_2 = 112;
parameter io_l_0 = 113;
parameter io_u_0 = 114;
parameter io_l_1 = 115;
parameter io_u_1 = 116;
parameter io_l_2 = 117;
parameter io_u_2 = 118;
parameter c_line_size = 119;
parameter addr_64 = 120;
parameter data_64 = 121;
parameter int_ack = 122;
parameter int_ack_vector = 123;
parameter type1_access = 124;
//type mem_types is
parameter mem = 124;
parameter io = 125;
parameter cfg = 126;
parameter all_delays = -1; // For config(delays,-1,0);
reg [1:1024] reg_init; initial reg_init = 1024'bx;
reg [fm_data_in1:fm_data_in2] fm_data_in_init;
initial begin
fm_data_in_init[incode1:incode2] = `idle_cmd;
fm_data_in_init[instrobe] = 1'b0;
fm_data_in_init[inctype1:inctype2] = 0;
fm_data_in_init[invalue_vector1:invalue_vector2] = reg_init[1:64];
fm_data_in_init[invalue_boolean] = `false;
fm_data_in_init[invalue1:invalue2] = 0;
fm_data_in_init[indelay_index1:indelay_index2] = 0;
fm_data_in_init[indelay1:indelay2] = 0;
fm_data_in_init[inrequest_limit1:inrequest_limit2] = 0;
fm_data_in_init[indecode1:indecode2] = 0;
fm_data_in_init[incycles1:incycles2] = 0;
fm_data_in_init[intvalue1:intvalue2] = 0;
fm_data_in_init[inmessage1:inmessage2] = reg_init[1:1024];
fm_data_in_init[inmlevel1:inmlevel2] = 0;
fm_data_in_init[infunction_name1:infunction_name2] = reg_init[1:1024];
fm_data_in_init[instype1:instype2] = 0;
fm_data_in_init[inobject_name1:inobject_name2] = 0;
fm_data_in_init[inobject_value1:inobject_value2] = reg_init[1:64];
fm_data_in_init[indelay_val1:indelay_val2] = 0;
fm_data_in_init[inmtype1:inmtype2] = 0;
fm_data_in_init[insaddr1:insaddr2] = reg_init[1:64];
fm_data_in_init[inexpected_data1:inexpected_data2] = reg_init[1:64];
fm_data_in_init[indfile1:indfile2] = reg_init[1:1024];
fm_data_in_init[inflush_f] = `false;
fm_data_in_init[instart_addr1:instart_addr2] = reg_init[1:64];
fm_data_in_init[inend_addr1:inend_addr2] = reg_init[1:64];
fm_data_in_init[intarget_id1:intarget_id2] = 0;
fm_data_in_init[inmsg1:inmsg2] = reg_init[1:1024];
fm_data_in_init[inbuffer_f] = `false;
fm_data_in_init[innotify_f] = `false;
fm_data_in_init[inreturn_data_f] = `false;
end // fm_data_in_init
reg [fm_data_in1:fm_data_in2] wk_cmd; initial wk_cmd = fm_data_in_init; // fm_data_in
task pcl_to_boolean;
output ret_val;
input [1:`token_size*8] inline;
output valid_f;
input [31:0] msg_level; // default = no_msg;
input [1:13*8] cmd_name; // default = "NO NAME GIVEN"
reg [1:`token_size*8] tmp_inline;
begin
valid_f = `true;
tmp_inline = inline;
case (tmp_inline)
"false","`false" : ret_val = 1'b0;
"true","`true" : ret_val = 1'b1;
default : begin
syntax_warn(cmd_name,tmp_inline,msg_level);
valid_f = `false;
end
endcase
end
endtask // pcl_to_boolean
task bfm_msg;
input [1 : `token_size*8*10] message;
input [31 : 0] message_level;
input [31 : 0] msg_level;
integer sev_level;
integer note;
begin
note = 100;
sev_level = note;
if (message_level === `warnings) begin
sev_level = `warnings;
end // if
case (sev_level)
note : begin
if (msg_level >= message_level) begin
$display("NOTE at %0t from %m", $time);
$display(" \" %0s\" ", message);
end // if
end
`warnings : begin
if (msg_level >= message_level) begin
$display("WARNING at %0t from %m", $time);
$display(" \" %0s\" ", message);
end // if
end
endcase
end
endtask // bfm_msg
task syntax_warn;
input [1 : 32*8] cmd_name;
input [1:`token_size*8] token;
input [31 : 0] msg_level; // default = `warnings
begin
if (msg_level >= `warnings) begin
$display("WARNING at %0t from %m", $time);
$display(" \"Syntax Error in %0s command: Illegal Value is %0s", cmd_name, token);
end // if
end
endtask // syntax_warn
function is_command;
input [1 : `token_size*8] inline;
begin
case (inline)
"configure" : is_command = `true;
"configure_delay" : is_command = `true;
"request" : is_command = `true;
"idle" : is_command = `true;
"trigger" : is_command = `true;
"wait_on" : is_command = `true;
"print_msg" : is_command = `true;
"set_msg_level" : is_command = `true;
"call" : is_command = `true;
"func_beg" : is_command = `true;
"func_end" : is_command = `true;
"sequential" : is_command = `true;
"stop_sim" : is_command = `true;
"wait_on_node" : is_command = `true;
"open_buffer" : is_command = `true;
"close_buffer" : is_command = `true;
"set" : is_command = `true;
"set_addr" : is_command = `true;
"get" : is_command = `true;
"get_addr" : is_command = `true;
"reload" : is_command = `true;
"dump" : is_command = `true;
"remote" : is_command = `true;
| This page: |
Created: | Thu Aug 19 11:57:45 1999 |
| From: |
../../../sparc_v8/system/lmc/rtl/pcislave_timing.v
|