/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
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/* obligations, and limitations governing use of the contents of this file. */
/* */
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/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
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/* are trademarks or registered trademarks of SPARC International, Inc. in */
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/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)rightpads.v
***
****************************************************************************
****************************************************************************/
// @(#)rightpads.v 1.13 01/14/97
// Automatically generated from iopad_order rev 1.9 by mkiopads, rev 1.9
![[Up: iopads rightpads]](v2html-up.gif)
module rightpads
( // Pads listed in bottom-to-top order:
// vss_167, // vss
o_168, // rom_addr[18]
o_168_o,
// vdd_169, // vdd
// vss_170, // vss
o_171, // rom_addr[19]
o_171_o,
o_172, // rom_addr[20]
o_172_o,
o_173, // rom_addr[21]
o_173_o,
o_174, // rom_addr[22]
o_174_o,
// vdd_175, // vdd
// vss_176, // vss
o_177, // rom_addr[23]
o_177_o,
o_178, // rom_oe_l
o_178_o,
o_179, // rom_we_l
o_179_o,
o_180, // rom_cs_l
o_180_o,
// vdd_181, // vdd
// vss_182, // vss
o_183, // mc_memaddr[0]
o_183_o,
o_184, // mc_memaddr[1]
o_184_o,
o_185, // mc_memaddr[2]
o_185_o,
o_186, // mc_memaddr[3]
o_186_o,
// vdd2_187, // vdd
// vss2_188, // vss
o_189, // mc_memaddr[4]
o_189_o,
o_190, // mc_memaddr[5]
o_190_o,
o_191, // mc_memaddr[6]
o_191_o,
o_192, // mc_memaddr[7]
o_192_o,
// vdd_193, // vdd
// vss_194, // vss
o_195, // mc_memaddr[8]
o_195_o,
o_196, // mc_memaddr[9]
o_196_o,
o_197, // mc_memaddr[10]
o_197_o,
o_198, // mc_memaddr[11]
o_198_o,
// vdd_199, // vss
// vss_200, // vss
o_201, // mc_mwe_l
o_201_o,
o_202, // mc_cas_l[0]
o_202_o,
o_203, // mc_cas_l[1]
o_203_o,
o_204, // mc_cas_l[2]
o_204_o,
// vdd_205, // vdd
// vss_206, // vss
o_207, // mc_cas_l[3]
o_207_o,
o_208, // mc_ras_l[0]
o_208_o,
o_209, // mc_ras_l[1]
o_209_o,
o_210, // mc_ras_l[2]
o_210_o,
// vdd2_211, // vdd
// vss2_212, // vss
o_213, // mc_ras_l[3]
o_213_o,
o_214, // mc_ras_l[4]
o_214_o,
o_215, // mc_ras_l[5]
o_215_o,
o_216, // mc_ras_l[6]
o_216_o,
// vdd_217, // vdd
// vss_218, // vss
o_219, // mc_ras_l[7]
o_219_o,
o_220, // mc_moe_l
o_220_o,
i_tn_221, // tn
i_tn_221_i,
i_tn_221_po,
i_ns_222, // iiddtn
i_ns_222_i,
// vdd_223, // vdd
// vss_224, // vss
i_225, // simm32_sel
i_225_i,
// vdd_226, // vdd
i_td_227, // therm_d
i_td_227_i,
b_228, // b_mempar[0]
b_228_o,
b_228_i,
b_229, // b_mempar[1]
b_229_o,
b_229_i,
// vdd_230, // vdd
// vss_231, // vss
// vdd2_232, // vdd
b_mem_oen, // b_mem_oen
b_233, // b_memdata[0]
b_233_o,
b_233_i,
b_234, // b_memdata[1]
b_234_o,
b_234_i,
// vss2_235, // vss
b_236, // b_memdata[2]
b_236_o,
b_236_i,
b_237, // b_memdata[3]
b_237_o,
b_237_i,
b_238, // b_memdata[4]
b_238_o,
b_238_i,
b_239, // b_memdata[5]
b_239_o,
b_239_i,
// vss_240, // vss
// vdd_241, // vdd
b_242, // b_memdata[6]
b_242_o,
b_242_i,
b_243, // b_memdata[7]
b_243_o,
b_243_i,
b_244, // b_memdata[8]
b_244_o,
b_244_i,
// vss_245, // vss
// vss2_246, // vss
b_247, // b_memdata[9]
b_247_o,
b_247_i,
b_248, // b_memdata[10]
b_248_o,
b_248_i,
// vdd2_249, // vdd
b_250, // b_memdata[11]
b_250_o,
b_250_i,
// vdd_251, // vdd
b_252, // b_memdata[12]
b_252_o,
b_252_i,
b_253, // b_memdata[13]
b_253_o,
b_253_i,
// vss_254, // vss
bscan_clk_cap,
bscan_clk_upd,
w_input_tn,
bscan_shift,
bscan_sel_ff_out,
bscan_sel_ff_in,
pi_in,
scan_in,
po_out,
scan_out
) ;
output o_168 ; // rom_addr[18]
input o_168_o ;
output o_171 ; // rom_addr[19]
input o_171_o ;
output o_172 ; // rom_addr[20]
input o_172_o ;
output o_173 ; // rom_addr[21]
input o_173_o ;
output o_174 ; // rom_addr[22]
input o_174_o ;
output o_177 ; // rom_addr[23]
input o_177_o ;
output o_178 ; // rom_oe_l
input o_178_o ;
output o_179 ; // rom_we_l
input o_179_o ;
output o_180 ; // rom_cs_l
input o_180_o ;
output o_183 ; // mc_memaddr[0]
input o_183_o ;
output o_184 ; // mc_memaddr[1]
input o_184_o ;
output o_185 ; // mc_memaddr[2]
input o_185_o ;
output o_186 ; // mc_memaddr[3]
input o_186_o ;
output o_189 ; // mc_memaddr[4]
input o_189_o ;
output o_190 ; // mc_memaddr[5]
input o_190_o ;
output o_191 ; // mc_memaddr[6]
input o_191_o ;
output o_192 ; // mc_memaddr[7]
input o_192_o ;
output o_195 ; // mc_memaddr[8]
input o_195_o ;
output o_196 ; // mc_memaddr[9]
input o_196_o ;
output o_197 ; // mc_memaddr[10]
input o_197_o ;
output o_198 ; // mc_memaddr[11]
input o_198_o ;
output o_201 ; // mc_mwe_l
input o_201_o ;
output o_202 ; // mc_cas_l[0]
input o_202_o ;
output o_203 ; // mc_cas_l[1]
input o_203_o ;
output o_204 ; // mc_cas_l[2]
input o_204_o ;
output o_207 ; // mc_cas_l[3]
input o_207_o ;
output o_208 ; // mc_ras_l[0]
input o_208_o ;
output o_209 ; // mc_ras_l[1]
input o_209_o ;
output o_210 ; // mc_ras_l[2]
input o_210_o ;
output o_213 ; // mc_ras_l[3]
input o_213_o ;
output o_214 ; // mc_ras_l[4]
input o_214_o ;
output o_215 ; // mc_ras_l[5]
input o_215_o ;
output o_216 ; // mc_ras_l[6]
input o_216_o ;
output o_219 ; // mc_ras_l[7]
input o_219_o ;
output o_220 ; // mc_moe_l
input o_220_o ;
input i_tn_221 ; // tn
output i_tn_221_i ;
output i_tn_221_po ;
input i_ns_222 ; // iiddtn
output i_ns_222_i ;
input i_225 ; // simm32_sel
output i_225_i ;
input i_td_227 ; // therm_d
output i_td_227_i ;
inout b_228 ; // b_mempar[0]
input b_228_o ;
output b_228_i ;
inout b_229 ; // b_mempar[1]
input b_229_o ;
output b_229_i ;
input b_mem_oen ; // b_mem_oen
inout b_233 ; // b_memdata[0]
input b_233_o ;
output b_233_i ;
inout b_234 ; // b_memdata[1]
input b_234_o ;
output b_234_i ;
inout b_236 ; // b_memdata[2]
input b_236_o ;
output b_236_i ;
inout b_237 ; // b_memdata[3]
input b_237_o ;
output b_237_i ;
inout b_238 ; // b_memdata[4]
input b_238_o ;
output b_238_i ;
inout b_239 ; // b_memdata[5]
input b_239_o ;
output b_239_i ;
inout b_242 ; // b_memdata[6]
input b_242_o ;
output b_242_i ;
inout b_243 ; // b_memdata[7]
input b_243_o ;
output b_243_i ;
inout b_244 ; // b_memdata[8]
input b_244_o ;
output b_244_i ;
inout b_247 ; // b_memdata[9]
input b_247_o ;
output b_247_i ;
inout b_248 ; // b_memdata[10]
input b_248_o ;
output b_248_i ;
inout b_250 ; // b_memdata[11]
input b_250_o ;
output b_250_i ;
inout b_252 ; // b_memdata[12]
input b_252_o ;
output b_252_i ;
inout b_253 ; // b_memdata[13]
input b_253_o ;
output b_253_i ;
input bscan_clk_cap ;
input bscan_clk_upd ;
input w_input_tn ;
input bscan_shift ;
input bscan_sel_ff_out ;
input bscan_sel_ff_in ;
input pi_in ;
input scan_in ;
output po_out ;
output scan_out ;
// Dummy pad vss_167 ()
// vss
// Output pad for o_168 (rom_addr[18])
MEM_OUT o_168_pad(
.OT (o_168_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (scan_in),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_168_so),
.X (o_168)
) ;
// Dummy pad vdd_169 ()
// vdd
// Dummy pad vss_170 ()
// vss
// Output pad for o_171 (rom_addr[19])
MEM_OUT o_171_pad(
.OT (o_171_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_168_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_171_so),
.X (o_171)
) ;
// Output pad for o_172 (rom_addr[20])
MEM_OUT o_172_pad(
.OT (o_172_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_171_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_172_so),
.X (o_172)
) ;
// Output pad for o_173 (rom_addr[21])
MEM_OUT o_173_pad(
.OT (o_173_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_172_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_173_so),
.X (o_173)
) ;
// Output pad for o_174 (rom_addr[22])
MEM_OUT o_174_pad(
.OT (o_174_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_173_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_174_so),
.X (o_174)
) ;
// Dummy pad vdd_175 ()
// vdd
// Dummy pad vss_176 ()
// vss
// Output pad for o_177 (rom_addr[23])
MEM_OUT o_177_pad(
.OT (o_177_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_174_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_177_so),
.X (o_177)
) ;
// Output pad for o_178 (rom_oe_l)
MEM_OUT o_178_pad(
.OT (o_178_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_177_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_178_so),
.X (o_178)
) ;
// Output pad for o_179 (rom_we_l)
MEM_OUT o_179_pad(
.OT (o_179_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_178_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_179_so),
.X (o_179)
) ;
// Output pad for o_180 (rom_cs_l)
MEM_OUT o_180_pad(
.OT (o_180_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_179_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_180_so),
.X (o_180)
) ;
// Dummy pad vdd_181 ()
// vdd
// Dummy pad vss_182 ()
// vss
// Output pad for o_183 (mc_memaddr[0])
MEM_OUT o_183_pad(
.OT (o_183_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_180_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_183_so),
.X (o_183)
) ;
// Output pad for o_184 (mc_memaddr[1])
MEM_OUT o_184_pad(
.OT (o_184_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_183_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_184_so),
.X (o_184)
) ;
// Output pad for o_185 (mc_memaddr[2])
MEM_OUT o_185_pad(
.OT (o_185_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_184_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_185_so),
.X (o_185)
) ;
// Output pad for o_186 (mc_memaddr[3])
MEM_OUT o_186_pad(
.OT (o_186_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_185_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_186_so),
.X (o_186)
) ;
// Dummy pad vdd2_187 ()
// vdd
// Dummy pad vss2_188 ()
// vss
// Output pad for o_189 (mc_memaddr[4])
MEM_OUT o_189_pad(
.OT (o_189_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_186_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_189_so),
.X (o_189)
) ;
// Output pad for o_190 (mc_memaddr[5])
MEM_OUT o_190_pad(
.OT (o_190_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_189_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_190_so),
.X (o_190)
) ;
// Output pad for o_191 (mc_memaddr[6])
MEM_OUT o_191_pad(
.OT (o_191_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_190_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_191_so),
.X (o_191)
) ;
// Output pad for o_192 (mc_memaddr[7])
MEM_OUT o_192_pad(
.OT (o_192_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_191_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_192_so),
.X (o_192)
) ;
// Dummy pad vdd_193 ()
// vdd
// Dummy pad vss_194 ()
// vss
// Output pad for o_195 (mc_memaddr[8])
MEM_OUT o_195_pad(
.OT (o_195_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_192_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_195_so),
.X (o_195)
) ;
// Output pad for o_196 (mc_memaddr[9])
MEM_OUT o_196_pad(
.OT (o_196_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_195_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_196_so),
.X (o_196)
) ;
// Output pad for o_197 (mc_memaddr[10])
MEM_OUT o_197_pad(
.OT (o_197_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_196_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_197_so),
.X (o_197)
) ;
// Output pad for o_198 (mc_memaddr[11])
MEM_OUT o_198_pad(
.OT (o_198_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_197_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_198_so),
.X (o_198)
) ;
// Dummy pad vdd_199 ()
// vss
// Dummy pad vss_200 ()
// vss
// Output pad for o_201 (mc_mwe_l)
MEM_OUT o_201_pad(
.OT (o_201_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_198_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_201_so),
.X (o_201)
) ;
// Output pad for o_202 (mc_cas_l[0])
MEM_OUT o_202_pad(
.OT (o_202_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_201_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_202_so),
.X (o_202)
) ;
// Output pad for o_203 (mc_cas_l[1])
MEM_OUT o_203_pad(
.OT (o_203_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_202_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_203_so),
.X (o_203)
) ;
// Output pad for o_204 (mc_cas_l[2])
MEM_OUT o_204_pad(
.OT (o_204_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_203_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_204_so),
.X (o_204)
) ;
// Dummy pad vdd_205 ()
// vdd
// Dummy pad vss_206 ()
// vss
// Output pad for o_207 (mc_cas_l[3])
MEM_OUT o_207_pad(
.OT (o_207_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_204_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_207_so),
.X (o_207)
) ;
// Output pad for o_208 (mc_ras_l[0])
MEM_OUT o_208_pad(
.OT (o_208_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_207_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_208_so),
.X (o_208)
) ;
// Output pad for o_209 (mc_ras_l[1])
MEM_OUT o_209_pad(
.OT (o_209_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_208_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_209_so),
.X (o_209)
) ;
// Output pad for o_210 (mc_ras_l[2])
MEM_OUT o_210_pad(
.OT (o_210_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_209_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_210_so),
.X (o_210)
) ;
// Dummy pad vdd2_211 ()
// vdd
// Dummy pad vss2_212 ()
// vss
// Output pad for o_213 (mc_ras_l[3])
MEM_OUT o_213_pad(
.OT (o_213_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_210_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_213_so),
.X (o_213)
) ;
// Output pad for o_214 (mc_ras_l[4])
MEM_OUT o_214_pad(
.OT (o_214_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_213_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_214_so),
.X (o_214)
) ;
// Output pad for o_215 (mc_ras_l[5])
MEM_OUT o_215_pad(
.OT (o_215_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_214_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_215_so),
.X (o_215)
) ;
// Output pad for o_216 (mc_ras_l[6])
MEM_OUT o_216_pad(
.OT (o_216_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_215_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_216_so),
.X (o_216)
) ;
// Dummy pad vdd_217 ()
// vdd
// Dummy pad vss_218 ()
// vss
// Output pad for o_219 (mc_ras_l[7])
MEM_OUT o_219_pad(
.OT (o_219_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_216_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_219_so),
.X (o_219)
) ;
// Output pad for o_220 (mc_moe_l)
MEM_OUT o_220_pad(
.OT (o_220_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_219_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_220_so),
.X (o_220)
) ;
// Non-scanned input pad for i_tn_221 (tn)
IBUF i_tn_221_pad(
.a (i_tn_221),
.pi (1'b1),
.po (i_tn_221_po),
.z (i_tn_221_i)
) ;
// Non-scanned input pad for i_ns_222 (iiddtn)
// fix for release 1.0 no parametric tree on this!
TEST_IN i_ns_222_pad(
.X (i_ns_222),
// .PI (pi_in),
.PI (1'b1),
.PO (i_ns_222_po),
.IT (i_ns_222_i)
) ;
// Dummy pad vdd_223 ()
// vdd
// Dummy pad vss_224 ()
// vss
// Input pad for i_225 (simm32_sel)
MEM_IN_PD i_225_pad(
.X (i_225),
.SHIFT (bscan_shift),
.SI (o_220_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_in),
// .PI (i_ns_222_po),
.PI (pi_in),
.PO (i_225_po),
.SO (i_225_so),
.IT (i_225_i)
) ;
// Dummy pad vdd_226 ()
// vdd
// Non-scanned input pad for i_td_227 (therm_d)
DDRV i_td_227_pad(
.A (i_td_227),
.Z (i_td_227_i)
) ;
// Bidirectional pad for b_228 (b_mempar[0]), enabled by b_mem_oen
PCI_BI b_228_pad(
.ENC_ (b_mem_oen_enc_l),
.OT (b_228_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (i_225_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (i_225_po),
.PO (b_228_po),
.SO (b_228_so),
.IT (b_228_i),
.X (b_228)
) ;
// Bidirectional pad for b_229 (b_mempar[1]), enabled by b_mem_oen
PCI_BI b_229_pad(
.ENC_ (b_mem_oen_enc_l),
.OT (b_229_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_228_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_228_po),
.PO (b_229_po),
.SO (b_229_so),
.IT (b_229_i),
.X (b_229)
) ;
// Dummy pad vdd_230 ()
// vdd
// Dummy pad vss_231 ()
// vss
// Dummy pad vdd2_232 ()
// vdd
// Tristate enable cell for b_mem_oen
ENABLE b_mem_oen_cell(
.EN (b_mem_oen),
.SHIFT (bscan_shift),
.SI (b_229_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (b_mem_oen_enc_l),
.SO (b_mem_oen_so)
) ;
// Bidirectional pad for b_233 (b_memdata[0]), enabled by b_mem_oen
PCI_BI b_233_pad(
.ENC_ (b_mem_oen_enc_l),
.OT (b_233_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_mem_oen_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_229_po),
.PO (b_233_po),
.SO (b_233_so),
.IT (b_233_i),
.X (b_233)
) ;
// Bidirectional pad for b_234 (b_memdata[1]), enabled by b_mem_oen
PCI_BI b_234_pad(
.ENC_ (b_mem_oen_enc_l),
.OT (b_234_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_233_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_233_po),
.PO (b_234_po),
.SO (b_234_so),
.IT (b_234_i),
| This page: |
Created: | Thu Aug 19 11:59:50 1999 |
| From: |
../../../sparc_v8/ssparc/iopads/rtl/rightpads.v
|