output S
, CO
;
input A
, B
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$CO = 0;
parameter
CLOAD$S = 0;
xor #(0.0,0.0)
(S, A, B);
and #(0.0,0.0)
(CO, A, B);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: C004GBVA.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module C004GBVA
(S,CO,A);
output S
,CO
;
input A
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$CO = 0;
parameter
CLOAD$S = 0;
buf #(0.0, 0.0)
( CO, A);
not #(0.0, 0.0)
( S, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: C004VA.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module C004VA
(S,CO,A,B);
output S
, CO
;
input A
, B
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$CO = 0;
parameter
CLOAD$S = 0;
xnor #(0.0,0.0)
( S, A, B);
or #(0.0,0.0)
( CO, A, B);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: CLKC12IDR.v,v 1.1 1995/10/31 01:58:31 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module CLKC12IDR
( Z, A);
output Z
;
input A
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
not #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: CLKC16IDR.v,v 1.1 1995/10/31 01:58:33 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module CLKC16IDR
( Z, A);
output Z
;
input A
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
not #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: CLKC2IDR.v,v 1.1 1995/10/31 01:58:34 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module CLKC2IDR
( Z, A);
output Z
;
input A
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
not #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: CLKC4IDR.v,v 1.1 1995/10/31 01:58:36 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module CLKC4IDR
( Z, A);
output Z
;
input A
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
not #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: CLKC8IDR.v,v 1.1 1995/10/31 01:58:37 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module CLKC8IDR
( Z, A);
output Z
;
input A
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
not #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: CMP1C.v,v 1.3 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module CMP1C
(Z,A,B,EN);
output Z
;
input A
, B
, EN
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
not (CT1N, CT1);
bufif1 #(0.0, 0.0)
( Z, CT1N, CT1);
xor (CT0, A, B);
not (ENN, EN);
and (CT1, CT0, ENN);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: CSAHB.v,v 1.6 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module CSAHB
(CO0,CO1,S,A,B,CI0,CI1,CS);
output CO0
, CO1
, S
;
input CI0
, CI1
, A
, B
, CS
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$CO = 0;
parameter
CLOAD$S = 0;
not (CI0N, CI0);
not (CI1N, CI1);
xor
( AXB, A, B);
xor
( CI0NXAXB, CI0N, AXB);
xor
( CI1NXAXB, CI1N, AXB);
CSL_MUX21
M1 (ST
, CI0NXAXB
, CI1NXAXB
, CS);
buf #(0.0,0.0)
( S, ST);
not
( CI0N, CI0);
not
( CI1N, CI1);
CSL_MUX21 #(0.0,0.0)
M2 (CO0, B, CI0N
, AXB
);
CSL_MUX21 #(0.0,0.0)
M3 (CO1, B, CI1N
, AXB);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: CSALB.v,v 1.5 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module CSALB
(CO0,CO1,S,A,B,CI0,CI1,CS);
output CO0
, CO1
, S
;
input CI0
, CI1
, A
, B
, CS
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$CO = 0;
parameter
CLOAD$S = 0;
xor
( AXB, A, B);
xor
( CI0XAXB, CI0, AXB);
xor
( CI1XAXB, CI1, AXB);
CSL_MUX21
M1 (ST
, CI0XAXB
, CI1XAXB
, CS);
buf #(0.0,0.0)
( S, ST);
not
( BN, B);
not
( CI0N, CI0);
not
( CI1N, CI1);
CSL_MUX21 #(0.0,0.0)
M2 (CO0, BN
, CI0N
, AXB
);
CSL_MUX21 #(0.0,0.0)
M3 (CO1, BN, CI1N
, AXB);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: DDRV.v,v 1.1 1995/04/29 02:46:09 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module DDRV
(Z,A);
output Z
;
input A
;
parameter
CMOS_TO_TTL$Z = 1;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
(Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: DDRVO.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module DDRVO
(Z,A);
output Z
;
input A
;
parameter
CMOS_TO_TTL$Z = 1;
parameter
CLOAD$Z = 85;
buf #(0.0, 0.0)
(Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: DDRVPD.v,v 1.1 1995/10/31 01:58:39 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module DDRVPD
(Z,A);
output Z
;
input A
;
parameter
CMOS_TO_TTL$Z = 1;
parameter
CLOAD$Z = 85;
buf #(0.0, 0.0)
(Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: DDRVPU.v,v 1.1 1995/10/31 01:58:41 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module DDRVPU
(Z,A);
output Z
;
input A
;
parameter
CMOS_TO_TTL$Z = 1;
parameter
CLOAD$Z = 85;
buf #(0.0, 0.0)
(Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: DEL05.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module DEL05
( Z, A);
output Z
;
input A
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: DEL1.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module DEL1
( Z, A);
output Z
;
input A
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: DEL2.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module DEL2
( Z, A);
output Z
;
input A
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: DEL4.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module DEL4
( Z, A);
output Z
;
input A
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: DIFH2C.v,v 1.3 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module DIFH2C
(Z,A,IDDTN);
output Z
;
input A
,IDDTN
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
CSL_MUX21 #(0.0, 0.0)
M1 (Z, 1'b1, A, IDDTN);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: EN3A.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module EN3A
(Z, A, B, C);
output Z
;
input A
, B
, C
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
xnor #(0.0, 0.0)
( Z, A, B, C);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: EN3B.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module EN3B
(Z, A, B, C);
output Z
;
input A
, B
, C
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
xnor #(0.0, 0.0)
( Z, A, B, C);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: EN3C.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module EN3C
(Z, A, B, C);
output Z
;
input A
, B
, C
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
xnor #(0.0, 0.0)
( Z, A, B, C);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: ENA.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
![[Up: spares spare_xnor1]](v2html-up.gif)
![[Up: spares spare_xnor2]](v2html-up.gif)
![[Up: spares spare_xnor3]](v2html-up.gif)
![[Up: spares spare_xnor4]](v2html-up.gif)
![[Up: spares spare_xnor5]](v2html-up.gif)
![[Up: spares spare_xnor6]](v2html-up.gif)
![[Up: spares spare_xnor7]](v2html-up.gif)
![[Up: spares spare_xnor8]](v2html-up.gif)
![[Up: spares spare_xnor9]](v2html-up.gif)
module ENA
(Z, A, B);
output Z
;
input A
, B
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
xnor #(0.0, 0.0)
( Z, A, B);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: ENB.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module ENB
(Z, A, B);
output Z
;
input A
, B
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
xnor #(0.0, 0.0)
( Z, A, B);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: ENC.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module ENC
(Z, A, B);
output Z
;
input A
, B
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
xnor #(0.0, 0.0)
( Z, A, B);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: ENL.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module ENL
(Z, A, B);
output Z
;
input A
, B
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
xnor #(0.0, 0.0)
( Z, A, B);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: EO1A.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module EO1A
(Z, A, B, C, D);
output Z
;
input A
, B
, C
, D
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
and ( CT0, A, B);
nor ( CT1, C, D);
nor #(0.0, 0.0)
( Z, CT0, CT1);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: EO1B.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module EO1B
(Z, A, B, C, D);
output Z
;
input A
, B
, C
, D
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
and ( CT0, A, B);
nor ( CT1, C, D);
nor #(0.0, 0.0)
( Z, CT0, CT1);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: EO1C.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module EO1C
(Z, A, B, C, D);
output Z
;
input A
, B
, C
, D
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
and ( CT0, A, B);
nor ( CT1, C, D);
nor #(0.0, 0.0)
( Z, CT0, CT1);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: EO3A.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module EO3A
(Z, A, B, C);
output Z
;
input A
, B
, C
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
xor #(0.0, 0.0)
( Z, A, B, C);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: EO3B.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module EO3B
(Z, A, B, C);
output Z
;
input A
, B
, C
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
xor #(0.0, 0.0)
( Z, A, B, C);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: EO3C.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module EO3C
(Z, A, B, C);
output Z
;
input A
, B
, C
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
xor #(0.0, 0.0)
( Z, A, B, C);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: EOA.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module EOA
(Z, A, B);
output Z
;
input A
, B
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
xor #(0.0, 0.0)
( Z, A, B);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: EOB.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module EOB
(Z, A, B);
output Z
;
input A
, B
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
xor #(0.0, 0.0)
( Z, A, B);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: EOC.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module EOC
(Z, A, B);
output Z
;
input A
, B
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
xor #(0.0, 0.0)
( Z, A, B);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: EON1A.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module EON1A
(Z, A, B, C, D);
output Z
;
input A
, B
, C
, D
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
or ( CT0, A, B);
nand ( CT1, C, D);
nand #(0.0, 0.0)
( Z, CT0, CT1);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: EON1B.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module EON1B
(Z, A, B, C, D);
output Z
;
input A
, B
, C
, D
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
or ( CT0, A, B);
nand ( CT1, C, D);
nand #(0.0, 0.0)
( Z, CT0, CT1);
endmodule
This page: |
Created: | Thu Aug 19 12:01:25 1999 |
| From: |
../../../sparc_v8/lib/rtl/csl_lib.v
|