/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
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/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)rl_asi_cntl.v
***
****************************************************************************
****************************************************************************/
//***********************************************************************
// @(#)rl_asi_cntl.v 1.62 4/20/93
//
// Description:
// ASI decoder
//
//***********************************************************************
/* functional model of MMU ASI Controller */
module rl_asi_cntl
(
ic_asi,
dc_asi,
probe_in,
flush_in,
asi_dcd3,
asi_dcd3_w,
asi_dcd4,
asi_dcd6,
asi_dcd8_or_9,
asi_dcd9,
mmasi,
asi_write,
mmu_asi,
flush_tlb_pte,
flush_tlb_seg,
flush_tlb_reg,
flush_tlb_ctx,
flush_tlb_all,
bypass_mmu_asi_w,
cntrl_spc_err,
probe,
flush,
probe_entire,
probe_lvl0,
probe_lvl1,
probe_lvl2,
probe_lvl3,
normal_asi_w,
wb_3_asi,
dc_miss_sustain,
asi_e,
asi_w,
size_w,
iu_size_e,
read_w,
last_st_w,
st_miss_x,
r_ldsto_w,
iu_dva,
iu_pipe_hold,
wb_valid_x,
wb_valid_t,
wr_tlb,
asi_done,
r_trap,
ok_2_probe,
mmu_asi_op, // ASI_OP state in par_cntl sm
asidcd_mask, // Mask non-device ASIs
ss_clock,
ss_scan_mode,
ss_reset);
output normal_asi_w
; // indicates that we are in W-stage of asi = 8,9,A, or B
output ic_asi
; // indicates that ic_tag and icst signal valid
output dc_asi
; // indicates that dc_tag and icst signal valid
output asi_dcd3
; // indicates asi probe/flush
output asi_dcd3_w
; // indicates asi probe/flush (non-qualified)
output asi_dcd4
; // indicates asi mmu register decode
output asi_dcd6
; // indicates asi mmu tlb, itbr decode
output asi_dcd8_or_9
; // indicates Data instruction space access (user)
output asi_dcd9
; // indicates Data instruction space access (supervisor)
output mmasi
; // indicates asi ld or st
output asi_write
; // indicates asi st to mmu
output mmu_asi
; // indicates asi ld or st to mmu
output flush_tlb_pte
; // indicates one pte to be flushed
output flush_tlb_seg
; // indicates one segement to be flushed
output flush_tlb_reg
; // indicates one region to be flushed
output flush_tlb_ctx
; // indicates one context to be flushed
output flush_tlb_all
; // indicates entire tlb to be flushed
output bypass_mmu_asi_w
; // asi 20 indicating mmu bypass
output cntrl_spc_err
; // improper asi
output probe
;
output flush
;
output probe_in
;
output flush_in
;
output probe_entire
;
output probe_lvl0
;
output probe_lvl1
;
output probe_lvl2
;
output probe_lvl3
;
input [1:0] wb_3_asi
; // asi field from wb
input [5:0] asi_e
; // asi field from iu
input [5:0] asi_w
; // asi field from iu
input [1:0] size_w
; // size field from iu
input [1:0] iu_size_e
; // size field from iu
input dc_miss_sustain
; // dc_miss sustained signal
input wb_valid_x
; // write buffer has valid entry (execute stage)
input wb_valid_t
; // write buffer has valid entry (translate stage)
input wr_tlb
; // par state WR_TLB
input read_w
; // read field from iu
input last_st_w
; // last st in write buffer and W-stage
input st_miss_x
; // st miss in write buffer and W-stage
input r_ldsto_w
; // ldsto field from iu
input [12:08] iu_dva
; // relevant portion of d virt addr from iu
input iu_pipe_hold
; // signal for holding the iu pipeline
input asi_done
; // asi op complete
input r_trap
; // registered trap signal
input ok_2_probe
;
input mmu_asi_op
;
input asidcd_mask
;
input ss_clock
; // input clock
input ss_scan_mode
; // input clock
input ss_reset
; // input reset
wire bypass_mmu_asi_e
;
wire asi_dcd3_e
;
wire asi_dcd4_e
;
wire asi_dcd6_e
;
wire mmasi_w
;
wire dc_asi_w
;
wire ic_asi_w
;
wire ic_asi;
wire flush_tlb_pte_in
;
wire flush_tlb_seg_in
;
wire flush_tlb_reg_in
;
wire flush_tlb_ctx_in
;
wire flush_tlb_all_in
;
wire probe_entire_in
;
wire probe_lvl0_in
;
wire probe_lvl1_in
;
wire probe_lvl2_in
;
wire probe_lvl3_in
;
wire cs_err_dcd_in
;
wire ldd_first_read
;
wire r_pipe_hold
;
Mflipflop_r_1 pipe_hold_ff_1(r_pipe_hold,iu_pipe_hold,~ss_reset,ss_clock) ;
/*** Chop back end of pipe_held, once asi op completed ******************/
wire pipe_held
= r_pipe_hold & ~asi_done ;
/******************************************************************************/
/*** Non-Device ASI decodes ***************************************************/
wire asi_dcd3_w;
MflipflopR_1 asi_dcd3_ff_1(asi_dcd3_w,asi_dcd3_e,ss_clock,iu_pipe_hold,ss_reset) ;
assign asi_dcd3 = asi_dcd3_w & ~asidcd_mask & (size_w == 2'b10) & ~r_ldsto_w;
wire asi_dcd4_w
;
MflipflopR_1 asi_dcd4_ff_1(asi_dcd4_w,asi_dcd4_e,ss_clock,iu_pipe_hold,ss_reset) ;
assign asi_dcd4 = mmu_asi_op & asi_dcd4_w & ~asidcd_mask ;
wire asi_dcd6_w
;
MflipflopR_1 asi_dcd6_ff_1(asi_dcd6_w,asi_dcd6_e,ss_clock,iu_pipe_hold,ss_reset) ;
/*** OR on ss_scan mode to force cxr_mux_sel during scan mode ****************/
assign asi_dcd6 = (mmu_asi_op & asi_dcd6_w & ~asidcd_mask) | ss_scan_mode;
/******************************************************************************/
/*** Probe decode registers ***************************************************/
wire r_probe
;
MflipflopR_1 probe_ff_1(r_probe,probe_in,ss_clock,pipe_held,ss_reset) ;
assign probe = r_probe & ok_2_probe;
wire r_probe_entire
;
MflipflopR_1 probe_entire_ff_1(r_probe_entire,probe_entire_in,ss_clock,pipe_held,ss_reset) ;
assign probe_entire = r_probe_entire & ok_2_probe;
wire r_probe_lvl0
;
MflipflopR_1 probe_lvl0_ff_1(r_probe_lvl0,probe_lvl0_in,ss_clock,pipe_held,ss_reset) ;
assign probe_lvl0 = r_probe_lvl0 & ok_2_probe;
wire r_probe_lvl1
;
MflipflopR_1 probe_lvl1_ff_1(r_probe_lvl1,probe_lvl1_in,ss_clock,pipe_held,ss_reset) ;
assign probe_lvl1 = r_probe_lvl1 & ok_2_probe;
wire r_probe_lvl2
;
MflipflopR_1 probe_lvl2_ff_1(r_probe_lvl2,probe_lvl2_in,ss_clock,pipe_held,ss_reset) ;
assign probe_lvl2 = r_probe_lvl2 & ok_2_probe;
wire r_probe_lvl3
;
MflipflopR_1 probe_lvl3_ff_1(r_probe_lvl3,probe_lvl3_in,ss_clock,pipe_held,ss_reset) ;
assign probe_lvl3 = r_probe_lvl3 & ok_2_probe;
wire r_flush
;
MflipflopR_1 flush_ff_1(r_flush,flush_in,ss_clock,pipe_held,ss_reset) ;
wire r_flush_tlb_pte
;
MflipflopR_1 flush_tlb_pte_ff_1(r_flush_tlb_pte,flush_tlb_pte_in, ss_clock,pipe_held,ss_reset) ;
wire r_flush_tlb_seg
;
MflipflopR_1 flush_tlb_seg_ff_1(r_flush_tlb_seg,flush_tlb_seg_in, ss_clock,pipe_held,ss_reset) ;
wire r_flush_tlb_reg
;
MflipflopR_1 flush_tlb_reg_ff_1(r_flush_tlb_reg,flush_tlb_reg_in, ss_clock,pipe_held,ss_reset) ;
wire r_flush_tlb_ctx
;
MflipflopR_1 flush_tlb_ctx_ff_1(r_flush_tlb_ctx,flush_tlb_ctx_in, ss_clock,pipe_held,ss_reset) ;
wire r_flush_tlb_all
;
MflipflopR_1 flush_tlb_all_ff_1(r_flush_tlb_all,flush_tlb_all_in, ss_clock,pipe_held,ss_reset) ;
wire cs_err_dcd
;
MflipflopR_1 cntrl_spc_err_ff_1(cs_err_dcd,cs_err_dcd_in,ss_clock, 1'b0,ss_reset) ;
// generate register version of cs_err_dcd to output to mmu_regs module
wire r_cs_err_dcd
;
MflipflopR_1 r_cntrl_spc_err_ff_1(r_cs_err_dcd,cs_err_dcd,ss_clock, 1'b0,ss_reset) ;
wire cs_err_mask_hld
= ~(cntrl_spc_err | ~r_pipe_hold) ;
wire cs_err_mask
;
MflipflopR_1 cs_err_msk_ff_1(cs_err_mask,r_cs_err_dcd,ss_clock, cs_err_mask_hld,ss_reset) ;
wire r_wb_hit_x_in
= ~(wb_valid_x & ~last_st_w);
wire r_wb_hit_x
;
Mflipflop_r_1 r_wb_hit_x_ff_1(r_wb_hit_x,r_wb_hit_x_in,~ss_reset, ss_clock) ;
assign cntrl_spc_err = r_cs_err_dcd & ~cs_err_mask & dc_miss_sustain &
r_wb_hit_x ;
/*** mmasi decode indicates ASI operation pending - *************************/
/*** needs PAR state machine to recognize this signal, and returns ****/
/*** mmu_asi_op. The operation is terminated by asi_done. ****/
assign mmasi = (mmasi_w & ~asi_done & (dc_miss_sustain | mmu_asi_op) &
(read_w & ~wb_valid_x | last_st_w | dc_asi));
assign mmu_asi = mmu_asi_op & (asi_dcd4_w | asi_dcd6_w) & ~r_trap ;
assign ic_asi = (mmu_asi_op & ic_asi_w & ~r_trap);
assign dc_asi = (mmu_asi_op & dc_asi_w & ~r_trap);
/*** flush decodes **********************************************************/
assign flush_tlb_pte = (r_flush_tlb_pte & ~r_trap & st_miss_x);
assign flush_tlb_seg = (r_flush_tlb_seg & ~r_trap & st_miss_x);
assign flush_tlb_reg = (r_flush_tlb_reg & ~r_trap & st_miss_x);
assign flush_tlb_ctx = (r_flush_tlb_ctx & ~r_trap & st_miss_x);
assign flush_tlb_all = (r_flush_tlb_all & ~r_trap & st_miss_x);
assign flush = (r_flush & ~r_trap & st_miss_x);
assign flush_tlb_pte_in = asi_dcd3_w & (iu_dva[11:08] == 4'h0) & (size_w == 2'b10);
assign flush_tlb_seg_in = asi_dcd3_w & (iu_dva[11:08] == 4'h1) & (size_w == 2'b10);
assign flush_tlb_reg_in = asi_dcd3_w & (iu_dva[11:08] == 4'h2) & (size_w == 2'b10);
assign flush_tlb_ctx_in = asi_dcd3_w & (iu_dva[11:08] == 4'h3) & (size_w == 2'b10);
assign flush_tlb_all_in = asi_dcd3_w & (iu_dva[11:08] == 4'h4) & (size_w == 2'b10);
assign flush_in = flush_tlb_pte_in | flush_tlb_seg_in |
flush_tlb_reg_in | flush_tlb_ctx_in |
flush_tlb_all_in ;
/*** probe decodes ***********************************************************/
assign probe_in = ((asi_dcd3_w & read_w & (iu_dva[11:8] == 4'h4)) |
(asi_dcd3_w & read_w & (iu_dva[11:8] == 4'h3)) |
(asi_dcd3_w & read_w & (iu_dva[11:8] == 4'h2)) |
(asi_dcd3_w & read_w & (iu_dva[11:8] == 4'h1)) |
(asi_dcd3_w & read_w & (iu_dva[11:8] == 4'h0))) &
(size_w == 2'b10) & ~r_ldsto_w & ~asi_done & ~r_trap ;
assign probe_entire_in = asi_dcd3_w & read_w & (iu_dva[11:8] == 4'h4) &
~asi_done & ~r_trap ;
assign probe_lvl0_in = asi_dcd3_w & read_w & (iu_dva[11:8] == 4'h3) &
~asi_done & ~r_trap ;
assign probe_lvl1_in = asi_dcd3_w & read_w & (iu_dva[11:8] == 4'h2) &
~asi_done & ~r_trap ;
assign probe_lvl2_in = asi_dcd3_w & read_w & (iu_dva[11:8] == 4'h1) &
~asi_done & ~r_trap ;
assign probe_lvl3_in = asi_dcd3_w & read_w & (iu_dva[11:8] == 4'h0) &
~asi_done & ~r_trap ;
/*****************************************************************************/
assign asi_dcd3_e = (asi_e == 6'h03);
assign asi_dcd4_e = (asi_e == 6'h04);
assign asi_dcd6_e = (asi_e == 6'h06);
/*** Indicates ASI store in progress - gated with mmstben in rl_va_mux *******/
assign asi_write = (asi_dcd3_w | asi_dcd4_w | asi_dcd6_w) & st_miss_x;
/*** Normal ASI decode (device space) ****************************************/
wire normal_asi_e
= (asi_e == 6'h08) | (asi_e == 6'h09) |
(asi_e == 6'h0A) | (asi_e == 6'h0B) |
(asi_e == 6'h20) |
((asi_e == 6'h03) & (iu_size_e == 2'b10));
/*** Write buffer ASI does NOT decode "normal", since only store hits ***/
/*** are in the write buffer ***/
wire normal_asi_w;
MflipflopR_1 normal_asi_w_ff_1(normal_asi_w,normal_asi_e,ss_clock,iu_pipe_hold,ss_reset) ;
/*****************************************************************************/
assign bypass_mmu_asi_e = (asi_e == 6'h20);
wire bypass_mmu_asi_w;
MflipflopR_1 bypass_mmu_ff_1(bypass_mmu_asi_w,bypass_mmu_asi_e,ss_clock,iu_pipe_hold,ss_reset) ;
/*********** decode for asi dcd 9 ******************************/
wire asi_dcd9_wb_in
= (wb_3_asi == 2'h1) ;
wire asi_dcd9_wb
;
Mflipflop_r_1 asi_dcd9_wb_ff_1(asi_dcd9_wb,asi_dcd9_wb_in,~ss_reset,ss_clock) ;
wire asidcd9_e
= (asi_e == 6'h9) ;
wire asi_dcd9_w_in
;
MflipflopR_1 asidcd9_w_ff_1(asi_dcd9_w_in,asidcd9_e,ss_clock,iu_pipe_hold,ss_reset) ;
assign asi_dcd9 = wr_tlb ? asi_dcd9_wb : asi_dcd9_w_in ;
/************* decode for asi dcd 8 ***************************/
wire asi_dcd89_wb_in
= ((wb_3_asi == 2'h0) | (wb_3_asi == 2'h1)) ;
wire asi_dcd89_wb
;
Mflipflop_r_1 asi_dcd89_wb_ff_1(asi_dcd89_wb,asi_dcd89_wb_in,~ss_reset,ss_clock) ;
wire asidcd89_e
= ((asi_e == 6'h8) | (asi_e == 6'h9)) ;
wire asi_dcd89_w_in
;
MflipflopR_1 asidcd89_w_ff_1(asi_dcd89_w_in,asidcd89_e,ss_clock,iu_pipe_hold,ss_reset) ;
assign asi_dcd8_or_9 = wr_tlb ? asi_dcd89_wb : asi_dcd89_w_in ;
assign cs_err_dcd_in = dc_miss_sustain & ((~(asi_w == 6'h08 |
asi_w == 6'h09 | asi_w == 6'h0A |
asi_w == 6'h0B | asi_w == 6'h20) & r_ldsto_w) |
(asi_dcd3_w & (size_w == 2'b10) &
(iu_dva[11:8] > 4'h4)) |
((asi_w == 6'h04) & (size_w == 2'b10) &
((iu_dva > 5'h04) &
~((iu_dva == 5'h10) | (iu_dva == 5'h13) |
(iu_dva == 5'h14)))) |
((size_w != 2'b10) &
(asi_dcd3_w | asi_dcd4_w | asi_dcd6_w |
(asi_w == 6'h0C) | (asi_w == 6'h0D) |
(asi_w == 6'h0E) | (asi_w == 6'h39))) |
~(asi_dcd3_w | asi_dcd4_w | asi_dcd6_w |
((asi_w >= 6'h08) & (asi_w <= 6'h14)) |
(asi_w == 6'h20) | (asi_w == 6'h39))) ;
assign dc_asi_w = ((asi_w == 6'h39) | (asi_w == 6'h0E)) ;
assign ic_asi_w = ((asi_w == 6'h0C) | (asi_w == 6'h0D)) ;
assign mmasi_w = (size_w == 2'b10) & ~r_ldsto_w &
((asi_dcd4_w &
((iu_dva <= 5'h04) | (iu_dva == 5'h10) |
(iu_dva == 5'h13) | (iu_dva == 5'h14))) |
(((~wb_valid_x & read_w) | st_miss_x) & (size_w == 2'b10) &
(asi_dcd6_w | (asi_w == 6'h0C) |
(asi_w == 6'h0D) | (asi_w == 6'h0E) |
(asi_w == 6'h39)))) ;
endmodule
This page: |
Created: | Thu Aug 19 12:03:17 1999 |
| From: |
../../../sparc_v8/ssparc/mmu/m_mmu_cntl/rtl/rl_asi_cntl.v
|